Feed-forward Modulators Topologies Design for

Broadband Communications Applications

Houda Daoud, IEEE Student Member, Samir Ben salem, IEEE Member, Sonia Zouari, IEEE Student Member and
Mourad Loulou, IEEE Senior Member
Information Technologies and Electronics Laboratory
National Engineering School of Sfax, B.P.W, Sfax, Tunisia
Emails: daoud.houda@tunet.tn, benselem.samir@gmail.com, sonia.zouari@enis.rnu.tn, mourad.loulou@ieee.org
The SC technique makes the CMOS analog circuits
design more accurate and robust. In this context,
performances objectives of 2MHz/ 10MHz signals
bandwidths and 10bits/ 8-11bits resolutions are assumed in
this work in order to fulfill the requirements of WCDMA
and WLAN standards [4]. To achieve the targeted
performances objectives, folded cascode and telescopic
gain-boosted OTAs architectures optimizing through
Heuristic Algorithm are investigated to design a 2nd order
and a 2-2 cascaded feed-forward modulators topologies
which are highly suitable for wide band radio applications.
This paper describes a methodology to design lowdistortion modulators for wide bandwidths. The SC
integrator is implemented using the optimized OTA
circuits. The paper is organized as follows. Section II
presents the design methodology for modulator. In
section III, the performances of folded cascode and
telescopic gain-boosting OTAs circuits optimized via
Heuristic Algorithm are introduced. The implementation of
2nd order and 2-2 cascaded feed-forward modulators
topologies for wide bandwidths is presented in section IV.
Finally, conclusions are reported in section V.

AbstractThis paper presents a design methodology for lowdistortions (feed-forward) Delta-Sigma () modulators
topologies used in next generations wireless applications.
Thus, optimized folded cascode OTA and telescopic OTA
gain-boosting are selected to implement the switched capacitor
(SC) integrator. First, a second order modulator is
implemented for 2MHz bandwidth. Second, a 2-2 cascaded
modulator is designed for 2MHz and 10MHz bandwidths in
order to improve the modulator performances. These
modulators are implemented using system-level simulations as
well as device-level simulations implemented with SC circuits
in AMS 0.35m CMOS process. Device-level simulations
results indicate that the 2nd and the 2-2 cascaded
modulators achieve respectively SNRs of 43dB and 38dB over
bandwidths of 2MHz and 10MHz with over-sampling ratios
16 and 8.
Key words: modulator design, feed-forward signal path,
folded cascode OTA, telescopic OTA gain-boosted,
optimization, large bandwidth.

I.

INTRODUCTION

The rapid growth in wireless communication systems

requiring higher capacities and data rates has motivated the
development of new generation wireless transceivers. To
face the requirements of new forthcoming protocols,
flexible receiver architecture is implemented using the
software defined radio (SDR) [1, 2]. The SDR aims to
performing the signal digitalization as near as possible to
the antenna, hence the digital programmable hardware,
such as digital signal processors (DSPs) can be used, but
circuits requirements are increased. To alleviate the analog
circuits demands, the downconversion is performed into
the baseband. The analog/digital converter (ADC) which is
the final analog block of an analog baseband front-end
receiver, directly influences its performances. Among the
diversity of ADCs architectures, modulator is the most
promising candidate to meet the needs of emerging multimode receivers [3]. The objective of this work is to
evaluate the performances of wide band modulators
topologies when designed using optimized OTA circuits via
Heuristic program. In fact, with the intensive ongoing
research on modulators, data acquisition systems
require high-speed, high-resolution and low-power
converters that are more challenging for SDR
implementation to operate in large signal bandwidths.

978-1-4577-1846-5/11/$26.00 2011 IEEE

II.

DESIGN METHODOLOGY FOR MODULATORS

In this section, a design methodology is proposed to

determine the design parameters of each modulator
analog block. As it can be seen from fig. 1, firstly, we opt
for the modulator topology for the reason that it is
Order L

modulator
architecture

Resolution

Bandwidth
OSR

Clocks
Switches

Hysteresis

System - level
design

Number of bits B

Specifications
SC integrator
design

Comparator
design

Experimental results

Sampling frequency
Optimized coefficients
Optimized OTA

Power consumption

Device - level
design

Performances
comparisons

Figure 1. Flow chart design of modulator

69

robust to non-idealities of circuit components [5]. By

varying the order L and the number of bits B in the
quantizer, a wide band topology could be performed.
Secondly, we fix the specifications including the
bandwidth, the over-sampling ratio, the resolution and the
sampling frequency. Using optimized OTAs circuits, the
SC integrator is then implemented taking the clocks and
switches design and the optimized coefficients into
consideration. After designing the quantizer, the chosen
topology is simulated using MATLAB software and
ORCAD PSPICE (CMOS 0.35m process). Finally, a
comparison of modulator performances is made
between the two used tools.

phase. We conclude that the folded cascode OTA and

telescopic OTA gain-boosted circuits are optimized
respectively for medium and large bandwidths
modulators.
IV.

This work is focused on the design of modulators

for wide band applications. Table III summarizes the
channel bandwidth and resolution requirements provided
from performed researches on base-band ADC
specifications [4, 9, 10]. Traditional modulator architecture
is increasingly sensitive to circuits imperfections. Recently,
it has become very popular to make use of low-distortion
swing suppression modulator topology [11]. Fig. 3
depicts a 2nd order modulator with feed-forward signal
path that we choose because of its relaxed requirements on
the analog building blocks.

OPTIMIZED OTAS CIRCUITS SELECTION

III.

The OTA which constitute the core of the SC integrator

is the most critical block to implement performant
modulator [6]. Our objective is to select topologies that can
meet the integrator requirements at minimum power
consumption. First, both high output swing and low noise
allowed us to optimize the folded cascode OTA with
PMOS devices input shown in fig. 2 (a). Second, to obtain
the desired static gain, the gain-boosting technique is
adopted for telescopic OTA (Fig. 2 (b)) [7]. The two OTAs
circuits are optimized using the optimization process
described in [8]. The performances of folded cascode OTA
and telescopic OTA gain-boosted are respectively
summarized in table I and table II. The OTA circuit
performances collected in table II show that the use of gainboosting technique enables us to optimize high DC gain
and large GBW OTA circuit without scarifying its margin
M1

Ibias

M2

_
_ +

M4

Where X, Y and E represent respectively the input signal,

the output signal and the quantization noise. Both of
bandwidth and resolution are expressed by (2) and (3):

M5

A1

M5

Vout-

V2

Vout
Vin -

Vin +

(1)

fS
2OSR

(2)

V1

M3
Vout +

M8

V1

M 10

Y (z) = X + (1- z-1 ) E

B=

M7

M9

A. Second order feed-forward modulator design

Targeting on the requirements of broadband
telecommunication ADC, we want to design a 2nd order
modulator for 2MHz bandwidth (table III). The output of
the modulator is given by:

Vdd

Vdd

FEED-FORWARD MODULATORS
IMPLEMENTATION

ENOB =

M6

Vout

M8

M7

+
_

A2

V4
Vin +

Vss

M1

M2

Ibias

(a)

Vin _

FOM =

Figure 2. (a) Folded cascode OTA, (b) Telescopic OTA gain-boosted

TABLE I.
THE PERFORMANCES SUMMARY OF FOLDED CASCODE OTA
78
306
67
187
9.3
1.3

TABLE II.
THE PERFORMANCES SUMMARY OF TELESCOPIC GAINBOOSTED OTA
DC Gain (dB)
GBW (CL=2pF) (MHz)
Phase margin (degrees)
Slew Rate (V/s)
Power consumption (mW)
Supply voltage (V)

P
.2.BS

ENOB

(4)

Where P is the modulator power consumption. To achieve

the best performance and maintain loop stability, loop
coefficients must be optimized. We use the optimized loop
coefficients presented in table IV [12]. To perform a
system-level simulation of the modulator, the chosen
architecture was simulated using MATLAB blocks. Fig. 4
shows the output spectrum of the modulator for an input
frequency of 1MHz, a sampling frequency of 64MHz and
an OSR of 16. Simulation results indicate that the chosen
architecture achieves a SNR of 44.6dB and an ENOB of
7bits for 2MHz bandwidth. The linear model described in
fig. 3 is implemented into SC circuits, as represented in fig.
5 using AMS CMOS 0.35m process. The most important
building block of a modulator is the SC integrator. The
optimized folded cascode OTA is used to implement the
integrators.

(b)
Vss

DC Gain (dB)
GBW (CL=2pF) (MHz)
Phase margin (degrees)
Slew Rate (V/s)
Power consumption (mW)
Supply voltage (V)

(3)

Where fS, OSR and SNR are respectively the sampling

frequency, the over-sampling ratio and the signal-to-noise
ratio. The figure of merit is given by:

M4

M3

6.02

M6

V3

SNR (dB) -1.76

96
487
58
300
12
1.4

TABLE III.

WIRELESS COMMUNICATION ADC REQUIREMENTS

Channel bandwidth (MHz)
2
10

70

Resolution (Bits)
10
8-11

Vdd

z -1
1-z-1

a1

a2

z -1
1-z -1

c2

M11

M7

Vout

Vout +

F1

Vin +

M5

M1

M2

a = [0.3, 0.7]
c = [1, 1, 1, 2]
4
SNRp
OL
22
0.9
63
0.85

PSD (dB)

-20

PSD (dB)

-60
-80

Vin +

Vin

F1d

CS1

Cf1

F2
F2

F1d
F2d

CS1

Vref +

Cfd2

F2d

F1

Vref -

F 2d

OTA1
+
-

Cf1

F2d
F1d

CS2

F1d

F 2d

Cf2

F1

F2
F2

CS2

F1

OTA2
+
-

Cf2

F2

F1

Cfd1

S1

Cfd1

E1
a1

F2

z-1

a2

1-z-1

c2

z-1

1-z -1

digital cancellation

y1

Vout -

e1

e2 =

E2

Cf3

Vref -

a3

z-1
1-z-1

a4

z-1

c4
+

1-z -1

z -1

c1

F2

Cfd2

H1

z -1

Vout +

S1

F1d

Vref +

F1
F2

(5)

e2 is the digital coefficient. The high order modulator

increases circuits complexity and the requirements of
analog building blocks become more demanding for higher
sampling frequency. For wide bandwidth of 10MHz, the
OSR cannot be very high because the achievable clock
frequency is constrained by the process. The output
spectrum of the modulator is presented for a sampling
frequency of 160MHz, an OSR of 8 and 16384 samples
(Fig. 9). It reveals a SNR and an ENOB respectively of
about 50dB and 8bits. From fig. 9, the 8.5MHz input
frequency is chosen close to the 10MHz bandwidth to
further improve the modulator performances. The 2-2
cascaded feed-forward modulator has been designed
after, in AMS 0.35m CMOS process. In SC cascaded
modulators, the main non-idealities considered are finite
and non-linear DC gain, slew rate and gain-bandwidth
limitations, OTA saturation voltage, OTA input referred

Figure 4. PSD of the 2nd order modulator using MATLAB blocks

F1

2
6

x 10

Y (z ) = X (z ) z -2 + e 2 (1- z -1 ) E 2 (z )

-120

V ref +

0.5
1
1.5
Frequency (Hz)

B. 2-2 cascaded feed-forward modulator design

Cascaded modulators realize high-order noise
shaping by cascading stages of 2nd or 1st order to avoid
instability. Using loop coefficients collected in table V, the
simulation of the 2-2 cascaded feed-forward modulator
is carried out using a set of Simulink blocks (Fig. 8). The
output of the modulator is given by:

-100

F2d

Figure 7. PSD of the 2nd order single-bit modulator device-level

-40

Cf3

-60

-100

F1d

-40

-80

-20

0.5
1
1.5
Frequency (MHz)

Vin -

Figure 6. Regenerative quantizer

The switches used in the integrator are implemented with

CMOS transmission gate where two non-overlap clocks
phases are needed. In order to reduce the influence of
charge injection, a delayed signal is needed for each clock
phase. The quantizer presents a hysteresis of 976.7V/V
which is less than 0.5*LSB, a propagation time of 3.8ns
and a power consumption of 36.5pW (Fig. 6). The singlebit DAC is a simple switch network connected to reference
voltages. The values of sampling and integration capacitors
are (1pF, 1pF) and (3.3pF, 1.42pF). From fig. 7, the SNR
and the ENOB which values are respectively about of
43dB/ 3.3dBFS and 6.85bits are close to system-level
performances with an error deviation less than 4%. In 2nd
order single-loop modulators, stability can be easily
achieved and modulator performances are less sensitive to
OTA non-idealities [12]. In order to satisfy the large
bandwidth (10MHz) and the resolution requirements given
by table III, the modulator needs to be of order of three of
more. Unfortunately, high order single-stages
modulators suffer from stability issues, so they are replaced
by cascaded modulators to improve the SNR [14]. In the
next section, we will focus on the implementation of the 22 cascaded feed-forward modulator.

M4

M3
Vss

LOOP COEFFICIENTS FOR SINGLE-BIT FEED-FORWARD

MODULATOR
a = [0.3, 0.7]
c = [1, 1, 1]
3
SNRp
OL
41
0.85
63
0.85

M14

F1

M6

TABLE IV.

a = [0.3, 0.7]
c = [2, 1]
2
SNRp
OL
45
0.95
62
0.9

M13

F1

Figure 3. Low-distortion topology block diagram

Loop
coefficients
Loop order
OSR
16
32

M10

F1

M12

c1

M9

M8

y2

e2

1
a1a2e1
z -1

H2
z -1

c3

Vref +

nd

Figure 5. The 2 order feed-forward single-bit SC modulator

71

Figure 8. The 2-2 cascaded feed-forward modulator block diagram

TABLE V.

TABLE VI.

LOOP COEFFICIENTS FOR THE CASCADED 2-2 FEEDFORWARD SINGLE-BIT MODULATOR

Loop coefficients

SUMMARY OF SINGLE-BIT FEED-FORWARD MODULATOR

PERFORMANCES
Feed-forward
modulator topology

(a1, a2, a3, a4, c1, c2, c3, c4, e1, e2)
(0.4, 0.8, 0.4, 0.8, 2, 1, 2, 1, 1, 3.125)

OSR
16
32

SNRp
65
92

Signal Bandwidth (MHz)

Sampling frequency (MHz)
OSR
SNR
ENOB
Power consumption (mW)
FOM (pJ/conversion)
Process/ Supply voltage

PSD (dB)

PSD (dB)

-40
-60
-80

-120

-50

-100

-100
0

4
6
8
Frequency (MHz)

8.5
9
Frequency (MHz)

10

noise, kT/CS noise and capacitor mismatch which can

degrade the modulator performances. The used feedforward signal path has reduced sensitivity to OTA nonidealities. In addition, we use the optimized telescopic OTA
gain-boosted with low noise, high gain and slew rate and
large GBW that are sufficient to achieve best performances.
The values of sampling and integration capacitors of the
first stage are (1pF, 1pF) and (2.5pF, 1.25pF). Fig. 10
shows the modulator output spectrum for 10MHz/-3.6dBFS
at a sampling frequency of 160MHz. Simulations results
present a SNR and an ENOB respectively of about 38.3dB
and 6bits. Table VI resumes the performances of both of 2nd
order and 2-2 cascaded modulators. We point out that
the use of folded cascode OTA has allowed to achieve the
desired performance when designing the 2nd order
modulator. Despite the increase of modulator stages to
improve its performances, the capacitor mismatch between
stages and the non-linear capacity degrade them. The power
consumption is increased from 18.7mW to 48mW because
of the increased number of used OTAs and the high
sampling frequency that requires the design of large
bandwidth OTA circuit.

[2]
[3]
[4]

[5]

[6]

[7]

2nd order and 2-2 cascaded SC modulators have

been implemented in MATLAB software and AMS 0.35m
CMOS process for use in wireless receivers. The
modulators topologies involve two key design issues. One
is the modulator with feed-forward signal path, which
has reduced sensitivity to OTA non-idealities.

[8]

[9]

[10]

0
PSD (dB)

PSD (dB)

-20

-60
-80
-100

-20

[11]

-40

[12]

-60
-80

4
6
Frequency (Hz)

10

8
8.5
Frequency (Hz)

2
64
16
44.6
43
7
6.85
19
41
0.35m/ 2.6V

System
level

Device
level

10
160
8
50
38.3
8
6
48.3
37.7
0.35m/ 2.8V

REFERENCES
[1]

CONCLUSION

-40

Device
level

2-2 cascaded

The other key issue is the selected OTAs architectures

optimizing through Heuristic Algorithm to meet the
integrator requirements. For 2MHz bandwidth, systemlevel simulation results have confirmed that both SNR and
ENOB are approximately saved compared to device-level
simulation results of the 2nd order modulator. The 2-2
cascaded modulator implemented recurring to SC
circuits and simulated at device level consumes 48mW and
achieves SNR of about 38dB that is degraded compared
with system-level design. Future works would involve the
use of multi-bits quantizers to design wide band
modulator with high performances for flexible receivers.

Figure 9. PSD of the 2-2 cascaded modulator system-level

V.

System
level

Design mode

OL
0.95
0.89

-20

2nd order

[13]

9
6

x 10

[14]

x 10

Figure 10. PSD of the 2-2 cascaded modulator device-level

72

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