Desiree Ibon

861125598
EE 120A Section 24
Lab 5 --Datapath Components - Adders
Lab Partner: Claire Yang

Overview
This lab was intended to provided us familiarity with the design of adders and special purpose
registers. This is done through the design and implementation of an adder that adds together two
4 bit numbers. Using Xlinx to create a schematic, a user constraint file was then programmed
and loaded into Adept software to simulate the behavior of the adder on our Basys-2 FPGA
boards.
New Concepts
N-bit adder: adds two N-bit numbers plus a carry-in bit, resulting in an N-bit, sum and a carryout bit
full adder: adds three one-bit binary numbers and outputs two one-bit binary numbers, a sum
and a carry
DIP switch: manual electric switch on a circuit board
Analysis
Truth table for one bit adder
A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

C (in)
0
1
0
1
0
1
0
1

C(out)
0
0
0
1
0
1
1
1

Sum
0
1
1
0
1
0
0
1

The task in this lab was to implement a calculator that adds two 4-bit numbers by designing a
schematic in Xlinx software and verifying the design on a Basys-2 FPGA board. Before a
schematic could be designed, a truth table for a one bit adder was made. Using 4 one bit adders
in our schematic instead of one 4 bit adder reduced the amount of time spent designing our
schematic. As seen in Figure 1, a one bit adder consists of two inputs, a and b, a C(in), a C(out,
and sum variable. The one bit adder was created by passing in a, b, and c(in) into an XOR gate
which computed the sum. The carry out bit was also computed with the use of two AND gates,
an XOR gate which all fed into an OR gate. Once the one bit adder was created, we used the
schematic design utility function of Xlinx to create a new symbol for use in our lab 5 schematic.
In our 4 bit adder schematic, there are 4 one-bit adders, and 4 clock signals as seen in Figure 2. A

user constraints file was then created as seen in Figure 3 where we chose 4 LEDS and 8
switches for use in testing our design. A bit file was then generated and loaded into the Adept
software and our design was verified on our Basys-2 FPGA board.
Records
Schematics:

Figure 1:One bit adder

Figure 2:4-bit adder

User constraint file:

Figure 3: User constraints file

Discussion
For this lab, our design had worked as per the specifications in the lab manual. Initially, there
was trouble in creating the 4 bit adder schematic due to Xlinx not updating our schematic design
for the one bit adder for use in our large scale schematic. To fix this, we had created a

completely new lab file and a new schematic. Once we did this, our lab worked per the
specifications provided in the lab manual.
Conclusion
Through this lab, we gained familiarity with adders and special purpose registers. We were also
able to use our knowledge of the schematic design utility function in Xlinx to create a one bit
adder. By doing this, this was more efficient than creating a 4 bit adder.
Questions
n/a