Professional Documents
Culture Documents
Y-SUS
Y SUS B
Board
d
Y-Drive Boards (1 Upper and 1 Lower).
Z-SUS Board
Control Board
X Drive Boards (3)
Main Board:
Front IR/Intelligent Sensor
Interconnect Diagram: 11X17 Foldout Section used as a quick reference sheet.
2
Plasma
Preliminary Matters
50PV450 Plasma
Pl
Di
Display
l
Section 1
This Section will cover Contact Information and remind the Technician of Important
Safety Precautions for the Customers Safety as well as the Technicians and the
Equipment.
Basic Troubleshooting Techniques which can save time and money sometimes can
be overlooked. These techniques will also be presented.
This Section will get the Technician familiar with the Disassembly, Identification and
Layout of the Plasma Display Panel.
At the
th end
d off this
thi Section
S ti the
th Technician
T h i i should
h ld be
b able
bl to
t Identify
Id tif the
th Circuit
Ci it
Boards and have the ability and knowledge necessary to safely remove and
replace any Circuit Board or Assembly.
Plasma
LG Contact Information
Customer Service (and Part Sales)
(800) 243-0000
(800) 847
847-7597
7597
http://gsfs-america.lge.com
http://www.us.lgservice.com
Knowledgebase Website
http://lgtechassist.com
LG Web Training
https://lge.webex.com
LG CS Learning Academy
http://ln.lge.com/ilearn
http://136.166.4.200
Training Manuals, Schematics with Navigational Bookmarks, Start-Up Sequence, Owners Guides,
e co ec Diagrams,
ag a s, Dimensions,
e s o s, Co
Connector
ec o IDs,
s, Product
oduc Pictures
c u es a
and
d Features.
ea u es
Interconnect
Also available on the Plasma Page:
PDP Panel Alignment Handbook,
Plasma Control Board ROM Update (Jig required)
Plasma
CAUTION
To avoid personal injury, disconnect the power before servicing this product. If electrical power is
required for diagnosis or test purposes, disconnect the power immediately after performing the
necessary checks
checks. Also be aware that many household products present a weight hazard
hazard.
At least two people should be involved in the installation or servicing of such devices.
Failure to consider the weight of an product could result in physical injury.
Plasma
Todays sophisticated electronics are electrostatic discharge (ESD) sensitive. ESD can weaken or damage
the electronics in a manner that renders them inoperative or reduces the time until their next failure.
Connect an ESD wrist strap to a ground connection point or unpainted metal in the product. Alternatively,
you can touch your finger repeatedly to a ground connection point or unpainted metal in the product. Before
removing a replacement part from its package,
package touch the anti-static bag to a ground connection point or
unpainted metal in the product. Handle the electronic control assembly by its edges only. When
repackaging a failed electronic device in an anti-static bag, observe these same precautions.
R l
Regulatory
Information
I f
i
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to
Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful
interference
f
when the equipment is operated in a residential installation. This equipment generates, uses,
and can radiate radio frequency energy, and, if not installed and used in accordance with the instruction
manual, may cause harmful interference to radio communications. However, there is no guarantee that
interference will not occur in a particular installation. If this equipment does cause harmful interference to
radio or television reception, which can be determined by turning the equipment off and on, the user is
encouraged to try to correct the interference by one or more of the following measures: Reorient or relocate
the receiving antenna; Increase the separation between the equipment and the receiver; Connect the
equipment to an outlet on a different circuit than that to which the receiver is connected; or consult the
dealer or an experienced radio/TV technician for help.
Plasma
Approximately 10 minute pre-run time is required before any adjustments are performed.
2.
Refer to the silk screening on the Switch Mode Power Supply for proper Voltage and Current listings and manufacturers
cautions.
3
3.
Refer to the Voltage Sticker on the Panel when making adjustments on the Power Supply
Supply, Y-SUS
Y SUS and Z-SUS
Z SUS Boards.
Boards
4.
Always adjust to the specified voltage level (+/- volt) unless otherwise specified.
5.
Be cautious of electric shock from the PDP module since the PDP module uses high voltage, check that the Power Supply
and Drive Circuits are completely discharged because of residual current stored before Circuit Board removal.
5
5.
C-MOS circuits are used extensively for processing the Drive Signals and should be protected from static electricity
electricity.
6.
The PDP Module must be carried by two people. Always carry vertical NOT horizontal.
7.
8.
Exercise care when making voltage and waveform checks to prevent costly short circuits from damaging the unit.
9.
Be cautious of lost screws and other metal objects to prevent a possible short in the circuitry.
10. New Plasma Models have thinner Display Panels and Frames than previous models. Be careful when lifting
Plasma Displays because flexing the panel may damage the frame mounts or panel.
Plasma
Plasma
Plasma
Plasma
50PV450 Specifications
For
o Full
u Spec
Specifications
cat o s
See the Specification Sheet
TruSlim
T Sli Frame
F
600Hz Max Sub Field Driving
Full HD 1080p Resolution
ENERGY STAR Qualified
Picture Wizard II
Intelligent Sensor
gy Saving
g
Smart Energy
ISFccc Ready
11
Plasma
12
Plasma
600 Hz Sub Field Driving is achieved by using 10 sub-fields per frame process
(vs. Comp. 8 sub-field/frame)
Original Image
Sub Field firing occurs using wall charge and polarity differences between Y-SUS and Z-SUS signals.
13
Plasma
BOTTOM PORTION
14
Plasma
HDMI 3
Composite
Video/Audio
REAR
INPUTS
15
Plasma
* CAUTION:
Do not remove AC power or the USB Flash Drive.
Do not turn off Power, during the upgrade
process.
Software Files are now available from
LGTechassist.com
16
Plasma
Location of
files found
On the Jump
Drive
17
Plasma
18
Plasma
105-201M
MKJ39170828
Plasma
Software Version
Units Total Time
To Reset press In Stop
Country Group
MODEL
S/W VER
UTT
ADC CAL.
: 50PV45*-U*
V3.04.0
:2
RGB : OK
YPbPr(SD) : OK
YPbPr(HD) : OK
EDID : RGB(OK) HDMI(1:0K 2:0K 3:OK)
:
0. TOOL OPTION
:
1. AREA OPTION
:
2. EPA
3. POWER OFF HISTORY
4. AUTO TEST
5. BAUD RATE
6. AUDIO EQ
7. Bass EQ
8. CHANNEL MUTE
9. SYNC LEVEL
10. DTV SNR
11. POWER ERROR HISTORY
20
Sensor
V0.05(0x05)
Intelligent Sensor
Software Version
6
USA
ON
9600
ON
ON
ON
May 2011
50PV450 Plasma
: 50PV45*-U*
V3.04.0
:2
Sensor
V0.05(0x05)
LAST HISTORY1
LAST HISTORY2
LAST HISTORY3
LAST HISTORY4
RGB : OK
YPbPr(SD) : OK
YPbPr(HD) : OK
EDID : RGB(OK) HDMI(1:0K 2:0K 3:OK)
:
0. TOOL OPTION
:
1. AREA OPTION
:
2. EPA
3. POWER OFF HISTORY
4. AUTO TEST
5. BAUD RATE
6. AUDIO EQ
7. Bass EQ
8. CHANNEL MUTE
9. SYNC LEVEL
10. DTV SNR
11. POWER ERROR HISTORY
LAST HISTORY5
6
USA
ON
RCU OFF
KEY OFF
2HOUR OFF
NO SIGNAL OFF
AC DEC OFF
5VMNT OFF
TVLINK OFF
CLEAR ALL
9600
ON
ON
ON
21
AC DET OFF
NO SIGNAL OFF
NO SIGNAL OFF
-------------------------
:
:
:
:
:
:
:
May 2011
0
0
0
2
1
0
0
50PV450 Plasma
: 50PV45*-U*
V3.04.0
:2
Sensor
V0.05(0x05)
RGB : OK
YPbPr(SD) : OK
YPbPr(HD) : OK
EDID : RGB(OK) HDMI(1:0K 2:0K 3:OK)
:
6
0. TOOL OPTION
:
USA
1. AREA OPTION
:
ON
2. EPA
3. POWER OFF HISTORY
4. AUTO TEST
9600
5. BAUD RATE
ON
6. AUDIO EQ
ON
7. Bass EQ
ON
8. CHANNEL MUTE
9. SYNC LEVEL
Highlight and
10. DTV SNR
Cursor Right
11. POWER ERROR HISTORY
DTV SNR
DTV SNR
33
22
May 2011
50PV450 Plasma
: 50PV45*-U*
V3.04.0
:2
V0.05(0x05)
RGB : OK
YPbPr(SD) : OK
YPbPr(HD) : OK
EDID : RGB(OK) HDMI(1:0K 2:0K 3:OK)
:
0. TOOL OPTION
:
1. AREA OPTION
:
2. EPA
3. POWER OFF HISTORY
4. AUTO TEST
5. BAUD RATE
6. AUDIO EQ
7. Bass EQ
8. CHANNEL MUTE
9. SYNC LEVEL
10. DTV SNR
11. POWER ERROR HISTORY
6
USA
ON
9600
ON
ON
ON
23
LAST HISTORY1
LAST HISTORY2
LAST HISTORY3
VA UVP
VS OCP
PFC_DET Error
5V OVP
5V UVP
17V OVP
17V UVP
M5V OVP
M5V UVP
VS OCP
VS OVP
VS UVP
VA OCP
VA OVP
VA UVP
CLEAR ALL
0
0
0
0
0
0
0
1
0
0
0
0
1
-------------
May 2011
50PV450 Plasma
0. ADC CALIBRATION
1. ADC ADJUST
2. SUB B/V ADJUST
3. 2/B ADJUST
4. EDID D/L
5. 2HOUR OFF
6. UART DOWNLOAD
7. MODULE CONTROL
8. DEBUG MODE
9. 15Min Forced Off
10. Phase Noise Control
11. 1MIN TIMER CONTROL
12. Lip Sync Adjust(DTV)
13. DVI/HDMI Switch
14. PLL Tracking Speed
15. Touch Sensitivity Setting
16. Over Modulation Control
17. Atten RF Signal
: ON
:
:
:
:
:
:
:
OFF
ON
OFF
OFF
20
OFF
0
HDMI1
OK
HDMI2
OK
HDMI3
OK
HDMI4
OK
RGB
OK
START
: 1
: OFF
24
May 2011
50PV450 Plasma
0. ADC CALIBRATION
1. ADC ADJUST
2. SUB B/V ADJUST
3. 2/B ADJUST
4. EDID D/L
5. 2HOUR OFF
6. UART DOWNLOAD
7. MODULE CONTROL
8. DEBUG MODE
9. 15Min Forced Off
10. Phase Noise Control
11. 1MIN TIMER CONTROL
12. Lip Sync Adjust(DTV)
13. DVI/HDMI Switch
14. PLL Tracking Speed
15. Touch Sensitivity Setting
16. Over Modulation Control
17. Atten RF Signal
Module Temp.
Module Name
Module Rom Ver.
35.5 Celsius
50R3
50R3_3DA1E0
:
:
:
:
:
:
:
0. AV PC Mode
1. ISM Control
2. Gama
3. PS Mode
4. DPS Control
5. Rom Download
:
:
:
:
:
:
OFF
ON
OFF
OFF
20
OFF
0
: 1
: OFF
AV
AUTO
0
13
OFF
OFF
Temperature
of the Panel
Software
Version
AUTO, PC
ON, OFF
1, 2, 3
Fixed
ON
ON
25
May 2011
50PV450 Plasma
: ON
:
:
:
:
:
:
:
OFF
ON
OFF
OFF
20
OFF
0
: 1
: OFF
26
May 2011
50PV450 Plasma
50PV450 Dimensions
There must be at least 4 inches of Clearance on all sides
46-5/16"
1176.02mm
23-1/8"
Center
Center
588.01mm
2"
50.8mm
5-15/16"
135mm
15-1/8"
384mm
30-5/16"
769.62mm
15-3/4"
400mm
Center
14"
355.6mm
28"
711.2mm
15-3/4"
400mm
Model No.
Serial No.
Label
Remove 4 screws
to remove stand
for wall mount
7-3/16"
182mm
2-5/16"
58.42mm
20-1/2"
520mm
Max Watts 270W
Power Consumption: Typical: 145W
<0.2 Watts (Stand-By)
11-3/8"
289.6mm
Weight:
27
May 2011
50PV450 Plasma
DISASSEMBLY SECTION
This section of the manual will discuss Disassembly, Layout and Circuit
Board Identification of the 50PV450 Advanced Single Scan Plasma Display Panel
Panel.
Upon completion of this section the Technician will have a better
understanding of the disassembly procedures, the layout of the printed
circuit boards and be able to identify each board.
board
28
Plasma
29
Plasma
FPC
F
FPC
Y-Drive
Upper
FPC
FPC
Z-SUS
FPC
Power Supply
(SMPS)
Y SUS
Y-SUS
FPC
FPC
Z-SUB
FPC
Control
M i B
Main
Board
d
FPC
Y-Drive
Lower
TCP
Heat Sink
FPC
C
AC In
Left X
IR/LED Board
Soft
S
ft T
Touch
h
Keypad
Right X
Center X
Invisible
Speaker
FPC
Side
Input
(part of
main)
Invisible
Speaker
30
April 2011
50PV450
Plasma
P102
PANEL
p/n: EAJ61527904 (PDP50R30000.ASLGB 50Inch 1920X1080)
p/n: EAJ61527931 (PDP50R30000.ASLGB 50Inch 1920X1080)
Y-DRIVE
UPPER
Board
p/n: EBR71728001
P203
SMPS
POWER SUPPLY
Board
P218
P111
P214
P104
P201
Y-SUS
Board
P211
P101
P205
P102
P206
P103
SC101 P813
L N
p/n: EBR69839001
P221
P201
P204
P217
P212
P216
P213
P102
P213
P105
P101
P203
Y-DRIVE
LOWER
Board
P121
P100
P201
P2
LEFT X Board
p/n: EBR71728101
P202
P203
P204
P201
P310
P202
LVDS
P301
P704
P104
AC In
p/n: EBR71728401
P205
P701
CONTROL
Board P31
p/n:
P102
EBR71727801
P101
P801
CENTER X P321
P203
P204
P205
p/n:
EBU60952917
EBR72942909
RIGHT X Board
P320 P310
P201
MAIN
Board
p/n: EBR71728501
P202
P203
P204
P100
J1
p/n:
EBR72650101
P102
n/c
P203
P202
p/n: EAY62171101
P215
P121
p/n: EBR71727901
P202
P203
P112
p/n: EBR69839201
P204
Z-SUS
Board
P811
P210
FT
IR
Z-SUB Board
P201
P103
p/n: EBR69839101
P101
p/n: EAB62028901
31
May 2011
P205
p/n:
EAB62028901
50PV450 Plasma
32
Plasma
33
Plasma
34
Plasma
D
Left
D
Right
Warning:
Never run the TV with the
TCP Heat Sink removed
E
Heat Sink
Ground
Wire
35
Plasma
Va from
the
Y-SUS to
Left X
Only
TCP
36
Plasma
Lift up
p the locking
g mechanism as shown to
release the ribbon cable.
(The Lock can be easily damaged, and
needs to be handled carefully.)
Tab
Tab
Chocolate
37
Plasma
38
Plasma
At the end of this Section the technician should understand the operation of each circuit board and how to
adjust the controls. The technician should then be able to troubleshoot a circuit board failure, replace the
defective circuit and perform all necessary adjustments.
39
Plasma
FPCs
FG Voltages measured
from Floating Ground
P101
P102
P103
P104
FG5V
P121
FPCs
P201
SMPS Board
Note:
Va not used
by Y-SUS only
fused and routed
to the X-Board
P212
P216
Floating Gnd (FG)
Y-Scan
P213
P213
Scan Data,
Clk
P203
M5V
18V / M5V
Note: 18V not used
by Control
P101
Y Drive Lower
RGB Logic
Signals
X-Board-Left
P101
P102
P103
3.3V
P122
P104
Va
P105
P301
3.3V
RGB Logic
Signals
3.3V
3.3V
P102
P103
P103 P202
P301
Va
P210
P221
P211 P311 P331
X-Board-Center
P232
P302
P102
P303
P203
P701
LVDS Video
P104
3.3V
Va
P101
Display Enable
P102
P203
P201
P101
Z-SUB
P2
CONTROL
Board P31
3.3V
FPCs
P201
P105
P102
Z Drive Control
Signals
P304
P305
FPCs
STBY/RUN STBY_3.3V
RUN 5V_MST
P211
P217
Floating Gnd (FG)
Y-Scan
18V / M5V
Logic Signals
To Y-SUS and Y-Drive
Z-Drive
Z-SUS
Board
AC
Input
Filter
Y-SUS Board
P221
FG5V
P202
P204
M5V, Vs, Va
P203
P811
P113
P215
Floating Gnd (FG)
Y-Scan
P112
Vs
P218
P214
Floating Gnd (FG)
FG10.9V
P111
Display Panel
Horizontal
Electrodes
Sustain
P704
P801
P100
P320 P310
P301
Speakers
MAIN
Board
IR,
Intelligent Sensor
P101
X-Board-Right
P302
P303
P304
P305
40
May 2011
50PV450 Plasma
(11)
(3)
(4)
(5)
(6)
(10)
(9)
(8)
(12)
(13)
(14)
(15)
(7)
41
Plasma
Adjustment Notice
All adjustments (DC or Waveform) are adjusted in WHITE WASH.
Customers Menu, Select Options, select ISM select WHITE WASH.
Set-Up
-Vy
Vsc
Ve
ZBias
Panel
Rear View
42
Plasma
43
Plasma
Y-SUS Board
VS
VA
M5V
Used to develop
p Bias Voltages
g on the Y-SUS,, Z-SUS Boards.
Main Board
VS
STBY 5V
Microprocessor Circuits
17V
5V
Adjustments
There are 2 adjustments located on the Power Supply Board VA and VS. The
M5V is pre-adjusted and fixed. All adjustments are made referenced to Chassis
Ground. Use Full White Raster 100 IRE
VS
VR901
VA
VR501
44
Plasma
F801
4A/250V
VS
VA Adj
VR502
POWER SUPPLY
p/n: EAY62171101
Hot
Ground
CURRENT LABEL
VA
VS Adj
VR901
F302/F801
160.1V STBY
390V Run
VS or VA Diode Check
Open with Board Disconnected or
Open with Board Connected
M5V Diode Check
0.73V Board Connected or
0.72V Disconnected
VA TP
VS TP
P811
P811
1) VS
2) VS
3) n/c
4) Gnd
5) Gnd
6) VA
7) M5V
F302
2.5A/250V
Pin
18
17
16
15
13-14
9-12
8
5-7
3-4
1-2
Label
Stby
Gnd
b
M_On
0V
ad
AC_Det
0V
a
RL_ON
0V
Stby_5V 3.47V
Gnd
Gnd
ac
Error_Det 3.44V
a
5.1V
0.46V
Gnd
Gnd
a
17V
0V
e
Auto_Gnd
Run
Gnd
3.28V
4.06V
3.28V
5.14V
Gnd
4.02V
5.17V
Gnd
17V
Diode
Gnd
Open
3.1V
Open
2.53V
Gnd
2.84V
2.13V
Gnd
3.06V
Note a:
The RL_On command turns on the 17V, +5V,
Error_Det and AC_DET.
Note b:
The M-On command turns on M5V, Va and Vs.
D102
RL103
F101
10A/250V
D101
P813
J63 J26
5.1V 17V
AC In
P701
n/c
45
Note c:
The Error Det line is not used in this model.
Note d:
AC Det line is not used.
Note e:
Pin 18 is grounded on the Main. If opened, the
power supply turn on automatically.
May 2011
50PV450 Plasma
P811
To Y-SUS
Fuse F801
160.1V Stby
390V Run
VS Source
VS VR901
4Amp/250V
VA Source
VA VR501
Fuse F302
160.1V Stby
390V Run
17V Source
2.5Amp/250V
Bridge
Rectifiers
PFC
C
Circuit
STBY 5V,
5V Source
RL103
P701
n/a
Main Fuse
F101
To MAIN
P813
AC Input
SC 101
10Amp/250V
46
Plasma
47
Plasma
(SMPS)
AC In
STBY
3.47V
AC
Det
AC
Det.
+5V
Regulator
RUN
5.14V
RL On
RL On
17V
Reg
Vs
Reg
1st
M5V
Reg
Relays
Stand
By 5V Reg
3rd
5V
17V
RL On
2nd
Va
Reg
Vs
M5V
Vs
Va
8
Va
Y-SUS
M_On
M5V
Vs
Vs
Vs
7
8
10.9VFG
Reg
7
8
Error Det.
AC Det.
Mutes
Audio
17V
Audio
IC801
Not
Used
Multiple
Regulators
Reset
C108 & R62
3.3VST
2
3
M5V
Va
Error Relay
Det. On
M_On
7
Microprocessor
IC1
Z-SUS
M5V
18V / M5V
18V
10.9V
Floating Gnd
At point 3
TV is in
Stand-By
state. It is
Energy Star
Compliant.
Less than 1
Watt
MAIN
Board
18V
Reg
8
3.3V Reg
IC302
CONTROL
18V / M5V
Y DRIVE Upper
5VFG
Reg
Y DRIVE Lower
5VFG
3.3V
X Board Va
Left
8
2
4
7 5VFG
3.3V
X Board Va
Center
8
Front IR
Board
48
STBY 5V
Power On
3.3V
Reg
May 2011
X Board
Right
Soft
Touch
Key Pad
Power Key
50PV450 Plasma
49
Plasma
Example
Voltage Label
VA
Voltage
Vs TP
or P811
Pin 1 or 2
Vs Adjust:
Place voltmeter on VS TP.
Adjust
j
VR901 until the reading
g
matches your Panels label.
Va Adjust:
Place voltmeter on VA TP.
Adjust
j
VR502 until the reading
g
matches your Panels label.
50
Plasma
or
100W
100W
VS
P811
Pins
Note:
Always test the SMPS under a load using the
2 light bulbs.
Abnormal operational conditions may result if not
loaded.
VA TP
VS
VS
n/c
Gnd
Gnd
Va
M5V
VS TP
F801
4A/250V
CURRENT LABEL
VS Adj
VR901
Gnd
Pins
VA Adj
VR502
4 or 5
P811
Check Pins 1 or 2
for Vs voltage
POWER SUPPLY
p/n: EAY62171101
Hot
Ground
F302
2.5A/250V
P813
Check Pins 6
for Va voltage
Check Pins 7
for M5V voltage
RL103
Check Pins 1 or 2
For 17V (17V)
F101
10A/250V
P813
AC In
Note:
To turn on the Power Supply;
1) With Main Board connected, press power.
2) Without Main Board connected SMPS will turn on automatically.
P701
n/c
51
Check Pin 16
for AC Det (4.94V)
May 2011
50PV450 Plasma
(A) Ground the Auto Gnd Line (Pin 18) will allow the supply to be
powered up one section at a time.
(B) Add a 100 watt resistor from 5V Standby to RL_ON and the 17V
and 5V Run Lines on P813 will become active
active. Also AC-Det (4
(4.06V)
06V)
and Error_Det (4.1V) become active (Not Used).
(C) Add a 100 watt resistor from any 5V line to M_ON to make the
(Monitor) M5V, VS and VA lines operational.
P811 (VS pins 1 and 2) and (VA pins 6).
6)
P811 (M5V pin 7)
52
Plasma
Label
STBY
Run
No Load
Diode
Auto_Gnd
Gnd
Gnd
4.86V
Open
0V
3.28V
0V
Open
17
16
ad
AC Det
0V
4.06V
4.94V
3.1V
15
RL_ON
0V
3.28V
0V
Open
13-14
STBY_5V
3.47V
5.14V
4.94V
2.53V
9 12
9-12
G d
Gnd
G d
Gnd
G d
Gnd
G d
Gnd
G d
Gnd
3.44V
4.02V
4.94V
2.84V
5.1V
0.46V
5.17V
5.22V
2.13V
34
3-4
Gnd
Gnd
Gnd
Gnd
Gnd
1_2
0V
17V
17V
3.06V
8
5-7
M_ON
ac
Error_Det
a
17V
5V
17V
a Note: The RL_On command turns on the 17V, +5V, Error_Det and AC_DET.
b Note: The M
M-On
On command turns on M5V, Va and Vs.
c Note: The Error Det line is not used in this model.
Note: This connector has two
d Note: AC Det if missing, the TV will attempt to turn on, but shut off.
rows of pins.
e Note: Pin 18 is grounded on the Main. If opened, the power
Odd on top row.
supply turns on automatically.
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
53
Plasma
Pin Number
SC101
Standby
Run
120VAC
120VAC
L and N
Diode Mode
Open
P811
Pin
Label
Run
Diode Check
1 2
1~2
V
Vs
*201V
O
Open
n/c
n/c
n/c
4~5
Gnd
Gnd
Gnd
Va
*55V
Open
M5V
5.0V
1.38V
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
54
Plasma
(Overview)
Y-SUS Board develops the Y-Scan drive signal to the Y-Drive boards.
This Section of the Presentation will cover alignment and troubleshooting the Y-SUS Board.
Upon completion of the Section the technician will have a better understanding of the
operation of the circuit and will be able to locate test points needed for troubleshooting and
alignments.
g
Adjustments
DC Voltage and Waveform Checks
Diode Mode Measurements
Operating Voltages
SMPS Supplied
VA
VS
M5V
Y-SUS Developed
-VY VR501
VSC VR500
V SET UP VR402
V SET DN VR401
18V
Floating Ground
-Vy and VSC generated when Vs arrives on the board. FG10.9V, FG23.77V and 18V generated when M5V arrives on the board.
55
Plasma
Z-SUS Board
VA
Distributes Vs
Control Board
VS
Distributes
VA
Circuits generate
Y-Sustain Waveform
Left X Board
M5V
Generates Floating
g Ground
10.9V/23.77V by
DC/DC Converters
Distributes FG10.9V
Logic
Logic signals
needed to scan
the panel
FG5V
Display
Panel
56
Plasma
FS203 (VS)
6.3A/250V
-Vy
Vy
R527
P218
VR501
VSC
VSC
R548
P210
FS202 (M5V)
10A/125V
/
VR500
-Vy
FS201 (VA)
4A/125V
VR401
Set Dn
C540
FS501 (18V)
2A/125V
VR402
Set Up
P213
P102
WARNING: Do not run set if P213
is removed. Damage will occur.
To Z-SUS
P203
57
Ribbon
Logic Signals from
the Control Board
Va to Left X Board
Pins 5~7
Plasma
VR500
+Vy
P216
Pins 11-12 VSCAN
Pins 1-10 FGnd
FGnd
VScan
P216
D501
FS202 (M5V)
10A / 125V
D512
P210
7) M5V
6) VA
4-5) Gnd
3) n/c
1-2) VS
18.34V
D515
IC302
FS501 (18V)
2A / 125V
VR401
Set-Dn
P217
IC500
D511 10.9VFG
23.77VFG
P215
C540
D500
103VFG
IC501
P217
Pins 6-12 FGnd
n/c
Pin 5
VSCAN
Pins 1-4
D505
190VFG
P214
VSC
R548
FS203 (VS)
6.3A / 250V
T500
D503
1) M5V
2) M5V
3) OC2_B
4) Gnd
5) DATA_B
6) Gnd
7) OC1_B
8) OC2_T
9) Gnd
10) DATA_T
11) Gnd
12) OC1_T
13) Gnd
14) CLK
15) STB
FS201 (VA)
4A / 125V
Example:
VR402
Set-Up
Y-SUS
EBR69839001
Gnd
J81
P215
Pins 9-12 VSCAN
n/c
Pin 8
FGnd
Pins 1-7
P218
J113
P214
Pins 3-12 FGnd
Pins 1-2
FG10.9V
D502
P218
7-8) Gnd
6) n/c
4-5) VS
3) n/c
1-2) ER
P210
+Vy
R527
J33
D504 158VFG
T502
P102
-Vy VSC
CTRL_OE
P102
6-8) 18V
3-5) M5V
P203
P213
To run the 18V and Floating Ground
24V and 10V, Ground CTRL_OE and
supply 5V to Y-SUS
58
P203
1-2) Gnd
3) n/c
4-5) VA
P213 to P213
1) M5V
2) M5V
3) OC2_B
4) Gnd
5) DATA_B
6) Gnd
7) OC_B
8) OC2_T
9) Gnd
10) DATA_T
11) Gnd
12) OC1_T
13) Gnd
14) CLK
15) STB
RUN
4.96V
4.96V
2.77V
Gnd
0V
Gnd
1.73V
2.73V
Gnd
0V
Gnd
1.74V
Gnd
0.68V
4.27V
DIODE
1.38V
1.38V
Open
Gnd
1.85V
Gnd
1.85V
Open
Gnd
1.85V
Gnd
1.85V
Gnd
1.85V
1.85V
May 2011
50PV450 Plasma
Set should run for 10 minutes, this is the Heat Run mode.
Set screen to White Wash.
1) Adjust Vy (VR500) to Panels Label voltage (+/- 1/2V)
2) Adjust VSC (VR501) to Panels Label voltage (+/- 1/2V)
-Vy
VSC
R548
VSC TP
+
+
R527
-Vy TP
Location:
Center Top
Left of board
VR501
VSC Adj
VR500
-Vy Adj
59
Plasma
107VRMS
Blanking
560V p/p
Blanking
Adjustment Area
60
Plasma
61
Plasma
Fig 1
Fi
1:
As an example of how to lock in to the Y-Scan Waveform. Fig
1 shows the signal locked in at 4ms per/div.
Note the 3 blanking sections.
j
is p
pointed out within the Waveform
The area for adjustment
Area to
expand
FIG1
4mS
Blanking
Adjustment
Area
Fig 2:
At 2mSec per/division, the area of the waveform to
use for SET-UP or SET-DN is now becoming clear.
Now only two blanking signals are present
present.
FIG2
2mS
Area to
p
expand
Blanking
Fig 3:
At 100us per/div the area for adjustment of SET-UP or SET-DN
i now easier
is
i tto recognize.
i
It is
i outlined
tli d within
ithi th
the W
Waveform.
f
st
Remember, this is the 1 large signal to the right of blanking.
Area to
be adjusted
FIG3
100uS
Blanking
Expanded from above
g 4:
Fig
At 40uSec per/division, the adjustment for
SET-UP can be made using VR402 and the
SET-DN can be made using VR401.
It will make this adjustment easier if you use the
Expanded mode of your scope.
scope
Expanded
345V
p/p
FIG4
40uS
180 uSec
62
Plasma
VR401
B
SET-UP ADJUST:
1) Adjust VR402 and set the (A) portion of the signal to
match the waveform above
above. (345V p/p 5V)
A
VR402
ADJUSTMENT
LOCATIONS:
Center of the
board.
SET-DN ADJUST:
2) Adjust VR401 and set the (B) time of the signal to match
the waveform above. (180uSec 5uSec)
63
Plasma
Too Low
88.8uSec
64
NOTE: If
abnormal settings
cause excessive
brightness then
shutdown,
remove the LVDS
from Control
board and make
necessary
adjustments.
Then reconnect
LVDS cable,
select White
Wash and adjust
correctly.
Plasma
P/N EBR69839001
65
Plasma
P102 Y
Y--SUS Board Ribbon to Control P203 Voltage and Diode Test
P102 "Y-SUS" to P105 "Control"
Pi
Pin
L b l
Label
R
Run
Di d Check
Diode
Ch k
Pi
Pin
L b l
Label
R
Run
Di d Check
Diode
Ch k
30
CTRL_OE
0.06V
Open
15
DATA_TOP
0V
Open
29
OE
0.02V
2.29V
14
OC1_TOP
1.16V
Open
28
SUS_UP
0.13V
p
Open
13
CLK
0.46V
Open
p
27
SUS_DN
2.84V
Open
12
STB
2.86V
Open
26
SET_DN
2.2V
Open
11
OC1_BTM
Gnd
Open
25
Slope_Rate_Sel
0.05V
Open
10
DATA_BTM
0V
Open
24
Det_Level_Sel
0.3V
Open
OC2_BTM
1.98V
Open
23
Ramp_Slope_Opt1
0.06V
Open
+18V
18.34V
1.32V
22
SET_UP
0.06V
Open
+18V
18.34V
1.32V
21
YER UP
YER_UP
0 11V
0.11V
Open
+18V
18 34V
18.34V
1 32V
1.32V
20
Gnd
Gnd
Gnd
M5V
4.89V
1.40V
19
YER_DN
0.09V
Open
M5V
4.89V
1.40V
18
PASS_TOP
1.02V
Open
M5V
4.89V
1.40V
17
DELTA_VY_DET
0.35V
Open
Gnd
Gnd
Gnd
16
OC2_TOP
1.98V
Open
Gnd
Gnd
Gnd
66
Plasma
P203 Y
Y--SUS Board to Left XX-Board P121 Voltage and Diode Test
Location: Bottom Right of board
P203
c
To Left X-Board
Label
Run
Diode Check
1~2
Gnd
Gnd
Gnd
n/c
n/c
Open
4~5
Va
*55V
Open
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
67
Plasma
P210 Y
Y--SUS Board to SMPS P811 Voltage and Diode Test
Location: Top Right of board
P210
c
To SMPS
Label
Run
Diode Check
1~2
Vs
*201V
Open
n/c
n/c
n/c
4~5
Gnd
Gnd
Gnd
Va
*55V
Open
M5V
5.0V
1.38V
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
68
Plasma
P213 Y
Y--SUS Board Connector to P213 Lower Y-Drive (Logic Signals)
TIP: This connector does not come with a new Y-SUS or Y-Drive.
TIP: Use C540 Left leg to check the Y
Y-Scan
Scan signal if the Y
Y-Drive
Drive boards are removed
Note: The Lower Y-Drive board receives Monitor 5V from the Y-SUS.
P213
Y-SUS Board
Label
Run
Diode Check
M5V
4.96V
1.38V
M5V
4.96V
1.38V
OC2_B
2.77V
Open
Gnd
Gnd
Gnd
DATA_B
0V
1.85V
Gnd
Gnd
Gnd
OC1 B
OC1_B
1 73V
1.73V
1 85V
1.85V
OC2_T
2.73V
Open
Gnd
Gnd
Gnd
10
DATA_T
0V
1.85V
11
Gnd
Gnd
Gnd
12
OC1_T
1.74V
1.85V
13
Gnd
Gnd
Gnd
14
CLK
0.68V
1.85V
15
STB
4.27V
1.85V
69
Plasma
P213 Y
Y--SUS Board Connector Waveforms
Note: The Lower Y-Drive board receives Monitor 5V from the Y-SUS.
P213
P213 Y-SUS
Y SUS to
t L
Lower Y
Y-Drive
D i P213
Pin
Label
M5V
M5V
OC2_B
Gnd
DATA_B
G d
Gnd
OC1_B
OC2_T
Gnd
10
DATA_T
11
Gnd
12
OC1_T
13
G d
Gnd
14
CLK
15
STB
70
Plasma
P214 Y
Y--SUS Board to Upper YY-Drive P111 Voltage and Diode Test
Location: Top Left of board
P111
P214
Pi
Pin
L b l
Label
R
Run
Di d Check
Diode
Ch k
Di d Check
Diode
Ch k
3-12
FGnd
FGnd
FGnd
FGnd
1-2
FG10.9V
4.89V
Open
0.55V
Black Lead on
Floating Gnd
All readings
di
from
f
Floating
Fl ti Ground
G
d
Y-Drive Upper
Red Lead on
Floating Gnd
Y-SUS Board
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
71
Plasma
P215 Y
Y--SUS Board to Upper YY-Drive P112 Voltage and Diode Test
Location: Bottom Left of board
P112
P215
Pin
Label
Run
Diode Check
Diode Check
9-12
Vscan
107V
Open
Open
n/c
n/c
n/c
n/c
1-7
FGnd
FGnd
FGnd
FGnd
Black Lead on
Floating Gnd
c
Y-Drive Upper
Red Lead on
Floating Gnd
Y-SUS Board
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
72
Plasma
P216 Y
Y--SUS Board to Lower YY-Drive P212 Voltage and Diode Test
Location: Bottom Left of board
P212
P216
Pin
Label
Run
Diode Check
Diode Check
11-12
Vscan
107V
Open
Open
1-10
FGnd
FGnd
FGnd
FGnd
Black Lead on
Floating Gnd
Red Lead on
Floating Gnd
All readings
g from Floating
g Ground
Y-Drive Upper
Y-SUS Board
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
73
Plasma
P217 Y
Y--SUS Board to Lower Y-Drive P211 Voltage and Diode Test
Location: Bottom Left of board
P211
P217
Label
Run
Diode Check
Diode Check
6 12
6-12
FG d
FGnd
FG d
FGnd
FG d
FGnd
FG d
FGnd
n/c
n/c
n/c
n/c
1-4
Vscan
107V
Open
Open
Black Lead on
Floating Gnd
Red Lead on
Floating Gnd
All readings
g from Floating
g Ground
Y-Drive Upper
Y-SUS Board
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
74
Plasma
c
P218 "Y-SUS" to "Z-SUS" P203
Pin
Label
Run
Diode Check
1~2
Gnd
Gnd
Gnd
n/c
n/c
n/c
4~5
+Vs
*201V
Open
n/c
n/c
n/c
7~8
ER_PASS
*98V~102V
Open
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
75
Plasma
J32
10.9V
D511
FG10.9V
T502
FS201
VA
D512
FG23.77V
Location
FS501
18V
D515
FG18.34V
J81
(CTRL_OE)
Tip: Remove board, Ground J81 (CTRL_OE) Jump any 5V supply to pin 7 of P210
or FS202 and it will turn on these supplies for test.
76
Plasma
Location
T500
D505 Cathode
+Vy Source
77
Plasma
FS203 (VS)
6.3A / 250V
(FS202) M5V
0.54V Red Lead on FG
1.4V Blk Lead on FG
(FS501) 18V
0.62V Red Lead on FG
1.32V Blk Lead on FG
FS202 (M5V)
10A / 125V
FS201 (VA)
4A / 125V
Board Connected
Diode Check readings
FS201 Va or
FS203 Vs
Open
FS202 M5V
0.73V
FS501 (18V)
2A / 125V
FS501 18V
1.28V
78
Plasma
Y-SUS FET
Identification and
Location
P218
Q502
D S
J33
T500
D503
D500
IC500
IC501
P214
D501
P210
D505
D511
T502
HS603
HS601
D512
D515
P215
IC302
Q609
Position
Circuit No.
Direction
D610
HS601
Forward
Q606,Q607
Q608,Q609
Q612
Reverse
HS602
Q605
Q608
D608
D602
O.L. (Overload)
D604
C540
HS602
Forward
D604,D605
Q601,Q602
0.35V ~ 0.45V
0.45V ~ 0.55V
D602
Forward
Reverse
P217
Q603,Q605
Q602
Y-SUS
EBR69839001
O.L. (Overload)
Reverse
HS603
Q601
Q610,Q612
D605
0.4V ~ 0.5V
P216
Q610
Q603
Q606
P102
D609
Q607
D610
P203
P213
79
May 2011
50PV450 Plasma
80
Plasma
p/n: EBR69839101
PANEL
SIDE
Y-SUS
SIDE
P111
P112
The Upper Y
Y-Drive
Drive is also responsible for developing
the FG5V operational voltage for both Drive boards.
It receives FG10.9V from the Y-SUS on P111 pins
11~12 and routs this voltage to IC191 which regulates
it down to 5VFG.
The Upper Y-Drive then delivers the 5VFG to all the
buffers for their low voltage signal processing circuits.
The 5VFG is also sent down to the lower Y-Drive via
pins 21~30 to P221 p
pins 1~9 for the lower
P121 p
Y-Drive buffers. Can not read pins because they are
covered in silicon.
P121
81
Plasma
IC191
(1) 5VFG
(2) FGnd
(3) 10.9VFG
Q191
D191
P111
P112
Pin
Diode Check
0.42V
2.19V
0.63V
2.79V
A
C
82
Plasma
P214
Pi
Pin
L b l
Label
R
Run
Di d Check
Diode
Ch k
Di d Check
Diode
Ch k
11-12
FG10.9V
4.89V
Open
0.5V
1-10
FGnd
FGnd
FGnd
FGnd
Black Lead on
Floating Gnd
All readings
di
from
f
Floating
Fl ti Ground
G
d
Y-Drive Upper
Red Lead on
Floating Gnd
Y-SUS Board
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
83
Plasma
P215
Pin
Label
Run
Diode Check
Diode Check
6-12
FGnd
FGnd
FGnd
FGnd
n/c
n/c
n/c
n/c
1-4
Vscan
107V
Open
1.54V
Black Lead on
Floating Gnd
c
Y-Drive Upper
Red Lead on
Floating Gnd
Y-SUS Board
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
84
Plasma
P121 Upper YY-Drive to Lower YY-Drive P221 Voltage and Diode Test
Location: Bottom of board
P121 "Upper
Upper Y
Y-Drive"
Drive to P221 "Lower
Lower Y-Drive"
Y Drive
Pin
Label
Run
1~4
SUS_DN (FG)
FG
11
YSUS_DATA
0V
12
YT_OCR
2.4V
13
YT_OC1
2.2V
14
YT_LE(STB)
2.6V
15
YT_CLK
0.8V
16
YT_DATA
0V
17~20
SUS_DN (FG)
FG
21~23
FG5V
4.97V
27~30
FG5V
FG
P121
All voltages
lt
are from
f
Floating
Fl ti G
Ground
d
85
Plasma
p/n: EBR69839201
P221
Y-SUS
SIDE
P211
P212
Warning: Never run the set
with just P213 disconnected.
You must remove the Lower
and Upper Y-Drive boards
completely.
Never run the set with P221
unplugged unless you remove
the Upper Y-Drive board
completely.
P213
86
Plasma
P217
Label
Run
Diode Check
Diode Check
9 12
9-12
V
Vscan
107V
O
Open
1 54V
1.54V
n/c
n/c
n/c
n/c
1-7
FGnd
FGnd
FGnd
FGnd
Black Lead on
Floating Gnd
Red Lead on
Floating Gnd
All readings
g from Floating
g Ground
Y-Drive Upper
Y-SUS Board
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
87
Plasma
P216
Pin
Label
Run
Diode Check
Diode Check
3-12
FGnd
FGnd
FGnd
FGnd
1-2
Vscan
107V
Open
1.54V
Black Lead on
Floating Gnd
Red Lead on
Floating Gnd
All readings
g from Floating
g Ground
Y-Drive Upper
Y-SUS Board
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
88
Plasma
Label
Run
1~4
FG5V
5V
5-9
FGnd
0V
12
YT_OCR
2.4V
13
YT_OC1
2.2V
14
YT_LE(STB)
2.6V
15
YT CLK
YT_CLK
0 8V
0.8V
16
YT_DATA
0V
17~20
SUS_DN (FG)
FG
21~23
FG5V
4.97V
24~30
SUS_DN (FG)
FG
P221
c
Can not read the pins because
they are covered in silicon
All voltages
lt
are from
f
Floating
Fl ti G
Ground
d
89
Plasma
Note: The Lower Y-Drive board receives Monitor 5V from the Y-SUS.
P213
P213
c
c
Lower
Y-Drive
Y-SUS
Board
Diode Check
0.55V
0.55V
0.63V
Gnd
0.63V
Gnd
0.63V
0.63V
Gnd
0.63V
Gnd
0.63V
Gnd
0.63V
0.63V
Black Lead
on pin
90
Plasma
P213 Y-SUS
Y SUS to
t L
Lower Y
Y-Drive
D i P213
Pin
Label
Pin
Label
15
M5V
14
M5V
13
OC2_B
12
Gnd
11
DATA B
DATA_B
10
Gnd
OC1_B
OC2_T
Gnd
DATA_T
Gnd
OC1 T
OC1_T
Gnd
CLK
STB
91
Plasma
To remove the
T
th Ribbon
Ribb C
Cable
bl ffrom th
the connector
t fifirstt carefully
f ll lift the
th Locking
L ki T
Tab
b ffrom
the back and tilt it forward ( lift from under the tab as shown in Fig 1).
The locking tab must be standing straight up as shown in Fig 2.
Lift up the entire Ribbon Cable gently to release the Tabs on each end. (See Fig 3)
y slide the Ribbon Cable free from the connector.
Gently
Be sure ribbon tab is released
By lifting the ribbon up slightly,
before removing ribbon.
Gently Pry
Up Here
Locking tab in
upright position
Fig 1
Fig 3
Fig 2
To reinstall the Ribbon Cable, carefully slide it back into the slot see ( Fig 3 ), be sure the Tab is seated
securely and press the Locking Tab back to the locked position see ( Fig 2 then Fig 1).
92
Plasma
93
Plasma
FRONT SIDE
RED LEAD On
BLACK LEAD On ANY
Floating Ground
Output Lug Reads 0.78V
y white outline
Indicated by
Reversing the leads reads Open
94
Plasma
Z-SUS SECTION
This Section of the Presentation will cover troubleshooting the Z-SUS Board Assembly.
Upon completion of this section the Technician will have a better understanding of the circuit and be
able to locate test points needed for troubleshooting and all alignments.
Locations
Operating Voltages
Power Supply
pp y Supplied
pp
VS
M5V
Y SUS Supplied
Y-SUS
18V
Developed on Z-SUS
Z Bias
95
Plasma
Y-SUS Board
18V
M5V
M5V
Control Board
M5V
18V
Receives
Logic
Signals
Via 3 FPC
Flexible
Printed
Circuits
NO IPMs
Z-SUB
96
PDP
Display
P
Panel
l
Plasma
FS201
VS
6.3A/250V
VZB TP
Across R156
VZB Adj
VR101
Z-SUS
Output
FETs
Z-SUS
Waveform
Development
FETs
Z-SUS
Waveform
T t Point
Test
P i t
J54
P/N EBR71727901
No IPMs
FS202
M5V
4A/125V
P204
P205
05
M5V from SMPS to the
Y-SUS, +18V generated
on the Y-SUS are routed
through the Control board.
Logic Signals generated on
the Control board.
To Z-SUB
P206
P201
97
Plasma
VR101
VZB Adj
Example:
Model : PDP 50R3###
Voltage Setting: 5V/ Va:55/ Vs:201
N.A. / -190 / 150 / N.A. / 130
Max Watt : 360 W (Full White)
VZB TP
R156
1-2) 18V
3) n/c
4-5) M5V
6-7) Gnd
8) SUS_DN
9) CTRL_EN
10) SUS_UP
11) VZB2
12) ER_DN
13) VZB1
14) ER_UP
15) ZBIAS
Q113
Q106
Q114
D118
P204
Gnd
Gnd
J21 18V
FS202
Z-SUS
EBR71727901
Q102
J16 M5V
FS202 (M5V)
4A / 125V
Q109
D110
ER_UP
ER_DN
SUS_DN
18.34V
(n/c)
4.89V
Gnd
0.73V
0.06V
0.15V
2.49V
0.1V
2.53V
0.11V
1.89V
57VRMS
100uSec 261V p/p
FS201 (VS)
6.3A / 250V
Q104
VZB (Z Bias)
P201
1-2) ER
3) n/c
4-5) VS
6) n/c
7-8) Gnd
D111
D114
D108
Q107
Q103
Q110
Z-Drive J54
Waveform
P205
P201
P206
98
May 2011
50PV450 Plasma
Z-SUS Waveform
The Z-SUS (in combination with the Y-SUS) generates a
g
and an ERASE PULSE for generating
g
g
SUSTAIN Signal
SUSTAIN and DISCHARGE in the Panel.
Y Drive
Waveform
Blanking
Z Drive
Waveform
Blanking
This Waveform is just for reference to observe the effects of Z Bias adjustment
99
Plasma
Sett should
S
h ld run for
f 10 minutes,
i t
this is the Heat Run mode.
Set screen to White Wash
mode or 100 IRE White input.
Negative
Lead
VZB (Z Bias)
R156
Positive
Lead
100
Plasma
P203 Z
Z--SUS Connector to Y
Y--SUS P218 Voltages and Diode Checks
Voltage and Diode Mode Measurements
Label
Run
Diode Check
1~2
ER_PASS
*98V~102V
Open
n/c
n/c
n/c
4~5
5
+Vs
s
*201V
0
Open
Ope
n/c
n/c
n/c
7~18
Gnd
Gnd
Gnd
P203 Location:
Top Left of Board
Pin 1
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
101
Plasma
P201 Z
Z--SUS Connector to Control P2 Voltages and Diode Checks
Voltage and Diode Mode Measurements
J21
18V
Label
Run
Diode Check
+18V
18.34V
Open
+18V
18.34V
Open
n/c
n/c
1.52V
+5V (M5V)
4.89V
1.52V
+5V (M5V)
4.89V
1.52V
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
SUS_DN
0.73V
Open
CTRL_EN
0.06V
Open
10
SUS_UP
0.15V
Open
11
VZB2
2.49V
Open
12
ER_DN
0.1V
Open
13
VZB1
2.53V
Open
p
14
ER_UP
0.87V
Open
15
ZBIAS
1.9V
Open
FS202
M5V
4A/125V
Pin 1
P201 Location:
Bottom Left hand side
102
Plasma
FS201 (VS)
6.3A / 250V
Q104
Q113
Q114
1-2) ER
3) n/c
4-5) VS
6) n/c
7-8) Gnd
Z-SUS
EBR71727901
HS10
1
Q109
Q106
D118
D110
HS10
2
Q102
FS202
P204
D111
D114
D108
Q107
Q103
Q110
P205
P201
Position
HS101
Forward
D114,D118
Q107,Q110
Q106,Q109
0.35V ~ 0.45V
0.35V ~ 0.45V
0.35V ~ 0.45V
O.L. (Overload)
Reverse
D109,D110,D108,D111 Q104,Q113,Q114
HS102
Forward
Reverse
P206
Circuit No.
Direction
0.35V ~ 0.45V
0.5V ~ 0.6V
Q102,Q103
0.4V ~ 0.55V
O.L. (Overload)
103
May 2011
50PV450 Plasma
2) Disconnect P105
3) Jump STBY5V to
FS202 on Z-SUS
(M5V Fuse)
104
Plasma
Signals
Main Board Supplied Panel Control and LVDS (Video) Signals
Control Board Generated Y-SUS
Y SUS and Z-SUS
Z SUS Drive Signals (Sustain)
Y-Drive Board Scan Signals (Gate Address)
X Board Drive Signals (RGB Address)
Operating Voltages
Y-SUS Supplied +5V (M5V) Developed on the SMPS
+18V (Routed to the Z-SUS)
(Not used by the Control Board)
Plasma
p/n: EBR71727801
106
Plasma
IC25
1) 0.8V
2) Gnd
3) 4.87V
4) 6.46V
8) 2.95V
7) 1.85V
6) 1.85V
5) 4.82V
18V
Pins 23-25
M5V
Pins 26-28
FL1/FL2
FL5
Diode Check
All Connectors
Connected
0.73V
IC61
05) 3.29V
06) 3.29V
07) 3.28V
08) 3.32V
04) 5.75V
03) 1.88V
02) Gnd
01) 0.8V
P2
P105
C52
C61
To
Y-SUS
Board
4.89V
IC25
P22 N/C
IC101
IC102
3) 4.93V
2) 3.29V
1) Gnd
IC51
1.04V
M5V
FL1/2
1-4
(3.3V)
IC53
L1
1.85V
D1 Blinks
Indicating Board
is Functioning
L2
1.84V
C65
FL5
IC61
C76
1.04V
1.04V
IC11
1.63V
25
Mhz
M5V
3.26V
IC1
To
Main
Board
AUTO
Gen
Q1
C72
P102
To Center
X Board
18.34V
(n/c)
4.89V
Gnd
0.73V
0.06V
0.15V
2.49V
0.1V
2.53V
0.11V
1.89V
VS-DA
TP
CONTROL BOARD
p/n: EBR71727801
1-4
(3.3V)
IC53
P2
To Z-SUS
Board
D1
1.84V
3.3V
4.89V
14-15) 18V
13) n/c
11-12) M5V
9-10) Gnd
08) SUS_DN
07) CTRL_EN
06) SUS_UP
05) VZB2
04) ER_DN
03) VZB1
02) ER_UP
01) ZBIAS
IC53
3) 4.89V
2) 3.3V
1) Gnd
4.89V
1-4
(3.3V)
IC53
P104
To Right
X Board
P31
LVDS
3.3V To X-Boards
Diode Check All
Connectors Connected
0.6769V
107
May 2011
50PV450 Plasma
With Chocolate
(Heat Transfer Material)
Covering the Temp IC.
The Chocolate
((Heat Transfer Material))
may stick to the Panel.
Be sure to put it in the
right place if the board
is removed.
CONTROL BOARD
LOCATION
Pin 1
IC103
04) 3.3V 03) Gnd
05) Gnd 02) Gnd
06) 3.3V 01) 3.3V
108
Plasma
AUTO
GEN
109
Plasma
X1
CONTROL
BOARD
CRYSTAL
LOCATION
110
Plasma
MCM
IC1
To
Y-SUS
DRAM DRAM
To
ZSUS
Data Buffer IC
X-DRIVE BOARD
Resistor Array
To
Main
MCM IC1
To Center
X-Board
3.3V to
TCPs
PANEL
3 Buffer
Outputs
per TCP
IC53
To
Left
XBoard
16 bit words
RGB Data Shown
To Right
T
Ri ht
X-Board
111
Plasma
Pin c
Pins 23 through 25
Receive 18V from the Y-SUS.
Pins 26 through 28
Receive M5V from the Y-SUS.
Note: The +18V is not used by the
C t lb
Control
board,
d it iis routed
t d tto the
th
Z-SUS leaving on P2 Pins 14~15.
112
Plasma
Control P105 to Y
Y--SUS P102 Plug Information
Label
Run
Diode Check
Pin
Label
Run
Diode Check
CTRL_OE
0.06V
2.84V
16
DATA_TOP
0V
2.81V
OE
0.02V
2.84V
17
OC1_TOP
1.16V
2.84V
SUS_UP
0.13V
2.82V
18
CLK
0.46V
Gnd
SUS DN
SUS_DN
2 84V
2.84V
2 83V
2.83V
19
STB
2 86V
2.86V
Gnd
SET_DN
2.2V
2.82V
20
OC1_BTM
Gnd
Gnd
Slope_Rate_Sel
0.05V
2.82V
21
DATA_BTM
0V
Gnd
Det_Level_Sel
0.3V
2.82V
22
OC2_BTM
1.98V
2.98V
R
Ramp_Slope_Opt
Sl
O t
0 06V
0.06V
2 81V
2.81V
23
+18V
18 34V
18.34V
O
Open
SET_UP
0.06V
2.82V
24
+18V
18.34V
Open
10
ER_UP
0.11V
2.81V
25
+18V
18.34V
Open
11
Gnd
Gnd
Gnd
26
M5V
4.89V
Open
12
ER_DN
0.09V
2.81V
27
M5V
4.89V
Open
13
BLOCKING
1.02V
2.84V
28
M5V
4.89V
Open
14
DELTA_VY_O
0.35V
2.81V
29
Gnd
Gnd
Gnd
15
OC2_TOP
1.98V
2.84V
30
Gnd
Gnd
Gnd
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
113
Plasma
Video Signals from the Main Board to the Control Board are
referred to as Low Voltage Differential Signals or LVDS. The
video is delivered in dual 24 bit LVDS format. Their presence
can be confirmed with the Oscilloscope by monitoring the
LVDS signals with SMPTE Color Bar input. Loss of these
Signals would confirm the failure is on the Main Board or the
LVDS C
Cable
bl ititself.
lf
Example of LVDS Video Signal (613mV p/p)
10Msec
LVDS
2Msec
114
Plasma
Label
Pin
Pin
Label
Run
80
Gnd
Gnd
Gnd
53
Gnd
Gnd
Gnd
26
Gnd
Gnd
Gnd
79
n/c
n/c
2.23V
52
n/c
n/c
1.05V
25
RA2-
1.11V
1.05V
78
ROM_RX
3.3V
3.11V
51
n/c
n/c
1.05V
24
RA2+
1.3V
1.05V
77
ROM_TX
3.3V
3.11V
50
Gnd
Gnd
Gnd
23
RB2-
1.11V
1.05V
76
n/c
n/c
n/c
49
n/c
n/c
1.05V
22
RB2+
1.3V
1.05V
75
n/c
n/c
n/c
48
n/c
n/c
1.05V
21
Gnd
Gnd
Gnd
74
G d
Gnd
G d
Gnd
G d
Gnd
47
n/c
/
n/c
/
1 05V
1.05V
20
RC2
RC2-
1 11V
1.11V
1 05V
1.05V
73
n/c
n/c
1.05V
46
n/c
n/c
1.05V
19
RC2+
1.3V
1.05V
72
n/c
n/c
1.05V
45
n/c
n/c
1.05V
18
Gnd
Gnd
Gnd
71
n/c
n/c
1.05V
44
n/c
n/c
1.05V
17
RCLK2-
1.2V
1.05V
70
n/c
n/c
1.05V
43
Gnd
Gnd
Gnd
16
RCLK2-
1.2V
1.05V
69
Gnd
Gnd
Gnd
42
Gnd
Gnd
Gnd
15
RD2-
1.11V
1.05V
68
n/c
n/c
1.05V
41
RA1- 1.11V
1.05V
14
RD2+
1.3V
1.05V
67
n/c
n/c
1.05V
40
RA1+ 1.3V
1.05V
13
RE2-
1.11V
1.05V
66
Gnd
Gnd
Gnd
39
RB1- 1.11V
1.05V
12
RE2+
1.3V
Gnd
RB1+ 1.3V
1.05V
11
Gnd
Gnd
Gnd
Gnd
10
n/c
n/c
n/c
65
n/c
n/c
1.05V
38
64
n/c
n/c
1.05V
37
63
n/c
/
n/c
/
1 05V
1.05V
36
RC1 1.11V
RC11 11V
1 05V
1.05V
n/c
/
n/c
/
n/c
/
62
n/c
n/c
1.05V
35
RC1+ 1.3V
1.05V
n/c
n/c
n/c
Gnd
Gnd
Gnd
61
n/c
n/c
1.05V
34
60
n/c
n/c
1.05V
33
RCLK1- 1.2V
59
Gnd
Gnd
Gnd
32
RCLK1- 1.2V
1.05V
58
Gnd
Gnd
Gnd
31
RD1- 1.11V
1.05V
57
n/c
n/c
1.05V
30
RD1+ 1.3V
1.05V
56
n/c
n/c
1.05V
29
RE1- 1.11V
55
n/c
n/c
1.05V
28
RE1+ 1.3V
54
n/c
n/c
1.05V
27
Gnd
Gnd
Gnd
P31
Diode Check
Gnd
n/c
n/c
n/c
1.05V
Module_SDA1
3.3V
2.55V
DISP_EN
2.8V
2.55V
Module_SCL1
3.3V
2.55V
PC_SER_DATA
3.3V
2.55V
1.05V
PC_SER_CLK
0.5V
2.55V
1.05V
Gnd
Gnd
Gnd
Gnd
115
Plasma
P2 Label
Label
Run
Diode Check
15
(+18V)
18.34V
Open
14
(+18V)
18 34V
18.34V
O
Open
13
n/c
n/c
1.52V
12
M5V
4.89V
1.52V
11
M5V
4.89V
1.52V
10
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
SUS_DN
0.73V
Open
CTRL EN
CTRL_EN
0 06V
0.06V
Open
SUS_UP
0.15V
Open
VZB2
2.49V
Open
ER_DN
0.1V
Open
VZB1
2.53V
Open
ER_UP
0.87V
Open
ZBIAS
1.9V
Open
18V
P2
M5V
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
116
Plasma
Gnd
5V
5V
G d
Gnd
117
Plasma
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Label
TCP3_RSDS_A2P
TCP3_RSDS_A1N
TCP3_RSDS_A1P
Gnd
TCP4_RSDS_A3N
TCP4_RSDS_A3P
TCP4 RSDS A2N
TCP4_RSDS_A2N
TCP4_RSDS_A2P
TCP4_RSDS_A1N
TCP4_RSDS_A1P
Gnd
RSDS_CLK_N3
RSDS_CLK_P3
Gnd
TCP5_RSDS_A3N
TCP5_RSDS_A3P
TCP5_RSDS_A2N
TCP5 RSDS A2P
TCP5_RSDS_A2P
TCP5_RSDS_A1N
TCP5_RSDS_A1P
Gnd
STB0
STB1
X_ER_DN0
X_SUS_DN0
CE1_0
CE2_0
P0C0
BLK0
Gnd
Run
1.25V
1.18V
1.25V
Gnd
1.18V
1.25V
1 18V
1.18V
1.25V
1.18V
1.25V
Gnd
1.34V
1.08V
Gnd
1.18V
1.25V
1.18V
1 25V
1.25V
1.18V
1.25V
Gnd
3.2V
3.2V
0.42V
0.42V
0.42V
0.42V
1.89V
1 89V
1.89V
Gnd
Diode Check
Open
Open
Open
Gnd
Gnd
1.36V
1 36V
1.36V
3.09V
3.08V
Open
Gnd
Gnd
3.09V
Gnd
1.36V
1.32V
Gnd
Gnd
1.36V
1.36V
Gnd
1.36V
1.36V
1.32V
Gnd
1.36V
1.36V
1.36V
1 32V
1.32V
Gnd
1 4
1~4
3.3V
White hash
marks count
as 5
Note:
There are no voltages in
y mode.
Stand-By
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
118
Plasma
1~4
3.3V
Note:
There are no voltages in
Stand-By mode.
P102 "Control to P310 "X-Cent"
Pin
Label
Run
Diode Check
Pin
Label
Run
Diode Check
Pin
Label
Run
Diode Check
3.3V
3.28V
Open
21
TCP7_RSDS_A2P
1.25V
1.36V
41
Gnd
Gnd
Gnd
3.3V
3.28V
Open
22
TCP7_RSDS_A1N
1.18V
1.36V
42
RSDS_CLK_N3
1.34V
Gnd
3.3V
3.28V
Open
23
TCP7_RSDS_A1P
1.25V
1.36V
43
RSDS_CLK_P3
1.08V
3.09V
3.3V
3.28V
Open
24
Gnd
Gnd
Gnd
44
Gnd
Gnd
Gnd
n/c
n/c
n/c
25
RSDS_CLK_N1
1.34V
Gnd
45
TCP10_RSDS_A3N
1.18V
1.36V
n/c
n/c
n/c
26
RSDS_CLK_P1
1.08V
1.36V
46
TCP10_RSDS_A3P
1.25V
1.32V
Gnd
Gnd
Gnd
27
Gnd
Gnd
Gnd
47
TCP10_RSDS_A2N
1.18V
Gnd
TCP6_RSDS_A3N
1.18V
3.09V
28
TCP8_RSDS_A3N
1.18V
1.36V
48
TCP10_RSDS_A2P
1.25V
Gnd
TCP6_RSDS_A3P
1.25V
3.08V
29
TCP8_RSDS_A3P
1.25V
1.32V
49
TCP10_RSDS_A1N
1.18V
1.36V
10
TCP6_RSDS_A2N
1.18V
Open
30
TCP8_RSDS_A2N
1.18V
Gnd
50
TCP10_RSDS_A1P
1.25V
1.36V
11
TCP6_RSDS_A2P
1.25V
Open
31
TCP8_RSDS_A2P
1.25V
Open
51
Gnd
Gnd
Gnd
12
TCP6_RSDS_A1N
1.18V
Gnd
32
TCP8_RSDS_A1N
1.18V
Open
52
STB4
3.2V
1.36V
13
TCP6_RSDS_A1P
1.25V
3.09V
33
TCP8_RSDS_A1P
1.25V
Open
53
STB5
3.2V
1.36V
14
Gnd
Gnd
Gnd
34
Gnd
Gnd
Gnd
54
X_ER_DN2
0.42V
1.32V
15
RSDS_CLK_N0
1.34V
1.36V
35
TCP9_RSDS_A3N
1.18V
Gnd
55
X_SUS_DN2
0.42V
Gnd
16
RSDS_CLK_P0
1.08V
1.32V
36
TCP9_RSDS_A3P
1.25V
1.36V
56
CE1_2
0.42V
1.36V
17
Gnd
Gnd
Gnd
37
TCP9_RSDS_A2N
1.18V
1.36V
57
CE2_2
0.42V
1.36V
18
TCP7_RSDS_A3N
1.18V
Gnd
38
TCP9_RSDS_A2P
1.25V
3.09V
58
P0C1
1.89V
1.36V
19
TCP7_RSDS_A3P
1.25V
1.36V
39
TCP9_RSDS_A1N
1.18V
3.08V
59
BLK1
1.89V
1.32V
20
TCP7_RSDS_A2N
1.18V
1.36V
40
TCP9_RSDS_A1P
1.25V
Open
60
Gnd
Gnd
Gnd
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
119
Plasma
1~4
3.3V
Note:
There are no voltages in
Stand-By mode.
Label
Run
Diode Check
Pin
Label
Run
Diode Check
Pin
Label
Run
3.3V
3.28V
Open
p
21
TCP12_RSDS_A2P
_
_
1.25V
1.36V
41
Gnd
Gnd
Diode Check
Gnd
3.3V
3.28V
Open
22
TCP12_RSDS_A1N
1.18V
1.36V
42
RSDS_CLK_N11
1.34V
Gnd
3.09V
3.3V
3.28V
Open
23
TCP12_RSDS_A1P
1.25V
1.36V
43
RSDS_CLK_P11
1.08V
3.3V
3.28V
Open
24
Gnd
Gnd
Gnd
44
Gnd
Gnd
Gnd
n/c
n/c
n/c
25
RSDS_CLK_N9
1.34V
Gnd
45
TCP15_RSDS_A3N
1.18V
1.36V
n/c
n/c
n/c
26
RSDS_CLK_P9
1.08V
1.36V
46
TCP15_RSDS_A3P
1.25V
1.32V
Gnd
G
d
Gnd
G
d
Gnd
G
d
27
Gnd
G
d
Gnd
G
d
Gnd
G
d
47
TCP15
C 5_RSDS
S S_A2N
1.18V
8
Gnd
G
d
TCP11_RSDS_A3N
1.18V
3.09V
28
TCP13_RSDS_A3N
1.18V
1.36V
48
TCP15_RSDS_A2P
1.25V
Gnd
TCP11_RSDS_A3P
1.25V
3.08V
29
TCP13_RSDS_A3P
1.25V
1.32V
49
TCP15_RSDS_A1N
1.18V
1.36V
10
TCP11_RSDS_A2N
1.18V
Open
30
TCP13_RSDS_A2N
1.18V
Gnd
50
TCP15_RSDS_A1P
1.25V
1.36V
11
TCP11_RSDS_A2P
1.25V
Open
31
TCP13_RSDS_A2P
1.25V
Open
51
Gnd
Gnd
Gnd
12
TCP11_RSDS_A1N
1.18V
Gnd
32
TCP13_RSDS_A1N
1.18V
Open
52
STB4
3.2V
1.36V
13
1 25V
1.25V
3 09V
3.09V
33
1 25V
1.25V
Open
53
STB5
3 2V
3.2V
1 36V
1.36V
14
Gnd
Gnd
Gnd
34
Gnd
Gnd
Gnd
54
X_ER_DN2
0.42V
1.32V
15
RSDS_CLK_NB
1.34V
1.36V
35
TCP14_RSDS_A3N
1.18V
Gnd
55
X_SUS_DN2
0.42V
Gnd
16
RSDS_CLK_PB
1.08V
1.32V
36
TCP14_RSDS_A3P
1.25V
1.36V
56
CE1_2
0.42V
1.36V
17
Gnd
Gnd
Gnd
37
TCP14_RSDS_A2N
1.18V
1.36V
57
CE2_2
0.42V
1.36V
18
TCP12_RSDS_A3N
1.18V
Gnd
38
TCP14_RSDS_A2P
1.25V
3.09V
58
P0C1
1.89V
1.36V
19
1 25V
1.25V
1 36V
1.36V
39
1 18V
1.18V
3 08V
3.08V
59
BLK1
1 89V
1.89V
1 32V
1.32V
20
TCP12_RSDS_A2N
1.18V
1.36V
40
TCP14_RSDS_A1P
1.25V
Open
60
Gnd
Gnd
Gnd
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
120
Plasma
Plasma
122
Plasma
123
Plasma
IC53
4.98V
3.3V
G d
Gnd
3.3V
3 3V
3.3V
3 3V
3.3V
3.3V
3.3V
124
Plasma
Va
Data
Gnd
Gnd
3.3V
3.3V
Va
Gnd
50
EC
Va2
EC
125
Plasma
TCP
Attached directly
to Flexible cable
Y-SUS Board
Logic
X_B/D
Frame
e
Rear pane
el Vertical Add
dress
Frontt panel Horizo
ontal Address
384 Vertical
Electrodes
Va
Control Board
3.3V
TCP
Taped Carrier
Package
ac age
192 lines
Chocolate
384 lines
192 lines
Long Black
Heat Sink
126
Plasma
TCP Testing
On Va (0.42V)
On Va (Open)
On the below:
On Va2 (0.5V)
On 3.3V (0.44V)
p )
On EC ((Open)
Gnd Gnd
Va 3.3V
Va
3.3V
EC Gnd
EC
Gnd
On the below:
On Va (Open)
On 3.3V (1.15V)
On EC (Open)
n/c
Data
Data
n/c
1 5 10 15 20 25 30 35 40 45 50
127
Plasma
TCP
Taped
Carrier
Package
Look for burns, pin
holes, damage, etc.
128
Plasma
P120, P320
P320,, P321 and P320 Connector Va from Left to Center to Right X
Voltage and Diode Mode Measurement (No Stand-By Voltages)
All Connectors are 4 Pin
Pin
Label
Run
Diode Mode
1-2
VA
*55V
Open
p
3-4
Gnd
Gnd
Gnd
P120 Left X
P320 Center X
P321 Center X
P320 Right X
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
129
Plasma
P120, P220, P221 and P320 X Board Connector (VA Diode Check)
P120 Left X
P320 Center X
P321 Center X
Va Right
g 2 pins
p
B th C
Both
Connectors
t
Gnd Left 2 pins
On Chassis Gnd
Va Right
g 2 pins
p
B th C
Both
Connectors
t
Gnd Left 2 pins
On Chassis Gnd
P320 Right X
130
Plasma
Label
Run
Diode Mode
1-2
VA
*55V
Open
n/c
n/c
n/c
4-5
Gnd
Gnd
Gnd
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
131
Plasma
Label
Run
Diode Check
Gnd
Gnd
Gnd
BLK0
1.89V
P0C0
Pin
Label
Run
Diode Check
Pin
Label
Run
Diode Check
23 TCP4_RSDS_A2P
TCP4 RSDS A2P
1 25V
1.25V
Open
45
RSDS CLK P0
RSDS_CLK_P0
1 08V
1.08V
Open
Open
24 TCP4_RSDS_A2N
1.18V
Open
46
RSDS_CLK_N0
1.34V
Open
1.89V
Open
25 TCP4_RSDS_A3P
1.25V
Open
47
Gnd
Gnd
Gnd
CE2_0
0.42V
Open
26 TCP4_RSDS_A3N
1.18V
Open
48 TCP1_RSDS_A1P
1.25V
Open
CE1_0
0.42V
Open
27
Gnd
Gnd
49 TCP1_RSDS_A1N
1.18V
Open
X_SUS_DN0
0.42V
Open
28 TCP3_RSDS_A1P
1.25V
Open
50 TCP1_RSDS_A2P
1.25V
Open
X_ER_DN0
0.42V
Open
29 TCP3_RSDS_A1N
1.18V
Open
51 TCP1_RSDS_A2N
1.18V
Open
STB1
3.2V
Open
30 TCP3_RSDS_A2P
1.25V
Open
52 TCP1_RSDS_A3P
1.25V
Open
STB0
3.2V
Open
31 TCP3_RSDS_A2N
1.18V
Open
53 TCP1_RSDS_A3N
1.18V
Open
10
Gnd
Gnd
Gnd
32 TCP3_RSDS_A3P
1.25V
Open
54
Gnd
Gnd
Gnd
11
TCP5_RSDS_A1P
1.25V
Open
33 TCP3_RSDS_A3N
1.18V
Open
55
n/c
n/c
Open
12
TCP5_RSDS_A1N
1.18V
Open
34
Gnd
Gnd
Gnd
56
n/c
n/c
Open
13
TCP5_RSDS_A2P
1.25V
Open
35
RSDS_CLK_P1
1.08V
Open
57
3.3V
3.28V
Open
14
TCP5_RSDS_A2N
1.18V
Open
36
RSDS_CLK_N1
1.34V
Open
58
3.3V
3.28V
Open
15
TCP5_RSDS_A3P
1.25V
Open
37
Gnd
Gnd
Gnd
59
3.3V
3.28V
Open
16
TCP5_RSDS_A3N
1.18V
Open
38 TCP2_RSDS_A1P
1.25V
Open
60
3.3V
3.28V
Open
17
Gnd
Gnd
Gnd
39 TCP2_RSDS_A1N
1.18V
Open
18
RSDS_CLK_P3
1.08V
Open
40 TCP2_RSDS_A2P
1.25V
Open
19
RSDS_CLK_N3
1.34V
Open
41 TCP2_RSDS_A2N
1.18V
Open
20
Gnd
Gnd
Gnd
42 TCP2_RSDS_A3P
TCP2 RSDS A3P
1 25V
1.25V
Open
21
TCP4_RSDS_A1P
1.25V
Open
43 TCP2_RSDS_A3N
1.18V
Open
22
TCP4_RSDS_A1N
1.18V
Open
44
Gnd
Gnd
Gnd
Gnd
57~60
57~60 pins
3.3V TP
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
132
Plasma
Label
Run
Diode Check
Pin
Label
Gnd
Gnd
Gnd
BLK1
1.89V
Open
24 TCP9_RSDS_A2N
1.18V
P0C1
1.89V
Open
25 TCP9_RSDS_A3P
1.25V
CE2_2
0.42V
Open
26 TCP9_RSDS_A3N
1.18V
Open
CE1_2
0.42V
Open
27
Gnd
X SUS DN2
X_SUS_DN2
0 42V
0.42V
O
Open
28 TCP8_RSDS_A1P
TCP8 RSDS A1P
1 25V
1.25V
X_ER_DN2
0.42V
Open
29 TCP8_RSDS_A1N
1.18V
STB5
3.2V
Open
30 TCP8_RSDS_A2P
1.25V
STB4
3.2V
Open
31 TCP8_RSDS_A2N
1.18V
10
Gnd
Gnd
Gnd
32 TCP8_RSDS_A3P
1.25V
11 TCP10_RSDS_A1P
TCP10 RSDS A1P 1.25V
1 25V
Open
33 TCP8_RSDS_A3N
TCP8 RSDS A3N
1 18V
1.18V
Open
12 TCP10_RSDS_A1N 1.18V
Open
34
Gnd
Gnd
Gnd
56
n/c
n/c
Open
13 TCP10_RSDS_A2P 1.25V
Open
35
RSDS_CLK_P1
1.08V
Open
57
3.3V
3.28V
Open
14 TCP10_RSDS_A2N 1.18V
Open
36
RSDS_CLK_N1
1.34V
Open
58
3.3V
3.28V
Open
15 TCP10_RSDS_A3P 1.25V
Open
37
Gnd
Gnd
Gnd
59
3.3V
3.28V
Open
16 TCP10_RSDS_A3N 1.18V
p
Open
38 TCP7_RSDS_A1P
1.25V
Open
p
60
3.3V
3.28V
Open
p
17
Gnd
Gnd
Gnd
39 TCP7_RSDS_A1N
1.18V
Open
60
3.3V
3.28V
Open
18
RSDS_CLK_P3
1.08V
Open
40 TCP7_RSDS_A2P
1.25V
Open
19
RSDS_CLK_N3
1.34V
Open
41 TCP7_RSDS_A2N
1.18V
Open
20
Gnd
Gnd
Gnd
42 TCP7_RSDS_A3P
1.25V
Open
21
TCP9_RSDS_A1P
1.25V
Open
43 TCP7_RSDS_A3N
1.18V
Open
22
TCP9_RSDS_A1N
1.18V
Open
44
Gnd
Gnd
23 TCP9_RSDS_A2P
Gnd
Gnd
Run
Diode Check
Pin
Label
Run
Diode Check
1.25V
Open
45
RSDS_CLK_P0
1.08V
Open
Open
46
RSDS_CLK_N0
1.34V
Open
Open
47
Gnd
Gnd
Gnd
48 TCP6_RSDS_A1P
1.25V
Open
Gnd
49 TCP6_RSDS_A1N
1.18V
Open
O
Open
50 TCP6_RSDS_A2P
TCP6 RSDS A2P
1 25V
1.25V
O
Open
Open
51 TCP6_RSDS_A2N
1.18V
Open
Open
52 TCP6_RSDS_A3P
1.25V
Open
Open
53 TCP6_RSDS_A3N
1.18V
Open
Open
54
Gnd
Gnd
Gnd
55
n/c
n/c
Open
57~60
57~60 pins
3.3V TP
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
133
Plasma
Label
Run
Diode Check
Gnd
Gnd
Gnd
BLK1
1.89V
P0C1
Pin
Label
Run
Diode Check
Pin
Label
Run
Diode Check
23 TCP14_RSDS_A2P
1.25V
Open
p
45
RSDS_CLK_PB
1.08V
Open
p
Open
24 TCP14_RSDS_A2N
1.18V
Open
46
RSDS_CLK_NB
1.34V
Open
1.89V
Open
25 TCP14_RSDS_A3P
1.25V
Open
47
Gnd
Gnd
Gnd
CE2_2
0.42V
Open
26 TCP14_RSDS_A3N
1.18V
Open
48 TCP11_RSDS_A1P
1.25V
Open
CE1_2
0.42V
Open
27
Gnd
Gnd
49 TCP11_RSDS_A1N
1.18V
Open
X SUS DN2
X_SUS_DN2
0 42V
0.42V
Open
28 TCP13_RSDS_A1P
TCP13 RSDS A1P
1 25V
1.25V
Open
50 TCP11_RSDS_A2P
TCP11 RSDS A2P
1 25V
1.25V
Open
X_ER_DN2
0.42V
Open
29 TCP13_RSDS_A1N
1.18V
Open
51 TCP11_RSDS_A2N
1.18V
Open
STB5
3.2V
Open
30 TCP13_RSDS_A2P
1.25V
Open
52 TCP11_RSDS_A3P
1.25V
Open
STB4
3.2V
Open
31 TCP13_RSDS_A2N
1.18V
Open
53 TCP11_RSDS_A3N
1.18V
Open
10
Gnd
Gnd
Gnd
32 TCP13_RSDS_A3P
1.25V
Open
54
Gnd
Gnd
Gnd
11 TCP15_RSDS_A1P 1.25V
Open
33 TCP13_RSDS_A3N
1.18V
Open
55
n/c
n/c
Open
12 TCP15_RSDS_A1N 1.18V
Open
34
Gnd
Gnd
Gnd
56
n/c
n/c
Open
13 TCP15_RSDS_A2P 1.25V
Open
35
RSDS_CLK_P9
1.08V
Open
57
3.3V
3.28V
Open
14 TCP15_RSDS_A2N 1.18V
Open
36
RSDS_CLK_N9
1.34V
Open
58
3.3V
3.28V
Open
15 TCP15_RSDS_A3P 1.25V
Open
37
Gnd
Gnd
Gnd
59
3.3V
3.28V
Open
16 TCP15_RSDS_A3N 1.18V
Open
38 TCP12_RSDS_A1P
1.25V
Open
60
3.3V
3.28V
Open
17
Gnd
Gnd
Gnd
39 TCP12_RSDS_A1N
1.18V
Open
18
RSDS_CLK_P11
1.08V
Open
40 TCP12_RSDS_A2P
1.25V
Open
19
RSDS_CLK_N11
1.34V
Open
41 TCP12_RSDS_A2N
1.18V
Open
20
Gnd
Gnd
Gnd
42 TCP12_RSDS_A3P
TCP12 RSDS A3P
1.25V
Open
21 TCP14_RSDS_A1P 1.25V
Open
43 TCP12_RSDS_A3N
1.18V
Open
22 TCP14_RSDS_A1N 1.18V
Open
44
Gnd
Gnd
Gnd
Gnd
57~60
57~60 pins
3.3V TP
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
134
Plasma
Distributes Key_CTL_0 and Key_CTL_1 to the Front IR Board for Front Key Pad
detection.
Receives Intelligent Sensor data from the Front IR/Key Board (via SCL/SDA).
Drives front Power LEDs.
Distributes +3.3V_ST and 5V_MST to the Front IR Board.
135
Plasma
P701
LVDS
P301 to
SMPS
IC1
Microprocessor
Video p
processor
P704
to Ft IR
USB 1
HDMI 3
P801
Speakers
Silicon
Tuner
HDMI 2
HDMI 1
136
Plasma
Label
a
17V
Gnd
a
5.1V
Stby
0V
Gnd
0.46V
ac
Error_Det 2.87V
Gnd
Gnd
3.4V
Stby_5V
a
0V
RL_ON
ad
AC_Det
0V
b
0V
M_On
e
Auto_Gnd Gnd
Run
17V
Gnd
5.1V
4.9V
Gnd
5.1V
2.4V
Diode
OL
Gnd
0.88V
3.05V
Gnd
1.02V
2.6V
4.4V
3.2V
Gnd
2.92V
OL
Gnd
P701
MAIN BOARD
p/n: EBU60952917 or
p/n: EBR72650101
D2
P301
Gnd Out
C
G
A1
A2
IC201
In
L313 IC308
123
IC302
DDR
3.3VST
IC301
2
1.8V_MST
Q302
IC704
NVRAM
Diode
Open
Open
Open
Open
RUN
Audio Amp
Gnd
IC502
3.3V
3.3V
0V
Gnd
1.18V
1.18V
OL
Gnd
3.1V
3.1V
Gnd
OL
OL
Gnd
3.3V
1.3V
5V
0V
1.24V
1.02V
1.75V
OL
OL
B
4 3
1
A2
X1
Micro/Video
Microprocessor
IC304
Q304
RS232 Buffer
Grayed Out
Components are on the back
A1
D504
Q303
In OG
TUNER
Q402
+1.2V_DVDD
E
+3.3V_MST
C
B
D505
A1
Q404
3.3V_TU
123
E
B
EDID
IC305
IC401
Q503
A2
IC504
123
Tuner Control
E
C
Q702
A2
Q502
IC503
EDID
Q504 HDMI3
Out
EG
CEC FET
A1
X402
25Mhz
X401 31.875Mhz
E
C
Q501
D501
A1
D502
Gnd
IC402
12Mhz
IC703
3.14V
0.19V
n/c
n/c
A2
C
3.9V
PVSB Processor
D1
IC801
EDID
USB 5V
Mstar
3.3V_MST
P801
HDCP
Flash Memory
IC303
Diode Chk
1.3V_VDDC
5V_MST
P704
Q301
IC307
IC602
1.8V_TU
AV IN 2
137
May 2011
50PV450 Plasma
MAIN BOARD
p/n: EBU60952917 or
p/n: EBR72650101
P701
D2
P301
A2
A1
IC201
L313
IC308
DDR
1.3V_VDDC
IC203
P704
Flash Memory
HDMI3
Mstar
To Speakers
(All Pins 8.5V)
IC801
A1
Audio Amp
P801
IC402
D1
A2
X1
12Mhz
Micro/Video
Microprocessor
X402
25Mhz
PVSB Processor
TUNER
Q402
E
X401 31.875Mhz
CEC FET
4
Q502
C
B
A2
Q404
D505
A1
D501
A1
C
IC401
A2
Tuner Control
D504
AV IN 2
A1
A2
138
May 2011
50PV450 Plasma
IC203
inbond Serial
Pin Flash
[1] 3.3V
[9]
[2] 3.3V
[10]
[3] n/c
[11]
[4] n/c
[12]
[5] n/c
[13]
[6] n/c
[14]
[7] 0.08V
[15]
[8] 3.3V
[16]
Q402
0V
Gnd
n/c
n/c
n/c
n/c
0.08V
0.08V
+1.3V_VDDC
Pin Regulator
[1] 0.8V*
[2] 0V
[[3]] 5V
[4] 6.1V
[5] 5V
[6] 1.3V
[7] 1.3V
[8] 4.5V
*Caused Video to Mute
Pin
[B]
[E]
[C]
Tuner CVBS
Buffer (Analog)
1.1V
1.7V
Gnd
Pin
[B]
[E]
[C]
Tuner SIF
Buffer (Digital)
1.2V
1.8V
Gnd
Q404
IC308
Q502
Pin
[1 B]
[[2 S]]
[3 D]
[4 G]
139
HDMI CEC
Buffer
Gnd
3.18V
3.29V
3.3V
MAIN BOARD
p/n: EBU60952917 or
p/n: EBR72650101
IC301
3.3VST
321
IC501 IC202
IC704
IC302
Out Gnd
1.8V_MST
B
C
In
Q301
Q302
5V_MST
HDCP
NVRAM
USB 5V
IC303
3.3V_MST
Q504
E
IC304
Q304
Out
G O In
+1.2V_DVDD
IC504
GE
Q303
RS232 Buffer
D502
+3.3V_MST
IC703
EDID
3 21
IC305
3.3V_TU
Q702
3 21
IC307
2
EDID
IC502
Q501
IC503
B
Q503
E
EDID
1.8V_TU
IC602
RGB & Earphone Audio
140
May 2011
50PV450 Plasma
IC202
NVRAM
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Gnd
Gnd
Gnd
Gnd
3.3V
3.3V
Gnd
3.3V
Pin
[1]
[2]
[3]
1.8V_MST
Regulator
0.6V
1.8V (Out)
3.3V (In)
IC307
Pin
[1]
[2]
[3]
3.3V_VST
Regulator
Gnd
3.3V (Out)
5.09V (In)
IC501
Pin
[1]
[2]
[3]
3.3V_MST
Regulator
Gnd
3.3V (Out)
5.04V (In)
IC301
IC302
IC303
Q301
IC703
IC304
1.2V_DVDD Reg
Pin
Dig Ch Only
[1] Gnd
[2] 1.2V (Out)
[3] 3.3V (In)
IC305
Q302
Pin
[1]
[2]
[3]
3.3V_TU
Regulator
2.1V
3.3V (Out)
5.1V (In)
Pin
[1]
[[2]]
[3]
1.8V_TU
Regulator
Gnd
1.8V ((Out))
3.3V (In)
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
HDCP Data
EEPROM
Gnd
Gnd
3.3V
Gnd
3.3V
3.3V
3.3V
3.3V
5V_MST
IC502
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
IC503, IC504
EDID Data
For HDMI
Gnd
Gnd
Gnd
Gnd
3.3V
3.3V
3.3V
3.3V
Pin
[1]
[[2]]
[3]
[4]
[5]
[6]
[7]
[8]
RGB
Earphone Amp
Gnd
Gnd
Gnd
Gnd
5.09V
5.09V
0V
5.09V
IC602
Q303
Q304
3.3V
5.6V
0V
0V
(-5.5V)
(-5.5V)
(-5.5V)
0V
3.3V
3.3V
n/c
n/c
0V
5.6V
Gnd
3.3V ((B+))
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
USB 5V
Limiter
Gnd
5.1V (In)
5.1V (In)
3.3V
0V
5.1V (Out)
5.1V (Out)
n/c
IC704
3.3V_PVSB
Pin
Dig Ch Only
[G] 0V
Only on
[S] 3.3V with Dig
[D] 3.3V Channel
urns on 3.3V_PVSB
RS232 Tx/Rx
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[[16]]
Q501, Q503
Q504
Hot Swap
141
Q702
Pin
[B]
[C]
[E]
D502
RS232
Tx Buffer
0.6V
0V
Gnd
142
Plasma
1.49V
X1 Runs
R
all
ll the
th time
ti
(Micro
(Mi
C t l)
Crystal)
X402 25MHZ
X402
1.48V
1.6V
X1
MAIN Board
Crystal Location
143
Plasma
Main Board Plug P301 to Power Supply Voltages and Diode Check
P301 "Main" to P813 "SMPS"
Pin
Label
P301
STBY
Run
Diode Check
1_2
17V
0V
17V
OL
3-4
3
4
Gnd
Gnd
Gnd
Gnd
5.1V
0.46V
5.1V
0.88V
Error_Det
2.87V
4.9V
3.05V
5-7
8
ac
9-12
Gnd
Gnd
Gnd
Gnd
13-14
STBY_5V
3.4V
5.1V
1.02V
0V
2.4V
2.6V
AC Det
0V
4.4V
2.92V
M_ON
0V
3.2V
OL
Auto_Gnd
Gnd
Gnd
Gnd
15
16
ad
17
18
RL_ON
Pin c front
a Note:
The RL_On command turns on the 17V, +5V, Error_Det and AC_DET.
b Note: The M-On command turns on M5V
M5V, Va and Vs
Vs.
c Note: The Error Det line is not used in this model.
d Note: AC Det line if missing, the TV will attempt to turn on, but shut right back off.
e Note: Pin 18 is grounded on the Main. If opened, the power supply turns on automatically.
Diode Mode Check with the Board Disconnected. DVM in the Diode mode.
144
Plasma
Label
STBY
Run
Diode Check
IR
3.3V
3.9V
3.14V
Gnd
Gnd
Gnd
Gnd
Key_CTL_0
3.3V
3.3V
1.81V
Key_CTL_1
3.3V
3.3V
1.81V
LED_RED
2.7V
0V
OL
Gnd
Gnd
Gnd
Gnd
EYE_SCL
3.1V
3.1V
OL
EYE_SDA
3.1V
3.1V
OL
Gnd
Gnd
Gnd
Gnd
Stand-By 3.3V
10
3.3VST
3.3V
3.3V
1.3V
3.3V_Multi
is actually
+5V_MST
11
3.3V_MST
0V
5V
1.24V
12
LED_BLUE
0V
0V
1.02V
13
Touch_Ver_Check
0.19V
0.19V
1.75V
14
n/c
n/c
n/c
OL
15
n/c
/
n/c
/
n/c
/
OL
Infrared
Remote
3&4
Function
Buttons
7&8
Intelligent
Sensor
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
145
Plasma
Label
SBY
Run
Diode Check
R
R-
0V
8 V
8.5V
O
Open
R+
0V
8.5V
Open
L-
0V
8.5V
Open
L+
0V
8.5V
Open
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
146
Plasma
AUDIO B+ 17V
Pins 2,3, 44, 45 (Left)
Pins 34, 35, 40, 41 (Right)
IC801
Audio Amp
DATA pin 23
SCLK pin 24
147
Plasma
148
Plasma
Pin
Pin
Ctl Board Main Board
40
41
39
42
38
43
37
44
36
45
35
46
34
47
33
48
32
49
31
50
30
51
29
52
28
53
27
54
26
55
25
56
24
57
23
58
22
59
21
60
20
61
19
62
18
63
17
64
16
65
15
66
14
67
13
68
12
69
11
70
10
71
9
72
8
73
7
74
6
75
5
76
4
77
3
78
2
79
1
80
1
Pin 68 RE2613mV 10MSec
p/p
per/div
Pin 69 RE2+
149
Plasma
P701 "Main LVDS" to P31 "Control" Note: For Voltage Measurements, use the Control Board.
Pin
Label
Run
Diode
Pin
Label
Run
Diode
Pin
Label
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Gnd
n/c
ROM_RX
ROM_TX
n/c
n/c
G d
Gnd
n/c
n/c
n/c
n/c
Gnd
n/c
n/c
Gnd
n/c
n/c
n/c
n/c
n/c
n/c
Gnd
Gnd
n/c
n/c
n/c
Gnd
n/c
3.3V
3.3V
n/c
n/c
G d
Gnd
n/c
n/c
n/c
n/c
Gnd
n/c
n/c
Gnd
n/c
n/c
n/c
n/c
n/c
n/c
Gnd
Gnd
n/c
n/c
n/c
Gnd
OL
1.17V
1.17V
OL
OL
G d
Gnd
OL
OL
OL
OL
Gnd
OL
OL
Gnd
OL
OL
OL
OL
OL
OL
Gnd
Gnd
OL
OL
OL
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
n/c
Gnd
n/c
n/c
Gnd
n/c
n/c
/
n/c
n/c
n/c
n/c
Gnd
Gnd
RA1RA1+
RB1RB1+
Gnd
RC1RC1+
Gnd
RCLK1RCLK1RD1RD1+
RE1RE1+
n/c
Gnd
n/c
n/c
Gnd
n/c
n/c
/
n/c
n/c
n/c
n/c
Gnd
Gnd
1.11V
1.3V
1.11V
1.3V
Gnd
1.11V
1.3V
Gnd
1.2V
1.2V
1.11V
1.3V
1.11V
1.3V
OL
Gnd
OL
OL
Gnd
OL
OL
OL
OL
OL
OL
Gnd
Gnd
0.73V
0.73V
0.73V
0.73V
Gnd
0.73V
0.73V
Gnd
0.73V
1.04V
0.73V
0.73V
0.73V
0.73V
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Gnd
Gnd
RA2RA2+
RB2RB2+
G d
Gnd
RC2RC2+
Gnd
RCLK2RCLK2RD2RD2+
RE2RE2+
Gnd
n/c
n/c
n/c
n/c
Module_SDA1
DISP_EN
_
Module_SCL1
Run
Diode
Gnd
Gnd
1.11V
1.3V
1.11V
1.3V
G d
Gnd
1.11V
1.3V
Gnd
1.2V
1.2V
1.11V
1.3V
1.11V
1.3V
Gnd
n/c
n/c
n/c
n/c
3.3V
2.8V
3.3V
PC_SER_DATA 3.3V
PC_SER_CLK 0.5V
Gnd
Gnd
Gnd
Gnd
0.73V
0.73V
0.73V
0.73V
G d
Gnd
0.73V
0.73V
Gnd
0.73V
1.04V
0.73V
0.73V
0.73V
0.73V
Gnd
n/c
n/c
n/c
n/c
2.6V
0.48V
2.6V
1.44V
0.98V
Gnd
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
150
Plasma
3.3V_ST from the Main Board. This voltage is generated on the Power Supply.
It is output on P704 pin 10. It arrives on the IR/STKB at P100 pin 10.
3.3V_MST Generated on the Main Board by IC303 and output on P704 pin 11.
It arrives on the IR/STKB at P100 pin 11.
151
Plasma
IR Receiver
P100
To Main
Key Pad
D
Decoder
d
IC102 IR Receiver
O
Label
V: B+
O: Output
G Ground
G:
G
d
152
Readings
0V
3.24V
2 85V
2.85V
Plasma
P901 (IR / STKB and Intelligent Sensor )Voltages and Pin Identification
P901 Connector "MAIN Board" To "IR Board"
Pin
Label
STBY
Run
Diode Check
SCL
2.9V
3.49V
3.28V
SDA
2.92V
3.49V
3.28V
Gnd
Gnd
Gnd
Gnd
KEY 1
3.26V
3.28V
1.88V
KEY 2
3.26V
3.28V
1.88V
3.5V_ST
3.55V
3.49V
1.15V
Gnd
Gnd
Gnd
Gnd
LED_B/BUZZ
0V
0V
OL
IR
1.48V
1.45V
OL
10
G d
Gnd
G d
Gnd
G d
Gnd
G d
Gnd
11
+3.3V_Normal
0.35V
3.34V
0.53V
12
LED_R/BUZZ
0V
0V
2.67V
13
Gnd
Gnd
Gnd
Gnd
14
S/T_SCL
3.55V
3.49V
1.86V
15
S/T_SDA
3.55V
3.49V
1.86V
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
153
Plasma
Key 2 Line
KEY 1
KEY 2
Power
2.4V
Enter
2.4V
CH (Up)
0.21V
Volume (-)
0.21V
CH (Dn)
1.6V
Menu
1.6V
Input
0.88V
Volume (+)
0.88V
L b l
Label
STBY
R
Run
KEY 1
3.26V
3.28V
KEY 2
3.26V
3.28V
154
Plasma
p/n: EAB62028901
Anti Rattle
Pad
Rear View
Reading across
speaker wires,
8.2 ohm.
Front View
Speaker
Connection
155
Plasma
156
Plasma
VR402
Set-up
FPC
P101
0V
100V 2MSec
FPC
P103
IC191
Waveform
1
3
10.9VFG
D505
P104
23.77VFG
P210
IC50
0
IC501
D501
10.9VFG
D511
FS202 (M5V)
10A / 125V
D512
18.34V
P104
P215
D515
IC302
FGnd
FS201 (VA)
4A / 125V
FS501 (18V)
2A / 125V
VR401
Set-Dn
P121
VScan
D500
VR500
+Vy
VSC
R548
P201
VR402
Set-Up
C540
FGnd
P217
Y-Scan
J113
Gnd
P212
Va
*55V
Open
M5V
5.0V
1.38V
P216
CTRL_OE
P202
FPC
VS Adj
VR901
Chassis Gnd
Pin
Label
Run
Diode Check
M5V
4.96V
1.38V
M5V
4.96V
1.38V
OC2_B
2.77V
Open
Gnd
Gnd
Gnd
DATA_B
0V
1.85V
Gnd
Gnd
Gnd
Chassis Gnd
OC1_B
OC2_T
Gnd
10
11
1.73V
1.85V
2.73V
Open
Gnd
Gnd
DATA_T
0V
1.85V
Gnd
Gnd
Gnd
P204
12
OC1_T
1.74V
1.85V
13
Gnd
Gnd
Gnd
14
CLK
0.68V
1.85V
15
STB
4.27V
1.85V
Diode Check
Open
nc
Gnd
P202
Run
Diode
15
(+15V)
18.34V
Open
14
(+15V)
18.34V
Open
F101
10A/250V
13
n/c
n/c
1.52V
12
M5V
4.89V
1.52V
11
M5V
4.89V
1.52V
10
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
SUS_DN
0.73V
Open
CTRL_EN
0.06V
Open
SUS_UP
0.15V
Open
VZB2
2.49V
Open
ER_DN
0.1V
Open
VZB1
2.53V
Open
ER_UP
0.87V
Open
ZBIAS
1.9V
Open
100uSec
FS201 (VS)
6.3A / 250V
57VRms
D118
Q114
57VRMS
D110
J21 18V
P22
n/c
C61
To
Y-SUS
Board
4.89V
IC101
IC25
3) 4.93V
2) 3.29V
1) Gnd
IC102
M5V
1-4
(3.3V)
IC53
P214 "Y-SUS" to "Upper Y-Drive" P111 P215 "Y-SUS" to "Upper Y-Drive" P112
Pin
Label
Run
Pin
Label
Run
1-2
FG10.9V
4.89V
1-7
FGnd
FGnd
3-12
FGnd
FGnd
n/c
n/c
9-12
Vscan
107V
Pin
Label
Run
1-4
Vscan
107V
Pin
Label
Run
n/c
n/c
1-10
FGnd
FGnd
6-12
FGnd
FGnd
11-12
Vscan
107V
Pin
Run
Diode Check
1-2
Gnd
Gnd
3
*4-5
nc
nc
VA Voltage
Open
3.3V
0.02V
P2
FL5
IC61
Q107
Q103
Q110
1.63V
25
Mhz
1.69V
IC1
VS-DA
TP
P102
4.89V
1-4
(3.3V)
IC53
IC53
To Center
X Board
3) 4.89V
2) 3.3V
1) Gnd
P202
P121
X-Board Left
p/n: EBR71728101
P204
P110
3.3V in
on Pins
57~60
P120
Va out
on Pins
1~2
P205
P320
Va in on
Pins 1~2
P201
P310
3.3V in on
Pins 57~60
P202
P203
Diode
Open
Open
Open
Open
P701
P301
PANEL
TEST:
Remove LVDS
Cable. Short
across Auto
Gen TPs to
generate a test
pattern.
D2
C
Q301
G
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Label
IR
Gnd
Key_Ctl_0
STBY
RUN
Diode Chk
3.3V
3.9V
3.14V
Gnd
Gnd
Gnd
Key_Ctl_1
LED_Red
Gnd
3.3V
3.3V
2.7V
Gnd
3.3V
3.3V
0V
Gnd
1.18V
1.18V
OL
Gnd
EYE_SCL
EYE_SDA
Gnd
3.1V
3.1V
Gnd
3.1V
3.1V
Gnd
OL
OL
Gnd
3.3_VST
3.3_MST
LED_Blue
Touch_Ver_Check
n/c
n/c
3.3V
3.3V
0V
0V
5V
0V
0.19V
n/c
n/c
0.19V
n/c
n/c
To Ft IR
IC301
L313 IC308
12 3
1.8V_MST
NVRAM
Flash Memory
Mstar
A2
C
A1
Audio Amp
EDID
PVSB Processor
IC402
+1.2V_DVDD
X1
12Mhz
Micro/Video
Microprocessor
Q304
B
EG
C
Grayed Out
Components are on the back
IC304
A2
A1
Q303
TUNER
E
X401 31.875Mhz
A1
123
D504
A1
EDID
P204
P205
P320
Va in on
Pins 1~2
P201
P310
3.3V in on
Pins 57~60
IC602
3.3V_TU
1.8V_TU
AV IN 2
On Va (Open)
On 3.3V (1.15V)
On EC (Open)
TCP
P202
IC307
P321
Va out on
Pins 1~2
A2
123
Q503
D505
IC305
IC401
Tuner Control
C
B
Q404
IC504
Q502
Q702
A2
C
Q402
+3.3V_MST
IC503
EDID
In OG
Q504 HDMI3
Out
E
C
X402
25Mhz
S
D
4 3
1
USB 5V
D1
IC801
IC502
IC704
HDCP
P801
1.3V_VDDC
Q302
IC303
To
Speakers
IC201
DDR
3.3VST
3.3V_MST
1.3V
1.24V
1.02V
1.75V
OL
OL
A2
IC302
In
5V_MST
P704
A1
Gnd Out
X-Board Center
p/n: EBR71728401
P203
P103
MAIN BOARD
p/n: EBU60952917 or
p/n: EBR72650101
To P704 Main A
Ft IR/Key Pad
18V To Z-SUS
(In P105 pins 14-15)
(Out P2 pins 14-15)
Diode Check All Connectors
Connected 1.28V
To Right
X Board
P206
P104
P102
Ribbon Cable
LVDS
P31
LVDS
AUTO
Gen
C72
P205
M5V
P100
IR/Key Board
p/n: EBR72650101
M5V
FL1, FL2, FL5
CONTROL BOARD
p/n: EBR71727801
Gnd 3.26V
Gnd X1
0.65V
P101
J54 Z-Drive
Waveform TP
FS202 (M5V)
4A / 125V
3.26V
C76
1.04V
1.04V
Q1
1-4
(3.3V)
IC53
4.89V
Gnd
D1
IC11
Diode Check
Va: Open Blk on Gnd.
P203
1.84V
C65
1.84V
To Left
X Board
D1 Blinks
Indicating Board is
Functioning
Gnd
IC51
L1
1.85V
L2
FL1/2
P201
D114
D108
P201
288V p/p
P204
D111
J16
M5V
2MSec
Z-SUS
EBR71727901
Q102
ER_UP
ER_DN
SUS_DN
50V
Z-SUB BOARD
p/n: EBR71728001
M5V
P105
261V p/p
Q109
P701
n/c
C52
FS202 M5V
Diode Check reads
0.73V Board Connected
1.52V Disconnected
Z-SUS Signal
Q113
VZB TP
R156
P813
AC In
1-2) ER
3) n/c
4-5) VS
6) n/c
7-8) Gnd
Q106
Gnd
Gnd
Label
Q104
Diode
Open
n/c
Open
n/c
Gnd
Pin
VA Adj
VR502
RL103
Ribbon Cable
Y-SUS and Y Drive Signals
VR101
VZB Adj
POWER SUPPLY
p/n: EAY62171101
P101
F302
2.5A/
250V
P213
P203
FPC
3.1V
OL
OL
Note a:
The RL_On command turns on the
17V, +5V, Error_Det and AC_DET.
Note b:
The M-On command turns on M5V,
Va and Vs.
Note c:
The Error Det line is not used in this
model.
Note d:
AC Det if missing TV will attempt to
turn on but shuts back off.
Note e:
Pin 18 is grounded on the Main. If
opened, the power supply turn on
automatically.
VS TP
CTRL_OE should be 0V
(5V indicates a Problem)
P203
P201
4.4V
3.2V
Gnd
1.04V
Run
VA Voltage
nc
Gnd
Diode
3.06V
Gnd
2.13V
2.84V
Gnd
2.53V
OL
F801
4A/250V
Hot
Ground
P213
Y-Drive
Lower
VA TP
VS
VS
n/c
Gnd
Gnd
Va
M5V
Run
17V
Gnd
5.1V
4.9V
Gnd
5.1V
2.4V
F302/F801
160.1V STBY
390V Run
P102
Waveform
Scan
Data
M5V
Stby
0V
Gnd
0.46V
ac
Error_Det 2.87V
Gnd
Gnd
3.4V
Stby_5V
a
0V
RL_ON
ad
0V
AC_Det
b
0V
M_On
e
Auto_Gnd Gnd
16
17
18
FS501 18V
Diode Check reads
1.28V Board
Connected or 1.31V
Disconnected
Y-Scan
FPC
Label
a
17V
Gnd
a
5.1V
With the unit on, if D1 is not on, check 5V supply. If present replace the Control Board.
If missing, see (To Test Power Supply)
Y-SUS
EBR69839001
FGnd
n/c
Gnd
FS202 M5V
Diode Check reads
0.73V Board
Connected or 1.38V
Disconnected
FS203 (VS)
6.3A / 250V
T500
D503
P214
P221
P211
n/c
Gnd
560V p/p
P218
D502
+Vy
R527
J33
Y-Scan
n/c
Gnd
FS201 Va or FS203 Vs
Diode Check reads Open
with Board Disconnected or
Connected
P112
3
4~5
FGnd
FPC
100uS
VR501
VSC
FGnd
FPC
100V
*201V
P111
FG10.9V
Diode
Open
Vs
P811
IC191
1 5VFG
2 FGnd
3 10.9VFG
180uSec
5uSec
J81
FPC
P102
WARNING:
Remove Y-Drives
completely if
P213 is removed.
T502
Y-Drive
Upper
560V p/p
VR401
Set-Dn
Pin
1,2
3
4,5
Pin
1-2
3-4
5-7
8
9-12
13-14
15
107VRMS
345V p/p 5V
P203
P203
P204
X-Board Right
p/n: EBR71728501
P205
50PV450 LVDS P31 Control Board from P701 Main Board Waveform Samples
P31
Control
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
P701
Main
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
23
58
Video
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Video
CLK
CLK
RXD
TXD
Video
Video
Video
Video
CLK
CLK
Video
Video
Video
Video
Video
Video
Video
Video
Video
Video
Video
Video
Video
Video
Disp_En
WAVEFORMS:
Waveforms taken using
1080P SMTP Color Bar
input. All readings give
their Time Base related
to scope settings.
Winbond Serial
Flash
3.3V
3.3V
n/c
n/c
n/c
n/c
0.08V
3.3V
0V
Gnd
n/c
n/c
n/c
n/c
0.08V
0.08V
IC308
+1.3V_VDDC
Pin Regulator
[1] 0.8V*
[2] 0V
[3] 5V
[4] 6.1V
[5] 5V
[6] 1.3V
[7] 1.3V
[8] 4.5V
*Caused Video to Mute
Q402
Tuner CVBS
Buffer (Analog)
1.1V
1.7V
Gnd
D1
Pin
[B]
[E]
[C]
Tuner SIF
Buffer (Digital)
1.2V
1.8V
Gnd
D2
Pin
[B]
[E]
[C]
Q404
Q502
Pin
[1 B]
[2 S]
[3 D]
[4 G]
HDMI CEC
Buffer
Gnd
3.18V
3.29V
3.3V
Reset
Speed Up
Gnd
0V
Gnd
D504
Pin
[A1]
[A]
[A2]
LED-R
Routing
0V
0.13V
0.28V
D505
Pin
[A1]
[C]
[A2]
Pin
[A1]
[A]
[A2]
B+ Routing
to IC502
5.1V
4.55V
0V
D501
Pin
[A1]
[A]
[A2]
B+ Routing
to IC503
5.1V
4.55V
0V
Pin
[A1]
[A]
[A2]
B+ Routing
to IC504
0V
4.54V
5.0V
NVRAM
IC303
Pin
[1]
[2]
[3]
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Gnd
Gnd
G d
Gnd
Gnd
3.3V
3.3V
Gnd
3.3V
IC305
Pin
[1]
[2]
[3]
1.8V_MST
Regulator
0.6V
1.8V (Out)
3.3V (In)
3.3V_VST
Regulator
Gnd
3.3V (Out)
5.09V (In)
IC307
Pin
[1]
[2]
[3]
IC304
3.3V_MST
Regulator
Gnd
3.3V (Out)
5.04V (In)
IC501
1.2V_DVDD Reg
Pin
Dig Ch Only
[1] Gnd
[2] 1.2V (Out)
[3] 3.3V (In)
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
HDCP Data
EEPROM
Gnd
Gnd
3.3V
G d
Gnd
3.3V
3.3V
3.3V
3.3V
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
IC503, IC504
EDID Data
For HDMI
Gnd
Gnd
Gnd
Gnd
3.3V
3.3V
3.3V
3.3V
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
RGB
Earphone Amp
Gnd
Gnd
Gnd
Gnd
5.09V
5.09V
0V
5.09V
IC502
IC301
IC302
Pin
[1]
[2]
[3]
3.3V_TU
Regulator
2.1V
3.3V (Out)
5.1V (In)
Pin
[1]
[2]
[3]
1.8V_TU
Regulator
Gnd
1.8V (Out)
3.3V (In)
IC602
IC703
3.3V
5.6V
0V
0V
(-5.5V)
(-5.5V)
(-5.5V)
0V
3.3V
3.3V
n/c
n/c
0V
5.6V
Gnd
3.3V (B+)
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
USB 5V
Limiter
Gnd
5.1V (In)
5.1V (In)
3.3V
0V
5.1V (Out)
5.1V (Out)
n/c
IC704
Q302
Pin
[G]
[S]
[D]
5V_MST
Switch
0V
5.09V
5V
Q303
3.3V_PVSB
Pin
Dig Ch Only
[G] 0V
Only on
[S] 3.3V with Dig
[D] 3.3V Channel
Q304
urns on 3.3V_PVSB
Pin
Switch Q303
[B] 0.64V Onlyy on
with Dig
[C] 0V
[E] Gnd Channel
Q501, Q503
Q504
Pin
[B]
[C]
[E]
Hot Swap
Switch for HDMI
0V
0V
Gnd
Q702
Pin
[B]
[C]
[E]
D502
RS232
Tx Buffer
0.6V
0V
Gnd
160
Plasma