All About Op Amplifier-Collection

LM101,LM103
AN-32 FET Circuit Applications
Literature Number: SNOA620
FET Circuit Applications
National Semiconductor
Application Note 32
February 1970
*Polycarbonate dielectric
TL/H/6791 1
Sample and Hold With Offset Adjustment

The 2N4339 JFET was selected because of its low lGSS
(k100 pA), very-low lD(OFF) (k50 pA) and low pinchoff volt-
age. Leakages of this level put the burden of circuit performance on clean, solder-resin free, low leakage circuit layout.
TL/H/6791 3
TL/H/6791 2
Long Time Comparator
JFET AC Coupled Integrator
The 2N4393 is operated as a Miller integrator. The high Yfs

of the 2N4393 (over 12,000 mmhos @ 5 mA) yields a stage
gain of about 60. Since the equivalent capacitance looking
into the gate is C times gain and the gate source resistance
can be as high as 10 MX, time constants as long as a
minute can be achieved.
This circuit utilizes the m-amp technique to achieve very

high voltage gain. Using C1 in the circuit as a Miller integrator, or capacitance multiplier, allows this simple circuit to
handle very long time constants.
AN-32
C1995 National Semiconductor Corporation
TL/H/6791
RRD-B30M115/Printed in U. S. A.
TL/H/6791 4
Ultra-High ZIN AC Unity Gain Amplifier

resistor and drain. Any input capacitance you get with this
circuit is due to poor layout techniques.
Nothing is left to chance in reducing input capacitance. The

2N4416, which has low capacitance in the first place, is
operated as a source follower with bootstrapped gate bias
TL/H/6791 6
TL/H/67915
FET Cascode Video Amplifier
JFET Pierce Crystal Oscillator
The FET cascode video amplifier features very low input

loading and reduction of feedback to almost zero. The
2N3823 is used because of its low capacitance and high
Yfs. Bandwidth of this amplifier is limited by RL and load
capacitance.
The JFET Pierce crystal oscillator allows a wide frequency

range of crystals to be used without circuit modification.
Since the JFET gate does not load the crystal, good Q is
maintained thus insuring good frequency stability.
TL/H/6791 7
FETVM-FET Voltmeter
allowing a 0.5 volt full scale range which is impractical with
most vacuum tubes. The low-leakage, low-noise 2N4340 is
an ideal device for this application.
This FETVM replaces the function ot the VTVM while at the

same time ridding the instrument of the usual line cord. In
addition, drift rates are far superior to vacuum tube circuits
TL/H/6791 8
HI-FI Tone Control Circuit (High Z Input)

The 2N3684 JFET provides the function of a high input
impedance and low noise characteristics to buffer an op
amp-operated feedback type tone control circuit.
Rs-SCALING RESISTORS
TL/H/6791 10
Differential Analog Switch

The FM1208 monolithic dual is used in a differential multiplexer application where RDS(ON) should be closely
matched. Since RDS(ON) for the monolithic dual tracks
at better than g 1% over wide temperature ranges
(b25 to a 125 C), this makes it an unusual but ideal choice

for an accurate multiplexer. This close tracking greatly reduces errors due to common mode signals.
TL/H/6791 11
Magnetic-Pickup Phono Preamplifier

ratio of better than b70 dB (referenced to 10 mV input at
1 kHz) and has a dynamic range of 84 dB (referenced to
1 kHz). The feedback provides for RIAA equalization.
This preamplifier provides proper loading to a reluctance

phono cartridge. It provides approximately 25 dB of gain at
1 kHz (2.2 mV input for 100 mV output), it features S a N/N
TL/H/6791 12
TL/H/6791 13
Negative to Positive Supply Logic Level Shifter

This simple circuit provides for level shifting from any logic
function (such as MOS) operating from minus to ground
supply to any logic level (such as TTL) operating from a plus
to ground supply. The 2N3970 provides a low rds(ON) and
fast switching times.
Variable Attenuator
The 2N3685 acts as a voltage variable resistor with an
RDS(ON) of 800X max. The 2N3685 JFET will have linear
resistance over several decades of resistance providing an
excellent electronic gain control.
TL/H/6791 14
Voltage Controlled Variable Gain Amplifier

tion of greater than 100 dB can be obtained at 10 MHz
providing proper RF construction techniques are employed.
The 2N4391 provides a low RDS(ON) (less than 30X). The

tee attenuator provides for optimum dynamic linear range
for attenuation and if complete turnoff is desired, attenua-
AV e
me
m
e 500 TYPICAL
2
Yfs
Yos
TL/H/6791 15
Ultra-High Gain Audio Amplifier

current is, the more gain you get. You do sacrifice input
dynamic range with increasing gain, however.
Sometimes called the JFET m amp, this circuit provides

a very low power, high gain amplifying function. Since m of a
JFET increases as drain current decreases, the lower drain
TL/H/6791 16
Level-Shifting-Isolation Amplifier
The 2N4341 JFET is used as a level shifter between two op
amps operated at different power supply voltages. The
JFET is ideally suited for this type of application because

lD e lS.
VIN
IO e
R1
VIN l 0V
TL/H/6791 18
*Trademark of the
Burroughs Corp.
TL/H/679117
FET Nixie* Drivers
Precision Current Sink
The 2N3684 JFETs are used as Nixie tube drivers. Their Vp

of 2-5 volts ideally matches DTL-TTL logic levels. Diodes
are used to a a 50 volt prebias line to prevent breakdown of
the JFETs. Since the 2N3684 is in a TO-72 (4 lead TO-18)
package, none of the circuit voltages appear on the can.
The JFET is immune to almost all of the failure mechanisms
found in bipolar transistors used for this application.
The 2N3069 JFET and 2N2219 bipolar have inherently high

output impedance. Using R1 as a current sensing resistor to
provide feedback to the LM101 op amp provides a large
amount of loop gain for negative feedback to enhance the
true current sink nature of this circuit. For small current values, the 10k resistor and 2N2219 may be eliminated if the
source of the JFET is connected to R1.
TL/H/6791 19
JFET-Bipolar Cascode Circuit

video detector. An m derived filter using stray capacitance
and a variable inductor prevents 4.5 MHz sound frequency
from being amplified by the video amplifier.
The JFET-Bipolar cascode circuit will provide full video output for the CRT cathode drive. Gain is about 90. The cascode configuration eliminates Miller capacitance problems
with the 2N4091 JFET, thus allowing direct drive from the
*Polycarbonate dielectric capacitor
TL/H/6791 20
Low Drift Sample and Hold

The JFETs, Q1 and Q2, provide complete buffering to C1,
the sample and hold capacitor. During sample, Q1 is turned
on and provides a path, rds(ON), for charging C1. During
hold, Q1 is turned off thus leaving Q1 ID(OFF) (k50 pA)
and Q2 IGSS (k100 pA) as the only discharge paths. Q2

serves a buffering function so feedback to the LM101 and
output current are supplied from its source.
TL/H/679121
TL/H/6791 22
Wein Bridge Sine Wave Oscillator
JFET Sample and Hold Circuit

The logic voltage is applied simultaneously to the sample
and hold JFETs. By matching input impedance and feedback resistance and capacitance, errors due to rds(ON) of
the JFETs is minimized. The inherent matched rds(ON) and
matched leakage currents of the FM1109 monolithic dual
greatly improve circuit performance.
The major problem in producing a low distortion, constant

amplitude sine wave is getting the amplifier loop gain just
right. By using the 2N3069 JFET as a voltage variable resistor in the amplifier feedback loop, this can be easily
achieved. The LM103 zener diode provides the voltage reference for the peak sine wave amplitude; this is rectified
and fed to the gate of the 2N3069, thus varying its channel
resistance and, hence, loop gain.
VOUT t
R2
VIN
R1
TL/H/6791 24
TL/H/679123
High Impedance Low Capacitance Wideband Buffer
High Impedance Low Capacitance Amplifier
The 2N4416 features low input capacitance which makes

this compound-series feedback buffer a wide-band unity
gain amplifier.
This compound series-feedback circuit provides high input

impedance and stable, wide-band gain for general purpose
video amplifier applications.
TL/H/6791 25
Stable Low Frequency Crystal Oscillator

TL/H/6791 26
This Colpitts-Crystal oscillator is ideal for low frequency

crystal oscillator circuits. Excellent stability is assured because the 2N3823 JFET circuit loading does not vary with
temperature.
0 to 360 Phase Shifter

Each stage provides 0 to 180 phase shift. By ganging the
two stages, 0 to 360 phase shift is achieved. The 2N3070
JFETs are ideal since they do not load the phase shift networks.
TL/H/6791 27
DTL-TTL Controlled Buffered Analog Switch

chopper. The DM7800 monolithic I.C. provides adequate
switch drive controlled DTL-TTL logic levels.
This analog switch uses the 2N4860 JFET for its 25 ohm
rON and low leakage. The LM102 serves as a voltage buffer.
This circuit can be adapted to a dual trace oscilloscope
C1
20 MHz OSCILLATOR VALUES

j 700 pF
L1 e 1.3 mH
C2 e 75 pF
L2 e 10T */8 DIA */4 LONG
VDD e 16V
ID e 1 mA
20 MHz OSCILLATOR PERFORMANCE

LOW DISTORTION 20 MHz OSC.
2ND HARMONIC b 60 dB
3RD HARMONIC l b 70 dB
TL/H/6791 28
Low Distortion Oscillator

The 2N4416 JFET is capable of oscillating in a circuit where
harmonic distortion is very low. The JFET local oscillator
is excellent when a low harmonic content is required for a

good mixer circuit.
TL/H/6791 29
200 MHz Cascode Amplifier

only special requirement of this circuit is that lDSS of the
upper unit must be greater than that of the lower unit.
This 200 MHz JFET cascode circuit features low crossmodulation, large-signal handling ability, no neutralization, and
AGC controlled by biasing the upper cascode JFET. The
TL/H/6791 30
FET Op Amp
its bias current range thus improving common mode rejection.
The FM3954 monolithic-dual provides an ideal low-offset,

low-drift buffer function for the LM101A op amp. The excellent matching characteristics of the FM3954 track well over
TL/H/6791 31
High Toggle Rate High Frequency Analog Switch

ac impedance for off drive and high ac impedance for on
drive to the 2N3970. The LH0005 op amp does the job of
amplifying megahertz signals.
This commutator circuit provides low impedance gate drive

to the 2N3970 analog switch for both on and off drive conditions. This circuit also approaches the ideal gate drive conditions for high frequency signal handling by providing a low
10
TL/H/6791 32
4-Channel Commutator
which provides from a 10V to b20V gate drive to the
JFETs while at the same time providing DTL-TTL logic compatability.
This 4-channel commutator uses the 2N4091 to achieve low

channel ON resistance (k30X) and low OFF current leakage. The DM7800 voltage translator is a monolithic device
TL/H/6791 34
Current Monitor
R1 senses current flow of a power supply. The JFET is used
as a buffer because lD e lS, therefore the output monitor
voltage accurately reflects the power supply current flow.
11
TL/H/6791 35
Low Cost High Level Preamp and Tone Control Circuit

ratio of over 85 dB. The tone controls allow 18 dB of cut and
boost; the amplifier has a 1 volt output for 100 mV input at
maximum level.
This preamp and tone control uses the JFET to its best
advantage; as a low noise high input impedance device. All
device parameters are non-critical yet the circuit achieves
harmonic distortion levels of less than 0.05% with a S/N
VIN
lO e
Rl
VIN s 0V
TL/H/6791 36
Precision Current Source

TL/H/6791 37
The 2N3069 JFET and 2N2219 bipolar serve as voltage

devices between the output and the current sensing resistor, R1. The LM101 provides a large amount of loop gain to
assure that the circuit acts as a current source. For small
values of current, the 2N2219 and 10k resistor may be eliminated with the output appearing at the source of the
2N3069.
Schmitt Trigger
This Schmitt trigger circuit is emitter coupled and provides
a simple comparator action. The 2N3069 JFET places very
little loading on the measured input. The 2N3565 bipolar is a
high hFE transistor so the circuit has fast transition action
and a distinct hysteresis loop.
12
TL/H/6791 38
Low Power Regulator Reference

This simple reference circuit provides a stable voltage reference almost totally free of supply voltage hash. Typical
power supply rejection exceeds 100 dB.
TL/H/6791 39
High Frequency Switch

The 2N4391 provides a low on-resistance of 30 ohms and a
high off-impedance (k0.2 pF) when off. With proper layout
and an ideal switch, the performance stated above can

be readily achieved.
13

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If All Else Fails, Read This Article
74
Avoid Common Problems When

Designing Amplifier Circuits
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Introduction
Modern operational amplifiers (op amps) and instrumentation

amplifiers (in-amps) provide great benefits to the designer,
compared with assemblies of discrete semiconductors. A great
many clever, useful, and tempting circuit applications have been
published. But all too often, in ones haste to assemble a circuit,
some very basic issue is overlooked that leads to the circuit not
functioning as expectedor perhaps at all.
This article will discuss a few of the most common application
problems and suggest practical solutions.
Missing DC Bias Current Return Path When AC-Coupled
One of the most common application problems encountered is the

failure to provide a dc return path for bias current in ac-coupled
operational- or instrumentation-amplifier circuits. In Figure 1, a
capacitor is connected in series with the noninverting (+) input of
an op amp to ac couple it, an easy way to block dc voltages that are
associated with the input voltage (V IN ). This should be especially
useful in high-gain applications, where even a small dc voltage
at an amplifiers input can limit the dynamic range, or even
result in output saturation. However, capacitively coupling into
a high-impedance input, without providing a dc path for current
flowing in the + input, will lead to trouble!
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Figure 2. Correct method for ac coupling an op-amp

input for dual-supply operation.
Figure 2 shows a simple solution to this very common problem.
Here, a resistor is connected between the op-amp input and ground
to provide a path for the input bias current. To minimize offset
voltages caused by input bias currents, which track one another
when using bipolar op amps, R1 is usually set equal to the parallel
combination of R2 and R3.
Note, however, that this resistor will always introduce some noise
into the circuit, so there will be a trade-off between circuit input
impedance, the size of the input coupling capacitor needed, and
the Johnson noise added by the resistor. Typical resistor values are
generally in the range from about 100,000 to 1 M.
A similar problem can affect an instrumentation amplifier
circuit. Figure 3 shows in-amp circuits that are ac-coupled using
two capacitors, without providing an input-bias-current return
path. This problem is common with instrumentation amplifier
circuits using both dual- (Figure 3a) and single (Figure 3b)
power supplies.
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Figure 1. A malfunctional ac-coupled op-amp circuit.

What actually happens is that the input bias currents will flow
through the coupling capacitor, charging it, until the common-mode
voltage rating of the amplifiers input circuit is exceeded or the output
is driven into limits. Depending on the polarity of the input bias
current, the capacitor will charge up toward the positive supply
voltage or down toward the negative supply. The bias voltage is
amplified by the closed-loop dc gain of the amplifier.
This process can take a long time. For example, an amplifier with
a field-effect-transistor (FET) input, having a 1-pA bias current,
coupled via a 0.1-F capacitor, will have a charging rate, I/C, of
10 12/10 7 = 10 V/s, or 600 V per minute. If the gain is 100,
the output will drift at 0.06 V per minute. Thus, a casual lab test
(using an ac-coupled scope) might not detect this problem, and the
circuit will not fail until hours later. Obviously, it is very important
to avoid this problem altogether.
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Figure 3. Examples of nonfunctional ac-coupled

in-amp circuits.
The problem can also occur with transformer coupling, as
in Figure 4, if no dc return path to ground is provided in the
transformers secondary circuit.
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Figure 4. A nonfunctional transformer-coupled in-amp circuit.
http://www.analog.com/analogdialogue
Analog Dialogue 41-08, August (2007)
74
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Figure 5. A high-value resistor between each input and common supplies the necessary bias-current return path.
a. Dual supply. b. Single supply.
Simple solutions for these circuits are shown in Figure 5 and

Figure 6. Here, a high-value resistance (R A, R B) is added between
each input and ground. This is a simple and practical solution for
dual-supply in-amp circuits.
The resistors provide a discharge path for input bias currents.
In the dual-supply example of Figure 5a, both inputs are now
referenced to ground. In the single-supply example of 5b, the
inputs may be referenced either to ground (VCM tied to ground)
or to a bias voltage, usually one-half the maximum input
voltage range.
The same principle can be used for transformer-coupled inputs
(Figure 6), unless the transformer secondary has a center tap,
which can be grounded or connected to VCM.
In these circuits, there will be a small offset-voltage error due to
mismatches between the resistors and/or the input bias currents.
To minimize such errors, a third resistor, about 1/10th their value
(but still large compared to the differential source resistance),
can be connected between the two in-amp inputs (thus bridging
both resistors).
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Figure 7. An in-amp drives an ADC in a typical

single-supply circuit.
Correctly Providing In-Amp Reference Voltage
A common assumption is that the in-amps reference-input

terminal is at high impedance, since its an input. So a designer
may be tempted to connect a high-impedance source, such as
a resistive divider, to the reference pin of an in-amp. This can
introduce serious errors with some types of instrumentation
amplifiers (Figure 8).
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Figure 6. Correct method for transformer input coupling

to an in-amp.
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Supplying Reference Voltages for In-Amps, Op Amps, and ADCs
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Figure 7 shows a single-supply circuit where an in-amp is driving

a single-ended analog-to-digital converter (ADC). The amplifiers
reference provides a bias voltage corresponding to zero differential
input, and the ADC reference provides the scale factor. A simple
RC low-pass antialiasing filter is often used between in-amp output
and ADC input to reduce out-of-band noise. Often designers are
tempted to use simple approaches such as resistance dividers to
supply the in-amp and ADC reference voltages. This can lead to
errors in the case of some in-amps.
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Figure 8. Incorrect use of a simple voltage divider

to directly drive the reference pin of a 3-op-amp
instrumentation amplifier.
For example, a popular in-amp design configuration uses three

op amps connected as above. The overall signal gain is
The gain for the reference input (if driven from low impedance)
is unity. However, in the case shown, the in-amp has its reference
pin tied directly to a simple voltage divider. This unbalances the
symmetry of the subtractor circuit and the division ratio of the
voltage divider. This would reduce the in-amps common-mode
rejection and its gain accuracy. However, if R4 is accessible, so
that its resistance value can be reduced by an amount equal to
the resistance looking back into the paralleled legs of the voltage
divider (50 k here), the circuit will behave as though a lowimpedance voltage source equal to (in this example) one-half the
supply voltage were applied to the original value of R4, and the
subtractors accuracy would be maintained.
This approach cannot be used if the in-amp is provided as a
closed single package (an IC). Another consideration is that the
temperature coefficients of the resistors in the voltage divider
should track those of R4 and the other resistors in the subtractor.
Finally, the approach locks out the possibility of having the
reference be adjustable. If, on the other hand, one attempts to use
small resistor values in the voltage divider in an effort to make the
added resistance negligible, this will increase power supply current
consumption and increase the dissipation of the circuit. In any
case, such brute force is not a good design approach.
Figure 9 shows a better solution, using a low-power op-amp buffer
between the voltage divider and the in-amps reference input. This
eliminates the impedance-matching and temperature-tracking
problem and allows the reference to be easily adjustable.
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This consideration is important when designing circuits with both

in-amps and op amps. Power-supply rejection techniques are
used to isolate an amplifier from power supply hum, noise, and
any transient voltage variations present on the power rails. This is
important because many real-world circuits contain, connect to,
or exist in environments that offer less-than-ideal supply voltage.
Also, ac signals present on the supply lines can be fed back into
the circuit, amplified, and under the right conditions, stimulate
a parasitic oscillation.
Modern op amps and in-amps all provide substantial low-frequency
power-supply rejection as part of their design. This is something
that most engineers take for granted. Many modern op amps and
in-amps have PSR specs of 80 dB to over 100 dB, reducing the
effects of power-supply variations by a factor of 10,000 to 100,000.
Even a fairly modest PSR spec of 40 dB isolates supply variations
from the amplifier by a factor of 100. Nevertheless, high-frequency
bypass capacitors (such as those in Figure 1 through Figure 7) are
always desirable and often essential.
In addition, when designers use a simple resistance divider on the
supply rail and an op-amp buffer to supply a reference voltage
for an in-amp, any variations in power-supply voltage are passed
through this circuitry with little attenuation and add directly to
the in-amps output level. So, unless low-pass filtering is provided,
the normally excellent PSR of the IC is lost.
In Figure 10, a large capacitor has been added to the voltage divider
to filter its output from power-supply variations and preserve PSR.
The 3-dB pole of this filter is set by the parallel combination of
R1/R2 and capacitor C1. The pole should be set approximately
10 times lower than the lowest frequency of concern.
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Figure 9. Driving the reference pin of an in-amp from the

low-imdepance output of an op amp.
Preserving Power-Supply Rejection (PSR) When Amplifiers Are

Referenced from the Supply Rail Using Voltage Dividers
An often overlooked consideration is that any noise, transients,

or drift of power-supply voltage, VS, fed in through the reference
input will add directly to the output, attenuated only by the
divider ratio. Practical solutions include bypassing and filtering,
and perhaps even generating the reference voltage with a precision
reference IC, such as the ADR121, instead of tapping off VS.
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Figure 10. Decoupling the reference circuit to preserve PSR.

The cookbook values shown provide a 3-dB pole frequency
of approximately 0.03 Hz. The small (0.01-F) capacitor across
R3 minimizes resistor noise.
The filter will take time to charge up. Using the cookbook values,
the rise time at the reference input is several time constants (where
T = R 3Cf = 5 s), or about 10 to 15 seconds.
The circuit of Figure 11 offers a further refinement. Here, the

op-amp buffer is operated as an active filter, which allows the use
of much smaller capacitors for the same amount of power-supply
decoupling. In addition, the active filter can be designed to provide
a higher Q and thus give a quicker turn-on time.
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Figure 12 (noninverting) and Figure 13 (inverting) show

circuits to accomplish VS/2 decoupled biasing for best results. In
both cases, bias is provided at the noninverting input, feedback
causes the inverting input to assume the same bias, and unity
dc gain also biases the output to the same voltage. Coupling
capacitor C1 rolls the low-frequency gain down toward unity
from BW3.
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Figure 11. An op-amp buffer connected as an active filter

drives the reference pin of an in-amp.
Test results: With the component values shown, and 12 V applied,
a 6-V filtered reference voltage was provided to the in-amp.
A 1-V p-p sine wave of varying frequency was used to modulate
the 12-V supply, with the in-amp gain set to unity. Under these
conditions, as frequency was decreased, no ac signal was visible
on an oscilloscope, at VREF or at the in-amp output, until
approximately 8 Hz. Measured supply range for this circuit was
4 V to greater than 25 V, with a low-level input signal applied to
the in-amp. Circuit turn-on time was approximately 2 seconds.
Decoupling Single-Supply Op-Amp Circuits
Finally, single-supply op-amp circuits require biasing of the input

common-mode level to handle the positive and negative swings
of ac signals. When this bias is provided from the power-supply
rail, using voltage dividers, adequate decoupling is required to
preserve PSR.
A common and incorrect practice is to use a 100-k/100-k
resistor divider with a 0.1 F bypass capacitor to supply VS /2
to the noninverting pin of the op amp. Using these values,
power- supply decoupling is often inadequate, as the pole
frequency is only 32 Hz. Circuit instability (motor-boating)
often occurs, especially when driving inductive loads.

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Figure 12. A single-supply noninverting amplifier circuit,

showing correct power-supply decoupling. Midband
gain = 1 + R2/R1.
A good rule of thumb when using a 100 k/100 k voltage divider,
as shown, is to use a C2 value of at least 10 F for a 0.3-Hz 3-dB
roll-off. A value of 100 F (0.03-Hz pole) should be sufficient for
practically all circuits.
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Figure 13. Proper decoupling for a single-supply

inverting-amplifier circuit. Midband gain = R2/R1.
Application Report
SLOA064 July 2001
A Differential Op-Amp Circuit Collection

Bruce Carter
High Performance Linear Products

ABSTRACT
All op-amps are differential input devices. Designers are accustomed to working with
these inputs and connecting each to the proper potential. What happens when there are
two outputs? How does a designer connect the second output? How are gain stages
and filters developed? This application note will answer these questions and give a
jumpstart to apprehensive designers.
1 INTRODUCTION
The idea of fully-differential op-amps is not new. The first commercial op-amp, the K2-W,
utilized two dual section tubes (4 active circuit elements) to implement an op-amp with
differential inputs and outputs. It required a 300 Vdc power supply, dissipating 4.5 W of power,
had a corner frequency of 1 Hz, and a gain bandwidth product of 1 MHz(1).
In an era of discrete tube or transistor op-amp modules, any potential advantage to be gained
from fully-differential circuitry was masked by primitive op-amp module performance. Fullydifferential output op-amps were abandoned in favor of single ended op-amps. Fully-differential
op-amps were all but forgotten, even when IC technology was developed. The main reason
appears to be the simplicity of using single ended op-amps. The number of passive components
required to support a fully-differential circuit is approximately double that of a single-ended
circuit. The thinking may have been Why double the number of passive components when
there is nothing to be gained?
Almost 50 years later, IC processing has matured to the point that fully-differential op-amps are
possible that offer significant advantage over their single-ended cousins. The advantages of
differential logic have been exploited for 2 decades. More recently, advanced high-speed A/D
converters have adopted differential inputs. Single-ended op-amps require a problematic
transformer to interface to these differential input A/D converters. This is the application that
spurred the development of fully-differential op-amps. An op-amp with differential outputs,
however, has far more uses than one application.
2 BASIC CIRCUITS
The easiest way to construct fully-differential circuits is to think of the inverting op-amp feedback
topology. In fully-differential op-amp circuits, there are two inverting feedback paths:
Inverting input to noninverting output
Noninverting input to inverting output
Both feedback paths must be closed in order for the fully-differential op-amp to operate properly.
SLOA064
When a gain is specified in the following sections, it is a differential gain that is the gain at
VOUT+ with a return of VOUT-. Another way of thinking of differential outputs is that each signal is
the return path for the other.
2.1
A New Pin
Fully-differential op-amps have an extra input pin (VOCM). The purpose of this pin is to provide a
place to input a potentially noisy signal that will appear simultaneously on both inputs i.e.
common mode noise. The fully-differential op-amp can then reject the common mode noise.
The VOCM pin can be connected to a data converter reference voltage pin to achieve tight tracking
between the op-amp common mode voltage and the data converter common mode voltage. In
this application, the data converter also provides a free dc level conversion for single supply
circuits. The common mode voltage of the data converter is also the dc operating point of the
single-supply circuit. The designer should take care, however, that the dc operating point of the
circuit is within the common mode range of the op-amp + and inputs. This can most easily be
achieved by summing a dc level into the inputs equal or close to the common mode voltage.
2.2
Gain
A gain stage is a basic op-amp circuit. Nothing has really changed from the single-ended
design, except that two feedback pathways have been closed. The differential gain is still Rf /Rin
a familiar concept to analog designers.
Gain = Rf/Rin
Rf
Rin
VinVocm
+Vcc
1
2
8
Vin+
CM
+
-
Vout+
Vout-
Rin
-Vcc
Rf
Figure 1: Differential Gain Stage
This circuit can be converted to a single-ended input by connecting either of the signal inputs to
ground. The gain equation remains unchanged, because the gain is the differential gain.
2.3
Instrumentation
An instrumentation amplifier can be constructed from two single-ended amplifiers and a fullydifferential amplifier as shown in Figure 2. Both polarities of the output signal are available, of
course, and there is no ground dependence.
SLOA064
+Vcc
Vin-
5
5
+
-
+Vcc
5
-Vcc
1
5
2
8
CM
+
-
4
5
Vout+
Vout-
Gain = (R2/R1)*(1+2*R5/R6)
R1=R3
R2=R4
R5=R7
+Vcc
Vocm
5
-Vcc
Vin+
5
5
-Vcc
Figure 2: Instrumentation Amplifier
3 FILTER CIRCUITS
Filtering is done to eliminate unwanted content in audio, among other things. Differential filters
that do the same job to differential signals as their single-ended cousins do to single-ended
signals can be applied.
For differential filter implementations, the components are simply mirror imaged for each
feedback loop. The components in the top feedback loop are designated A, and those in the
bottom feedback loop are designated B.
For clarity decoupling components are not shown in the following schematics. Proper operation
of high-speed op-amps requires proper decoupling techniques. That does not mean a shotgun
approach of using inexpensive 0.1-F capacitors. Decoupling component selection should be
based on the frequencies that need to be rejected, and the characteristics of the capacitors used
at those frequencies.
3.1
Single Pole Filters

Single pole filters are the simplest filters to implement with single-ended op-amps, and the same
holds true with fully-differential amplifiers.
A low pass filter can be formed by placing a capacitor in the feedback loop of a gain stage, in a
manner similar to single-ended op-amps:
SLOA064
fo=1/(2**R2*C1)
gain=-R2/R1
C1A
R2A
+Vcc
3
R1A
Vin-
Vocm
CM
Vin+
R1B
+
-
Vout+
Vout-
+
6
-Vcc
R2B
C1B
Figure 3: Single Pole Differential Low Pass Filter
A high pass filter can be formed by placing a capacitor in series with an inverting gain stage as
shown in Figure 4:
fo=1/(2**R1*C1)
gain=-R2/R1
C1A
R1A
VinVocm
3
1
CM
Vin+
C1B
R2A
+Vcc
+
-
Vout+
Vout-
R1B
6
-Vcc
R2B
125
Figure 4: Single Pole Differential High Pass Filter
3.2
Double Pole Filters

Many double pole filter topologies incorporate positive and negative feedback, and therefore
have no differential implementation. Others employ only negative feedback, but use the
noninverting input for signal input, and also have no differential implementation. This limits the
number of options for designers, because both feedback paths must return to an input.
The good news, however, is that there are topologies available to form differential low pass, high
pass, bandpass, and notch filters. However, the designer might have to use an unfamiliar
topology or more op-amps than would have been required for a single-ended circuit.
SLOA064
3.2.1 Multiple Feedback Filters

MFB filter topology is the simplest topology that will support fully-differential filters.
Unfortunately, the MFB topology is a bit hard to work with, but component ratios are shown for
common unity gain filters.
Reference 5 describes the MFB topology in detail.
C1A
R2A
+Vcc
R1A
Vin-
R3A
1
C2A
Vocm
C2B
R3B
+
-
CM
4
5
Vout+
Vout-
Vin+
R1B
R2B
Bessel
Fo=1/(2RC)
R1=R2=0.625R
R3=0.36R
C1=C
C2=2.67C
-Vcc
C1B
Butterworth
Fo=1/(2RC)
R1=R2=0.65R
R3=0.375R
C1=C
C2=4C
Chebyshev 3 dB
Fo=1/(2RC)
R1=0.644R
R2=0.456R
R3=0.267R
C1=12C
C2=C
Figure 5: Differential Low Pass Filter
SLOA064
C2A
R2A
+Vcc
C1A
Vin-
3
C3A
R1A
Vocm
CM
8
R1B
+
-
Vout+
Vout-
C3B
6
Vin+
C1B
Bessel
Fo=1/(2RC)
R1=0.73R
R2=2.19R
C1=C2=C3=C
-Vcc
R2B
C2B
Butterworth
Fo=1/(2RC)
R1=0.467R
R2=2.11R
C1=C2=C3=C
Chebyshev
Fo=1/(2RC)
R1=3.3R
R2=0.215R
C1=C2=C3=C
Figure 6: Differential High Pass Filter
There is no reason why the feedback paths have to be identical. A bandpass filter can be
formed by using nonsymmetrical feedback pathways (one low pass and one high pass). Figure
7 shows a bandpass filter that passes the range of human speech (300 Hz to 3 kHz).
C1
270 pF
R2
88.7 k
R1
100 k
+VCC
VinR3
41.2 k
C2
1 nF
Vcm
CM
R4
19.1 k
U1
THS4121
3
1
C4
22 nF
+
6
Vin+
C3
10 nF
-VCC
C5
22 nF
R5
86.6 k
Figure 7: Differential Speech Filter
+
-
4
5
Vout+
Vout-
SLOA064
Figure 8: Differential Speech Filter Response
3.2.2 Akerberg Mossberg Filter

Akerberg Mossberg filter topology is a double pole topology that is available in low pass, high
pass, band pass, and notch. The single ended implementation of this filter topology has an
additional op-amp to invert the output of the first op-amp. That inversion in inherent in the fullydifferential op-amp, and therefore is taken directly off the first stage. This reduces the total
number of op-amps required to 2:
R2A
R4A
C1A
+Vcc
U1
3
R1A
VinVocm
CM
Vin+
U2
3
R3A
+
-
Vocm
CM
R1B
C2A
+Vcc
+
-
Vout+
Vout-
R3B
6
-Vcc
-Vcc
C1B
C2B
R4B
R2B
Bessel
Fo=1/(2RC)
R2=R3=0.786R
R4=0.453R
C1=C2=C
Gain: R/R1
Butterworth
Fo=1/(2RC)
R2=R3=R
R4=0.707R
C1=C2=C
Gain: R/R1
Chebyshev
Fo=1/(2RC)
R2=R3=1.19R
R4=1.55R
C1=C2=C
Gain: R/R1
SLOA064
Figure 9: Akerberg Mossberg Low Pass Filter
R1A
VinR3A
C1A
C2A
+Vcc
U1
Vocm
2
8
+
-
CM
U2
3
R2A
C3A
+Vcc
Vocm
+
-
CM
Vout+
Vout-
R2B
6
-Vcc
-Vcc
C2B
C1B
C3B
R3B
Vin+
R1B
Bessel
Fo=1/(2RC)
R1=R2=1.27R
R3=0.735R
C2=C3=C
Gain: C1/C
Butterworth
Fo=1/(2RC)
R1=R2=R
R3=0.707R
C2=C3=C
Gain: C1/C
Chebyshev
Fo=1/(2RC)
R1=R2=0.84R
R3=1.1R
C2=C3=C
Gain: C1/C
Figure 10: Akerberg Mossberg High Pass Filter

Fo=1/(2RC)
R2=R3=R
R4=Q*R
Gain: -R4/R1
C1=C2=C
R2A
R4A
C1A
+Vcc
R3A
+
CM
+
C2A
+Vcc
U1
Vocm
R1A
Vin-
4
Vocm
U2
3
1
2
CM
+
-
R3B
6
-Vcc
-Vcc
C1B
R4B
Vin+
R2B
R1B
Figure 11: Akerberg Mossberg Band Pass Filter
C2B
Vout+
Vout-
SLOA064
Fo=1/(2RC)
R1=R2=R3=R
R4=Q*R
C1=C2=C3=C
Unity gain
R2A
R4A
C2A
C1A
+Vcc
R1A
VinVocm
+
CM
+
R1B
4
2
Vocm
U2
R3A
2
8
Vin+
U1
3
1
C3A
+Vcc
CM
+
-
Vout+
Vout-
R3B
6
-Vcc
6
-Vcc
C1B
C2B
C3B
R4B
R2B
Figure 12: Akerberg Mossberg Notch Filter
3.2.3 Biquad Filter

Biquad filter topology is a double pole topology that is available in low pass, high pass, band
pass, and notch. The highpass and notch versions, however, require additional op-amps, and
therefore this topology is not optimum for them. The single-ended implementation of this filter
topology has an additional op-amp to invert the output of the first op-amp. That inversion is
inherent in the fully-differential op-amp, and therefore is taken directly off the first stage. This
reduces the total number of op-amps required to 2:
SLOA064
R3A
R2A
BPout+
C1A
+Vcc
U1
R1A
VinVocm
+
CM
+
Vin+
R1B
R4A
Vocm
CM
8
R4B
-Vcc
U2
3
1
C2A
+Vcc
+
-
LPout+
LPout-
+
6
-Vcc
C1B
C2B
BPoutR2B
R3B
BANDPASS
LOWPASS
Bessel
Fo=1/(2RC)
R3=0.785R
R2=0.45R
Gain: -R2/R1
C1=C2=C
Fo=1/(2RC)
R3=R
C1=C2=C
Gain= -R2/R1
R2=Q*R
Butterworth
Fo=1/(2RC)
R3=R
R2=0.707R
Gain: -R2/R1
C1=C2=C
Chebyshev
Fo=1/(2RC)
R3=1.19R
R2=1.55R
Gain: -R1/R2
C1=C2=C
Figure 13: Differential BiQuad Filter
4 Driving Differential Input Data Converters

Most high-resolution, high-accuracy data converters utilize differential inputs instead of singleended inputs. There are a number of strategies for driving these converters from single-ended
inputs.
+
Vin
A/D +Input
A/D Common Mode Output

A/D -Input
Figure 14: Traditional Method of Interfacing to Differential-Input A/D Converters
In Figure 14, one amplifier is used in a noninverting configuration to drive a transformer primary.
The secondary of the transformer is center tapped to provide a common-mode connection point
for the A/D converter Vref output.
10
SLOA064
A/D -Input
+
Vin
A/D +Input
Figure 15: Differential Gain Stage With Inverting Single-Ended Amplifiers
Gain can be added to the secondary side of the transformer. In Figure 15, two single-ended op
amps have been configured as inverting gain stages to drive the A/D Inputs. The non-inverting
input inputs are connected to the transformer center tap and A/D Vref output.
Vin-
A/D -Input
+
+
A/D +Input
Figure 16: Differential Gain Stage With Noninverting Single-Ended Amplifiers
Figure 16 shows how single-ended amplifiers can be used as noninverting buffers to drive the
input of an A/D. The advantage of this technique is that the unity gain buffers have exact gains,
so the system will be balanced.
Transformer interfacing methods all have one major disadvantage:
The circuit does not include dc in the frequency response. By definition, the transformer
isolates dc and limits the ac response of the circuit.
If the response of the system must include dc, even for calibration purposes, a transformer is a
serious limitation.
A transformer is not strictly necessary. Two single-ended amplifiers can be used to drive an A/D
converter without a transformer:
11
SLOA064
Vin
+
A/D +Input
A/D -Input
+
Figure 17: Differential Gain Stage With Noninverting Single-Ended Amplifiers
Although all of the methods can be employed, the most preferable method is the use a fullydifferential op-amp:
+Vcc
Vin
CM
+
-
A/D +Input
A/D -Input
+
6
-Vcc
Figure 18: Preferred Method of Interfacing to a Data Converter
A designer should be aware of the characteristics of the reference output from the A/D
converter. It may have limited drive capability, and / or have relatively high output impedance. A
high-output impedance means that the common mode signal is susceptible to noise pickup. In
these cases, it may be wise to filter and/or buffer the A/D reference output:
Optional Buffer
A/D Vref Output
Op Amp Vocm Input
Figure 19: Filter and Buffer for the A/D Reference Output
12
SLOA064
Some A/D converters have two reference outputs instead of one. When this is the case, the
designer must sum these outputs together to create a single signal as shown in Figure 20:
Optional Buffer
Op Amp Vocm Input
A/D Vref+ Output

A/D Vref- Output
Figure 20: Filter and Buffer for the A/D Reference Output
5 Audio Applications
5.1
Bridged Output Stages

The presence of simultaneous output polarities from a fully-differential amplifier solves a problem
inherent in bridged audio circuits the time delay caused by taking a single-ended output and
running it through a second inverting stage.
INPUT
+
Power Amp 1
SPEAKER
+
Power Amp 2
Figure 21: Traditional Bridge Implementation
The time delay is nonzero, and a degree of cancellation as one peak occurs slightly before the
other when the two outputs are combined at the speaker. Worse yet, one output will contain one
amplifiers worth of distortion, while the other has two amplifiers worth of distortion. Assuming
traditional methods of adding random noise, that is a 41.4% noise increase in one output with
respect to the other, power output stages are usually somewhat noisy, so this noise increase will
probably be audible.
A fully-differential op-amp will not have completely symmetrical outputs. There will still be a
finite delay, but the delay is orders of magnitude less than that of the traditional circuit.
13
SLOA064
INPUT
CM
+
-
4
5
SPEAKER
Differential Stage
Figure 22: Improved Bridge Implementation
This technique increases component count and expense. Therefore, it will probably be more
appropriate in high end products. Most fully-differential op-amps are high-speed devices, and
have excellent noise response when used in the audio range.
5.2
Stereo Width Control

Fully-differential amplifiers can be used to create an amplitude cancellation circuit that will
remove audio content that is present in both channels.
14
SLOA064
R2
100 k
+Vcc
C1
4.7 F
Lin
R1
100 k
R8
100 k
3
1
2
CM
R6
100 k
U1
+
-
+Vcc
5
R5A
10 k Pot
R7
100 k
U2
-
C2
4.7 F
+
Lout
+
-Vcc
100 k
R3
100 k
R4
-Vcc
R10
100 k
R15
100 k
R13
100 k
+Vcc
C3
4.7 F
Rin
R9
100 k
3
1
2
CM
R14
100 k
U3
+
-
4
5
C4
4.7 F
+
Rout
R5B
10 k Pot
-Vcc
-Vcc
100 k
R11
U4
-
+
6
+Vcc
100 k
R12
Figure 23: Stereo Width Control
The output mixers (U2 and U4) are presented with an inverted version of the input signal on one
input (through R6 and R14), and a variable amount of out-of-phase signal from the other
channel.
When the ganged pot (R5) is at the center position, equal amounts of inverted and noninverted
signal cancel each other, for a net output of zero on the other input of the output mixers (through
R7 and R13).
At one extreme of the pot (top in this schematic), the output of each channel is the sum of the
left and right channel input audio, or monaural. At the other extreme, the output of each mixer is
devoid of any content from the other channel canceling anything common between them.
This application differs from previous implementations by utilizing fully-differential op-amps to
simultaneously generate inverted and noninverted versions of the input signal. The usual
method of doing this is to generate an inverted version of the input signal from the output of a
buffer amp. The inverted waveform, therefore, is subject to two op-amp delays as opposed to
one delay for the non-inverted waveform. The inverted waveform, therefore, has some phase
delay which limits the ultimate width possible from the circuit. By utilizing a fully-differential opamp, a near perfect inverted waveform is available for cancellation with the other channel.
15
SLOA064
6 Summary
Fully-differential amplifiers are based on the technology of the original tube-based op-amps of
more than 50 years ago. As such, they require design techniques that are new to most
designers. The performance increase afforded by fully differential op-amps more than outweigh
the slight additional expense of more passive components. Driving of fully differential A/D
converters, data filtering for DSL and other digital communication systems, and audio
applications are just a few ways that these devices can be used in a system to deliver
performance that is superior to single-ended design techniques.
References
16
1.
Electrical Engineering Times, Design Classics, Unsung Hero Pioneered Op-Amp,

http://www.eetimes.com/anniversary/designclassics/opamp.html
2.
Fully-differential Amplifiers, Texas Instruments SLOA054A
3.
A Single-supply Op-Amp Circuit Collection, Texas Instruments SLOA058
4.
Stereo Width Controllers, Elliot Sound Products, http://www.sound.au.com/project21.htm
5.
Active Low-Pass Filter Design, Texas Instruments SLOA049A
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Linear Brief 1
March 1969
The differential input single-ended output instrumentation

amplifier is one of the most versatile signal processing amplifiers available. It is used for precision amplification of differential dc or ac signals while rejecting large values of common mode noise. By using integrated circuits, a high level of
performance is obtained at minimum cost.
very low impedance is always presented to the feedback

resistors, and common mode rejection is unaffected by gain
changes. The LM101A, used as shown, has a greater bandwidth than the LM107, and may be used in a feedback network without instability. The gain is linearly dependent on R6
and is equal to 10 b4 R6.
To obtain good common mode rejection ratios, it is necessary that the ratio of R4 to R2 match the ratio of R5 to R3.
For example, if the resistors in circuit shown in Figure 1 had
a total mismatch of 0.1%, the common mode rejection
would be 60 dB times the closed loop gain, or 100 dB. The
circuit shown in Figure 2 would have constant common
mode rejection of 60 dB, independent of gain. In either circuit, it is possible to trim any one of the resistors to obtain
common mode rejection ratios in excess of 100 dB.
For optimum performance, several items should be considered during construction. R1 is used for zeroing the output.
It should be a high resolution, mechanically stable potentiometer to avoid a zero shift from occurring with mechanical
disturbances. Since there are several ICs operating in close
proximity, the power supplies should be bypassed with
0.01 mF disc capacitors to insure stability. The resistors
should be of the same type to have the same temperature
coefficient.
A few applications for a differential instrumentation amplifier
are: differential voltage measurements, bridge outputs,
strain gauge outputs, or low level voltage measurement.
Figure 1 shows a basic instrumentation amplifier which provides a 10 volt output for 100 mW input, while rejecting
greater than g 11V of common mode noise. To obtain good
input characteristics, two voltage followers buffer the input
signal. The LM102 is specifically designed for voltage follower usage and has 10,000 MX input impedance with 3 nA
input currents. This high of an input impedance provides two
benefits: it allows the instrumentation amplifier to be used
with high source resistances and still have low error; and it
allows the source resistances to be unbalanced by over
10,000X with no degradation in common mode rejection.
The followers drive a balanced differential amplifier, as
shown in Figure 1 , which provides gain and rejects the common mode voltage. The gain is set by the ratio of R4 to R2
and R5 to R3. With the values shown, the gain for differential signals is 100.
Figure 2 shows an instrumentation amplifier where the gain
is linearly adjustable from 1 to 300 with a single resistor. An
LM101A, connected as a fast inverter, is used as an attenuator in the feedback loop. By using an active attenuator, a
Instrumentation Amplifier
TL/H/8501 1
FIGURE 1. Differential-Input Instrumentation Amplifier
LB-1
C1995 National Semiconductor Corporation
TL/H/8501
RRD-B30M115/Printed in U. S. A.
*GAIN ADJUST
Av e 10b4 R6
TL/H/8501 2
FIGURE 2. Variable Gain, Differential-Input Instrumentation Amplifier
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Instrumentation Amplifier Application Note
Application Note
May 27, 2009
AN1298.2
Table of Contents
Introduction to the Instrumentation Amplifier................................................................................................................................... 2
Review of Standard Instrumentation Amplifier Design Techniques ................................................................................................ 2
Monolithic Instrumentation Amplifier Architecture ........................................................................................................................... 4
Introduction to Instrumentation Amplifier Product Family................................................................................................................ 4
Instrumentation Amplifier Specifications ......................................................................................................................................... 4
Instrumentation Amplifier Product Family Theory of Operation....................................................................................................... 6
Features of Instrumentation Amplifier Product Family .................................................................................................................... 7
Care and Feeding of Instrumentation Amplifiers ............................................................................................................................. 10
Application Circuits.......................................................................................................................................................................... 20
Pressure Sensor Interface Circuit ................................................................................................................................................... 21
Thermocouple Input with A/D Converter Output ............................................................................................................................. 22
Thermocouple Input with 4mA to 20mA Output Current ................................................................................................................. 23
RTD Input with A/D Converter Output ............................................................................................................................................. 24
Low Voltage High Side Current Sense............................................................................................................................................ 27
Multiplexed Low Voltage Current Sense ......................................................................................................................................... 30
Bi-Directional Current Sense........................................................................................................................................................... 32
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Application Note 1298

Introduction to the Instrumentation
Amplifier
An Instrumentation Amplifier is a confused animal

confused by its cousin, the op amp.
This Application Note describes the Intersil bipolar and MOS

input (see Table 1). Instrumentation Amplifiers, theory of
operation, advantages, and typical application circuits.
These devices are micropower Instrumentation Amplifiers
which deliver rail-to-rail input amplification and rail-to-rail
output swing on a single 2.4V to 5V supply. These
Instrumentation Amplifiers deliver excellent DC and AC
specifications while consuming only 60A typical supply
current. Because they provide an independent pair of
feedback terminals to set the gain and to adjust output level,
these Instrumentation Amplifiers achieve high
common-mode rejection ratios regardless of the tolerance of
the gain setting resistors. The ISL28271 and ISL28272 have
an ENABLE pin to reduce power consumption, typically less
than 5.0A, while the Instrumentation Amplifier is disabled.
Its symbol looks like an op amp (see Figure 1)

It has many of the same basic properties and
specifications as an op amp Offset Voltage, Input Bias
Current, CMRR, PSRR, etc.
You can make an Instrumentation Amplifier from a simple
op amp circuit.
But the behavior of an Instrumentation Amplifier is
profoundly different than an op amp! And it is very difficult to
make a precision Instrumentation Amplifier from a simple op
amp circuit many have tried, but most have failed.
An Instrumentation Amplifier provides a voltage subtraction
block followed by a fixed gain block; i.e.
V OUT = ( IN+ IN- ) Gain
TABLE 1.
Often, there is an optional output reference input which

allows the output voltage to be shifted by a fixed voltage:
MINIMUM
CLOSED
BW
INPUT
# OF
STAGE AMPLIFIERS LOOP GAIN (kHz) ENABLE?
PART
EL8170
Bipolar
100
192
No
EL8171
PMOS
10
450
No
EL8172
PMOS
100
170
No
EL8173
Bipolar
10
396
No
ISL28270 Bipolar
100
240
No
ISL28271 PMOS
10
180
Yes
ISL28272 PMOS
100
100
Yes
ISL28273 Bipolar
10
230
No
ISL28470 Bipolar
100
240
No
VOUT
VOUT
GAIN
In contrast, an op amp by definition only provides extremely

high gain with provisions to apply negative feedback to
establish a fixed gain or unique transfer function, H(s), such
as an integrator or filter.
Review of Standard Instrumentation

Amplifier Design Techniques
Difference Amplifier
In its most basic topology, an Instrumentation Amplifier can
be configured from a single op amp and four resistors as
shown in Figure 4; this is often referred to as a Difference
Amplifier.
-VCC
-VCC
IN-
FIGURE 3.
VOUT
IN+
(EQ. 2)
VREF
+
-
V OUT = ( IN+ IN- ) Gain + V REF
+VCC
+VCC
(EQ. 1)
INSTRUMENTATION AMPLIFIER
OP AMP
FIGURE 1.
R2
R1
IN-
R2
R1
+
VOUT = (IN+ - IN-) * (1 + R2/R1)
IN+
FIGURE 2. TWO OP AMP INSTRUMENTATION AMPLIFIER
AN1298.2
May 27, 2009

and a common voltage of 10V, the inputs to the op amp will
be sitting at a voltage of 9.9V. This circuit would not be
possible if the op amp was operated with VCC of +5V since
the op amp inputs voltage would exceed the supply voltage.
R2
R1
IN-
IN+
VOUT
R2
100k
R3
R4
Vcm = 10V
VREF
VCC
R1
1k
-
VOUT
R3
1k
FIGURE 4.
R4
100k
In this configuration, the gain is set by resistors R1 and R2:

Gain = R 2 R 1
(EQ. 3)
VREF
FIGURE 5.
(EQ. 4)
For the ability to reject a voltage that appears on both INand IN+ (i.e., common mode voltage), resistor values must
match such that R1 = R3 and R2 = R4. The common mode
rejection ratio (CMRR) is set by the matching ratio of R1:R3
and R2:R4. High common mode rejection ratio requires a
very high degree of ratio matching.
Two Amplifier Instrumentation Amplifier

To provide a high input impedance, a two amplifier
Instrumentation Amplifier can be used as in Figure 6.
R2
It can be shown that the CMRR is:
CMRR = 20 log 10 (x)
(EQ. 5)
IN-
Where x = R 4 ( R 3 + R 4 ) ( R 1 + R 2 ) R 1 R 2 R 1
(EQ. 6)
IN+
Worse case CMRR occurs when the tolerance of R4 and R1

are at their maximum, and R2 and R3 are at their minimum
value. The following table shows the relationship between
resistor tolerance and CMRR for gains of 1, 10, and 100.
TABLE 2.
RESISTOR
R1
CMRR
TOLERANCE
GAIN =1
GAIN = 10
GAIN =100
5%
-20.4dB
-15.6dB
-14.8dB
1%
-34.1dB
-28.9dB
-28.1dB
0.1%
-54.0dB
-48.8dB
-48.0dB
0.01%
-74.0dB
-68.8dB
-68.0dB
The Difference Amplifier has the advantage of simplicity and

the ability to operate with high common mode voltage on its
inputs, IN+ and IN-. However, the input resistance is set by
the resistor values R3 and R4, and does not provide high
input resistance as is common in most Instrumentation
Amplifier circuits.
R4
R3
-
VOUT
FIGURE 6. TWO AMPLIFIER INSTRUMENTATION AMPLIFIER
In this configuration, the gain is set by resistors R3 and R4:

Gain = 1 + R 4 R 3
(EQ. 7)
V OUT = ( IN+ IN- ) Gain
(EQ. 8)
The ability to reject a voltage that appears on both IN- and

IN+ (i.e., common mode voltage), depends on matched
resistor values such that, R1 = R3 and R2 = R4. The common
mode rejection ratio (CMRR) is set by the matching ratio of
R1:R3 and R2:R4, and, high CMRR requires a very high
degree of ratio matching. For example, with 10V of common
mode voltage, resistor tolerances must be at least 0.01%
to achieve 12-bit accuracy (72dB).
Classic Three Amplifier Instrumentation Amplifier

By adding a third op amp, the Classic Three Amplifier
Instrumentation Amplifier can be configured as shown in
Figure 7.
Additionally, the REF input must be driven by a very low

source impedance since the CMRR will be degraded by any
source resistance that contributes to the value of R4 and
causes increased mismatch between R2 and R4.
Also note that the common mode voltage will bias internal
nodes at a voltage that is set by the ratio of R3 and R4, or the
gain of the circuit. For example, in Figure 5, for a gain of 100
AN1298.2
May 27, 2009

IN-
R1
Introduction to Instrumentation Amplifier

Product Family
R2
V2
R5
-
Rg
VOUT
VIN
V1
R6
IN+
INVOUT
VOUT
V4
R3
IN+
R4
VREF
FIGURE 7. CLASSIC THREE AMPLIFIER INSTRUMENTATION

AMPLIFIER
V3
FB+
FB-
Rf
Rg
Usually, resistors R1 through R6 are equal value resistors of

R and the gain:
Gain = ( 1 + 2 R R gain )
(EQ. 9)
(EQ. 10)
This Application Note describes the Intersil Instrumentation

Amplifier Product Family, which includes the following
features:
With this circuit, the Gain can be set with a single resistor,
RGAIN and the input impedance is very high. However, the
common mode rejection ratio, CMRR, just like the Difference
Amplifier topology, is still set by the resistor matching
between R1, R2, R3, and R4. Extremely low tolerance
resistors or precision resistor trimming is required to achieve
high CMRR. The equations and Table shown for the
Difference Amplifier apply directly to the Classic Three
Amplifier Instrumentation Amplifier configuration.
Monolithic Instrumentation Amplifier

Architecture
Each of the three basic Instrumentation Amplifier architectures
that have been already discussed have been implemented in
standard integrated circuit packages. To achieve a high CMRR,
extensive resistor trimming is required with lasers or other
suitable techniques. While each of these devices provide
adequate specifications for a precision Instrumentation
Amplifier, each device has its own compromise based on
operating voltage range, supply current, common mode
operating range, input impedance, etc. These instrumentation
amplifiers use one external resistor to set the gain; while this
may seem to be an advantage, there are considerations which
make the single resistor configuration undesirable from a
design viewpoint. The temperature coefficient (TC) of the
external resistor will be a direct gain drift. Also, an external filter
can not be applied to the feedback network because it is
internal to the device.
1. Bipolar transistor inputs for low voltage noise

2. PMOS transistor inputs for low input bias current
3. Micropower operation requiring only 60A supply current
4. Rail-to-rail inputs and rail-to-rail output swing
5. Single supply operation from 2.4V to 5V supply
6. An independent pair of feedback terminals to set the gain
and to adjust output level allow these Instrumentation
Amplifier to achieve high CMRR (>104dB) regardless of
the tolerance of the gain setting resistors.
7. Internal loop compensation to provide optimum
bandwidth trade-off as shown in Table 1
8. The ISL28271 and ISL28272 have an ENABLE pin to
reduce the supply current to a typical of less than 5A and
tri-state the output stage to a high impedance state.
Instrumentation Amplifier Specifications

Many of the Instrumentation Amplifier specifications are very
similar to the standard specifications for operational
amplifiers. However, the unique architecture of the Intersil
Instrumentation Amplifiers make some of these
specifications differ slightly. Table 3 summarizes the
Specifications and Features of the Instrumentation Amplifier
Product Family.
AN1298.2
May 27, 2009

TABLE 3.
PARAMETERS
EL8170
Input Stage
Minimum Gain
Gain Set
Supply Current: Enabled
per Channel
Supply Current: Shutdown
ISL28270 ISL28470
EL8173
ISL28273
EL8171
ISL28271
EL8172
ISL28272
UNITS
Bipolar
Bipolar
PMOS
PMOS
100
10
10
100
2 Ext R
2 Ext R
2 Ext R
2 Ext R
65
65
65
60
65
60
Minimum VCC
2.4
2.4
2.4
2.4
VDC
Maximum VCC
5.5
5.5
5.5
5.5
VDC
Input Offset Voltage
200
150
150
1000
600
1500
600
300
500
Offset Drift
0.24
0.7
0.7
2.5
0.7
1.5
0.7
0.14
0.7
V/C
Input Bias Current, Maximum
3000
2000
2500
2000
2500
50
30
50
30
pA
25
30
25
30
pA
Input Offset Current, Maximum
2000
2000
Input Bias Current Cancellation
Yes
Yes
Bandwidth (-3dB) at AV = 10
396
Bandwidth (-3dB) at AV = 100
192
240
240
Slew Rate (Typ)
0.55
0.5
0.5
265
450
0.55
180
0.6
0.55
0.5
170
100
kHz
0.55
0.5
V/s
Rail-to-Rail Input
Yes
Yes
Yes
Yes
Rail-to-Rail Output
Yes
Yes
Yes
Yes
26
26
Output Current Limit, V+ = 5V
26
Output in Shutdown Mode

Gain Accuracy
29
29
26
29
-
kHz
mA
HiZ
HiZ
0.15
0.08
0.2
-0.19
0.35
0.5
0.5
0.1
0.12
CMRR (Typ)
114
110
110
106
110
PSRR (Typ)
106
110
110
90
95
90
100
eN at 1kHz
58
60
60
220
210
220
240
80
78
nv/Hz
3.6
3.5
14
10
10
VP-P
100
100
dB
100
dB
eN 0.1Hz to 10Hz
3.5
Input Protection - Diodes to

Rails
Yes
Yes
Yes
Yes
Input Protection - Diodes

across Inputs
Yes
No
No
No
Max Input Diode Current
SO8
SO8
SO8
SO8
-40 to +85
-40 to +85
-40 to +85
-40 to +85
Yes
Yes
Yes
Yes
Package
Operating Temp. Range
RoHS Compliant
mA
AN1298.2
May 27, 2009

+Ven
Re
Va
V1
IN-
Re
Vb
Ix1
Q1
Ix2
Q2
IN+
V2
V3
I2
I1
Q3
FB+
I3
Q4
V4
FB-
I4
V5
V6
VOUT
I5
I6
Ry
GAIN = A
Ry
FIGURE 9. SIMPLIFIED SCHEMATIC
Instrumentation Amplifier Product Family

Theory of Operation
Each of the features specifications of the Intersil
Instrumentation Amplifier Product Family will be discussed in
more detail in a future section of this Application Note, but
first, lets study the internal operation of this unique
Instrumentation Amplifier Product Family.
V5 = I5 Ry = 2 Ry I + ( V1 V2 ) Ry Re + ( V4 V3 ) Ry Re
(EQ. 20)
V6 = I6 Ry = 2 Ry I + ( V2 V1 ) Ry Re + ( V3 V4 ) Ry Re
(EQ. 21)
V OUT = A ( V 5 V 6 )
(EQ. 22)
where A is the gain of the output stage

A simplified schematic is shown in Figure 9.
( V 2 + V be2 ) ( V 1 + V be1 )
I x1 = ----------------------------------------------------------------------, and since V be1 = V be2
Re
V2 V1
I x1 = -------------------(EQ. 11)
Re
Assume Ry/Re = 1 (i.e., Re and Ry are equal value).

V OUT = A [ 2 R y I + ( V 1 V 2 ) + ( V 4 V 3 )
[ 2 R y I + ( V 2 V 1 ) + ( V 3 V 4 ) ]]
(EQ. 23)
V OUT = A [ ( V 1 V 2 ) + ( V 4 V 3 ) + ( V 1 V 2 ) + ( V 4 V 3 ) ]
Assuming high transistors:
(EQ. 24)
I 1 = I + I x1 = I + ( V 2 V 1 ) R e
(EQ. 12)
V OUT = 2 A [ ( V 1 V 2 ) + ( V 4 V 3 ) ]
(EQ. 25)
V OUT ( 2 A ) = [ ( V 1 V 2 ) + ( V 4 V 3 ) ]
(EQ. 26)
Since A is very large:
I 2 = I I x1 = I ( V 2 V 1 ) R e
V OUT ( 2 A ) 0
(EQ. 27)
Similarly for Q3 and Q4:
0 = ( V1 V2 ) + ( V4 V3 )
(EQ. 28)
I 3 = I + I x2 = I + ( V 4 V 3 ) R e
(EQ. 14)
Let VIN = V2 V1, and V3 = FB+, V4 = FB-
I 4 = I I x2 = I ( V 4 V 3 ) R e
(EQ. 15)
(EQ. 13)
Summing currents:
0 = -V IN + ( FB- FB+ )
(EQ. 29)
V IN + FB- FB+
(EQ. 30)
or
I5 = I2 + I3 = I ( V2 V1 ) Re + I + ( V4 V3 ) Re
(EQ. 16)
I5 = 2 I + ( V1 V2 ) Re + ( V4 V3 ) Re
(EQ. 17)
I6 = I1 + I4 = I + ( V2 V1 ) Re + I ( V4 V3 ) Re
(EQ. 18)
I6 = 2 I + ( V2 V1 ) Re + ( V3 V4 ) Re
(EQ. 19)
IN+ IN- = FB- FB+
(EQ. 31)
As you can see from Equation 31, negative feedback is

applied around the amplifier so that the voltage applied to
the feedback terminals (FB+ - FB-) must be equal to the
voltage applied to the input terminals (IN+ - IN-).
AN1298.2
May 27, 2009

For the standard data sheet connection:
V2
VIN
The input terminals (IN+ and IN-) and feedback terminals (FB+
and FB-) are single differential pair devices aided by an Input
Range Enhancement Circuit to increase the headroom of
operation of the common-mode input voltage. As a result, the
input common-mode voltage range for all these Instrumentation
Amplifiers is rail-to-rail. The parts are able to handle input
voltages that are at or slightly beyond the supply and ground
making these in-amps well suited for single 5V or 3.3V low
voltage supply systems. There is no need then to move the
common-mode input voltage of the these Instrumentation
Amplifiers to achieve symmetrical input voltage.
IN+
V1
INVOUT
VOUT
V4
FB+
V3
Rf
FB-
The use of a bipolar transistor input stage vs. the MOSFET

input stage allows the user to choose low bias current, high
input resistance.
Rg
Rail-to-rail operation for both the inputs and outputs is an

important and unique feature. The rail-to-rail inputs allow the
input voltages to be slightly below the VS- rail (typically
Ground) to slightly above the VS+ rail.

FB+ = 0V
FB- = V OUT R g ( R g + R f )
The conventional technique to achieve a rail-to-rail input

stage is to use two separate input stages, as shown in
Figure 12. One input stage (Q1 and Q2) provides common
mode input range to the top rail (VS+), and the other input
stage (Q3 and Q4) provides common mode input range to
the bottom rail.
V IN = FB- FB+
V IN = V OUT R g ( R g + R f ) 0
V OUT = V IN ( 1 + R f R g )
(EQ. 32)
Features of Instrumentation Amplifier

Product Family
A simplified schematic and block diagram is shown in
Figure 11 to illustrate the rail-to-rail operation for both the
input stage and the output stage. The same schematic
applies to the PMOS input devices when the PNP transistors
(Q1 to Q4) are replaced with P-Channel MOSFETs for
ultra-low input bias current.
VS+
INPUT RANGE ENHANCEMENT CIRCUIT
Ven = VS+ + 2V
I
Re
Vb
Va
Q1
IN-
I
Re
Q2
IBC
IN+
FB+
IBC
Q3
FB-
Q4
IBC
IBC
Q5
P-Channel
OUT
Ry
Ry
Q6
N-Channel
VSIBC => INPUT BIAS CURRENT CANCELLATION
FIGURE 11. SIMPLIFIED SCHEMATIC
AN1298.2
May 27, 2009

VS+
I
Q3
Q4
TRANSISTION
CIRCUIT
+IN
Q1
-IN
TO OUTPUT STAGE
INPUT OFFSET VOLTAGE (V)
250
VDD = 5.5V
200
-40C
150
100
+25C
50
0
-50
-100
+85C
-150
-200
-250
-0.5
Q2
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
COMMON-MODE INPUT VOLTAGE (V)
FIGURE 14. TYPICAL RAIL-TO-RAIL INPUT AMPLIFIER
FIGURE 12. 2 AMPLIFIER INSTRUMENTATION AMPLIFIER
Unless the input stages transistors are exactly matched,

changes in offset voltage and input bias current will result as
the common mode input range transitions between the two
input stages.
In contrast, the Product Family uses a single input stage for
the IN inputs and a single input stage for the FB inputs. An
Input Range Enhancement Circuit (IREC) provides a bias
voltage that is approximately 2V above the VS+ rail which is
used to bias the I current sources shown in the Block
Diagram. Since there is a single input stage, there is no input
stage transition point to create shifts in offset voltage and
bias current as the input common mode voltage changes.
The effectiveness of the Single Input Stage and IREC circuit
technique is evident as shown in the following Figures for the
offset voltage of a EL8170 (Figure 13) and a typical rail-torail input amplifier (Figure 14).
In addition to shifts in offset voltage as the input common

mode voltage changes, the input bias current will change
dramatically as the input stages transition from a PNP
transistor input stage to a NPN transistor input stage. The
following graphs compare the input bias current over the
common mode input range for the EL8170 (Figure 15) and a
typical rail-to-rail input amplifier (Figure 16).
AVERAGE INPUT BIAS CURRENT (pA)
VS-
1500
1000
VS = 3.3V
VS = 5.0V
500
VS = 2.9V
-500
-0.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0 5.5
250
200
+85C
INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE
3
150
+25C
100
50
-45C
0
-0.5
0.5
1.0
1.5
2.0
2.5
FIGURE 13. EL8170
3.0
3.5
IIB - INPUT BIAS CURRENT - (nA)
INPUT OFFSET VOLTAGE (V)
FIGURE 15. EL8170
VDD = 5V
TA = +25C
1
0
-1
-2
-3
-4
-0.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0 5.5
VIC - COMMON-MODE INPUT VOLTAGE (V)
FIGURE 16. TYPICAL RAIL-TO-RAIL INPUT AMPLIFIER
AN1298.2
May 27, 2009

The PNP input stage transistors are biased with an adequate
amount of current for speed, and consequently, their base
current increases. In order to keep the input bias current low,
an Input Bias Current Cancellation Circuit is used to apply
and equal but opposite compensation current to the inputs.
This compensation current subtracts from the base currents,
and the resulting input bias current is reduced to typically
around 500pA. This is shown in Figure 17 for the IN+ and INinputs, where the FB+ and FB- are identical for proper
matching between stages. The compensation current,
(Icomp) is derived from the IBC circuit and is equal to the
base current of Q1 and Q2.
Ven = VS+ + 2V
Re
Vb
Va
Q1
IN-
Q2
IN+
Icomp
Icomp
Q7
Q8
IBC
INPUT BIAS CURRENT
CANCELLATION
VS-
FIGURE 17. INPUT BIAS CURRENT CANCELLATION CIRCUIT
Since the feedback terminals are differential inputs, they can

be used in applications such as current sources for a true
Kelvin sense of the feedback voltage. In addition, a complex
network can be placed in the feedback path for frequency
shaping and filter circuits.
The basic Instrumentation Amplifier configuration is shown in
Figure 19:
Input Bias Current Cancellation Circuit is typically active

from 10mV above the negative rail (VS-) up to the positive
rail (VS+).
V2
Not only does the Input Bias Current Cancellation

compensation circuit keep the input bias current very small,
it also maintains a very small input bias current variation
over a wide operating range as shown in Figure 18 for +25C
to +85C.
AVERAGE INPUT BIAS CURRENT (pA)
Another unique feature built into the ISL28271 and ISL28272

is the ability to tri-state the output stage to a high impedance
state when the part is disabled via the ENABLE pin. This
allows several outputs to be wired together for a multiplexer
function. This feature will be shown in the Applications
section.
Because the Instrumentation Amplifier product family
provides an independent pair of feedback terminals to set the
gain and to adjust output level, these Instrumentation
Amplifiers achieve high CMRR regardless of the tolerance of
the gain setting resistors. The FB+ pin can be used as a REF
terminal to center or to adjust the output voltage. Because the
FB+ pin is a high impedance input, an economical resistor
divider can be used to set the voltage at the REF terminal
without degrading or affecting the CMRR performance. Any
voltage applied to the REF terminal will shift the output
voltage by VREF times the closed loop gain, which is set by
resistors RF and RG.
The operating voltage range of the Instrumentation Amplifier

product family is from 2.4V to 5.5V making it ideally suited
for operation on 3.3V or 5V power supplies. Also, it will
operate with a single 4.2 lithium ion battery. Additionally, they
are well suited for battery operation since the supply current
is only 66A maximum.
1500
VIN
V1
INVOUT
VOUT
V4
V3
VS = 3.3V
IN+
FB+
FB-
Rf
1000
500
+85C
+25C
Rg
FIGURE 19. TYPICAL RAIL-TO-RAIL INSTRUMENTATION

AMPLIFIER
-500
-1000
-0.5
0.5
1.0
1.5
2.0
2.5
FIGURE 18.
3.0
3.5
The gain of this circuit is set by the ratio of Rf and Rg such

that:
V OUT = V IN ( 1 + R f R g )
(EQ. 33)
AN1298.2
May 27, 2009

In this configuration, adjustable gain is possible with external
resistors for gains from unity up to 10,000. Two external gain
setting resistors are used to minimize temperature
coefficient (TC) mismatch as is common with a single gain
setting resistor.
Notice that resistor value mismatches only effect the gain,
and CMRR is not degraded by resistor mismatches as is the
case with the other basic Instrumentation Amplifier
configurations discussed previously.
In this case:
V REF = V CC R 2 ( R 1 + R 2 )
(EQ. 37)
The feedback terminals can also be used to apply a

reference voltage to shift the output voltage as shown in
Figure 22 with Rg connected to VREF instead of ground.
IN+
VIN
INVOUT
VOUT
The feedback terminals can be used to apply a reference

voltage to shift the input voltage. These are a high
impedance reference input that is not affected by gain. The
basic circuit is shown in Figure 20:
VREF
FB+
FB-
Rf
IN+
VIN
Rg
INVOUT
VOUT
VREF
FB+
FIGURE 22.
Rf
FB-
V IN = FB- FB+
FB- = V REF + R g ( V OUT V REF ) ( R f + R g )
V IN = V REF + R g ( V OUT V REF ) ( R f + R g ) V REF
Rg
V OUT = V IN ( 1 + R f R g ) + V REF
FIGURE 20. BASIC CIRCUIT
If we go back to the equations derived previously:

V IN = FB- FB+
(EQ. 34)
V IN = V OUT R g ( R f + R g ) V REF
(EQ. 35)
V OUT = ( V IN + V REF ) ( 1 + R f R g )
(EQ. 36)
Since the FB+ is a high input impedance, a simple resistor

divider could be used to set the VREF voltage as shown in
Figure 21.
IN+
VIN
INVOUT
VOUT
VCC
Rf
VREF
FB+
Rf
FB-
Rg
Rg
(EQ. 38)
Since the current in Rg must flow into VREF, the driving point
impedance of VREF will effect the accuracy of this
configuration. Therefore, VREF should be a low impedance
from an op amp, voltage regulator, or voltage reference.
Alternately, if a resistor divider is used to obtain VREF, the
Thevenin resistance of the divider network must be much
lower than the values of Rf and Rg, or the Thevenin
resistance must be included in the value of Rg and VREF.
However, the CMRR is not affected by the reference voltage
or its source resistance.
Care and Feeding of Instrumentation

Amplifiers
As in any low voltage, high accuracy measurement system,
extreme care must be taken with any of the Instrumentation
Amplifiers with respect to grounding scheme, Kelvin sense
connections, guarding and shielding, and interface to the
digital world. If the PCB connections are made incorrectly,
the most perfect measurement circuit can still have errors
resulting from poor grounding considerations and not
understanding the impact of Ohms Law. Any analog or
mixed signal PCB must have a well thought-out grounding
scheme with multiple ground planes or traces. There must
be no heavy DC current or AC current in the analog ground
planes that connect system measurement points.
FIGURE 21.
10
AN1298.2
May 27, 2009

be sure there is no digital noise introduced into the Analog
Ground, the two grounds are tied together at only one point
at the A/D Converter. Furthermore, a 0 resistor can be
used to connect the two grounds; this ensures a separate
Net for each ground so the PCB layout software or layout
person does not arbitrarily connect the two grounds. The use
of a 0 resistor is cheap insurance against a noisy and
inaccurate analog system! This Thermocouple Circuit will be
discussed in more detail in the Applications section.
A one point measurement system must be established to

prevent high currents from interfering with the basic
measurement. This is shown in Figure 23 for interfacing a
thermocouple to an A/D Converter. The High quality
measurement Ground must only connect to the critical
ground points in the analog front-end; this ground must
make a single point connection to the A/D converter at its
Analog Ground pin (AGND). There must be no other
connections such as digital grounds or power supply returns
to the High quality measurement Ground except a single
connection at the A/D Converter pins (AGND and DGND). To
+5V
7
VS+
+5V
R1
R
INPUT FILTER
J-TYPE
THERMOCOUPLE
(51.7V/C)
R2
R
IBIAS
+5V RETURN
LM35DM
(10m/C)
OPEN TC BIAS
R4
R
3
VS- 4
IN+
C1
C
(Vtc)
2
IN- V
OUT 6
(Vcjc) 8
R3
FB+
R
5
VOUT = (Vtc + Vcjc) * (1 + Rf/Rg)
Rf
191k, 1%
FB-
GAIN = 1 + Rf/Rg
GAIN = 1 + 191k/1k
GAIN = 192
R5
191k,
1%
R6
1k, 1%
A/D CONVERTER
s
VIN
ISL6007DIB825
Rg
1k, 1%
VOUT
(2.5V)
VREF
GND
HIGH QUALITY
MEASUREMENT GROUND
AGND
s
DGND
CONNECT AGND AND DGND

AT ONE POINT AT ADC
FIGURE 23.
Rs
1.2V
DC/DC CONVERTER
OUTPUT
PROCESSOR LOAD
10A, MAX
0.005
10k
0.1F
+5V
10k
7
VS+
EL8171, EL8173, ISL28273, ISL28271
3 IN+
2 INVOUT
VOUT = 0V to + 2.5V
8 FB+
5 FB- V S
Rf
48.7k, 0.1%
GAIN = 50
Rg
1k, 0.1%
FIGURE 24.
11
AN1298.2
May 27, 2009

Instrumentation Amplifiers can be used in high accuracy
current sense applications as shown in the circuit in Figure 24.
Notice the use of a Kelvin connection shown on the current
sense resistor Rs as indicated by the slanted connections to
the resistor. To avoid errors caused by IR drops, the
connections must be made directly at the leads of the
0.005 current sense resistor. Just 1m of contact
resistance or PCB trace resistance will cause a 20% error in
the current reading.
Guarding and driven guards is a PCB layout technique to
reduce errors caused by PCB leakage currents and improve
high frequency CMRR. This can be done by surrounding
high impedance input leads with traces that are driven by a
low source impedance voltage that is equal to the common
mode voltage.
At any point in a circuit where dissimilar metals come in
contact a small thermocouple voltage is developed.
Fortunately, the copper lead frame of a surface mount device
is the same copper material as PCB etch, and the
thermocouple effect is minimized. However, there are many
other places where thermocouples can be generated; for
example, across a connector finger, across relay contacts, or
even across a resistor! Yes, a poorly constructed resistor
can show many V/C of thermocouple voltage. It has been
found that external components (resistors, contacts, sockets,
etc.) can create thermocouple voltages that exceed
10V/C.
It must be recognized that thermocouple voltages are
developed by the difference in temperature between the two
ends of dissimilar metal junctions, and not the absolute
ambient temperature. If both ends of the metal junctions are
isothermal (i.e., at the same temperature) there is no
thermocouple voltage developed. Therefore, the first rule to
avoid thermocouple effects is to eliminate hot spots on a
PCB (e.g., linear voltage regulators). If hot spots cannot be
avoided, then the two ends of metal junctions must be
oriented so they are on isothermal lines on the PCB.
The second rule to minimize thermocouple effects is to
balance the number of junctions in a loop so that the error
voltages are cancelled or become a common mode voltage
that is reduced by the CMRR of the op amps in the signal
chain. If the number of junctions are not balanced, then it
may be necessary to create a junction by adding a series
resistor that has no effect on circuit operation but balances
the number of junctions.
Unknown to most design engineers is the danger of internal
clipping when operating an instrumentation amplifier on a
single supply. Unfortunately, the internal nodes are invisible
to the user and impossible to measure; manufacturers data
sheets often ignore the issue, or they have obscure typical
characteristics graphs or misleading paragraphs that
attempt to explain the phenomena. Since the
Instrumentation Amplifiers operate in a current summing
12
mode as explained in the Instrumentation Amplifier Product

Family Theory of Operation on page 6 there is no possibility
of internal clipping.
If we review the classic three amplifier instrumentation
amplifier configuration shown in Figure 25, the effect of
internal clipping can be clearly shown.
VCC
INA1
VIN
Rg
100
IN+
A2
VO1
+
-
10k
R1
50k
10k
R2
50k
VOUT
10k
A3
VO2
10k
VREF
Vcm
FIGURE 25.
Simple circuit analysis shows that the two internal voltage

VO1 and VO2 are:
V O1 = V IN ( 1 + R 1 R g ) + V cm
(EQ. 39)
V O2 = V cm V IN R 1 R g
(EQ. 40)
Two clipping conditions will occur if the effects of VIN and

Vcm are not considered:
1. VO1 cannot exceed the maximum output voltage for A1
which is the supply voltage (VCC) and the saturation
voltage of A1s output stage.
V IN ( 1 + R 1 R g ) + V cm < V CC + V sat
(EQ. 41)
2. VO2 cannot go below Ground + the saturation voltage of

A2s output stage.
V cm > V IN R 1 R g + V sat
(EQ. 42)
In reality, this places a such a severe restriction on single

supply operation that it makes this circuit almost impossible
to use as a general purpose single supply instrumentation
amplifier. For example, A2 output stage saturation voltage
prevents even 0V of common mode voltage!
To overcome this issue, modern monolithic IC
instrumentation amplifiers add PNP level shift transistors (Q1
and Q2) to raise the input voltages off Ground as shown in
the circuit in Figure 26.
AN1298.2
May 27, 2009
A1
VO1
Q1
there is no possibility of internal clipping. As long as the total

of the common mode voltage plus the input signal is
between 0V and the VS+ supply voltage there will be no
internal clipping. The output voltage will swing within its railto-rail output specification of 10mV to either rail for a 100k
load. There is no restriction on differential input voltage or
common mode voltage provided the output voltage does not
exceed its full scale range due to input voltage level, gain,
CMRR, and VREF level.
IN-
VCC
VIN
Rg
100
R1
50k
R2
50k
Q2
IN+
VO2
A2
Vcm
FIGURE 26.
The two internal voltage VO1 and VO2 are now:

V O1 = V IN ( 1 + R 1 R g ) + V cm + 0.7V
(EQ. 43)
V O2 = V cm V IN R 1 ( R g + 0.7V )
(EQ. 44)
Now, the danger of internal clipping situation has been

improved for A2 but made worse for A1 since an additional
0.7V has been added to VO1. For example, the maximum
common mode voltage is only 1.5V for this instrumentation
amplifier operating on a supply voltage of 5V 5% with a
gain of 250 and a 10mV input signal! If you doubt the validity
of these statements, check vendor data sheets for analog
devices that exhibit these characteristics.
All input and feedback terminals of the Instrumentation

Amplifiers have internal ESD protection diodes to both
positive (VS+) and negative supply (VS-) rails, limiting the
input voltage to within one diode drop beyond the supply
rails. The EL8170, EL8172, ISL28270 and ISL28470 have
additional back-to-back diodes across the input terminals
and also across the feedback terminals. If overdriving the
inputs is necessary, the external input current must never
exceed 5mA. On the other hand, the EL8171, EL8172,
ISL28271, ISL28272 and ISL28273 have no diode clamps to
limit the differential voltage on the input terminals allowing
higher differential input voltages at lower gain applications. It
is recommended however, that the input terminals of these
devices are not overdriven beyond 1V to avoid offset drift.
An external series resistor may be used as an external
protection to limit excessive external voltage and current
from damaging the inputs. A 20k resistor can be used to
protect the inputs against 100V transients on the inputs. If
the overvoltage condition is continuous, the 20k resistor
must be rated at 1W for adequate power dissipation.
Since the Instrumentation Amplifiers operate in a current

summing mode as explained in the Instrumentation
Amplifier Product Family Theory of Operation on page 6,
Ven = VS+ + 2V
VS+
I
Re
VS+
VS+
IN-
I
Re
VS+
FB-
IN+
VS-
VS-
VS-
VSEL8170 ONLY
EL8170 ONLY
INPUT BIAS CURRENT

CANCELLATION
5mA MAXIMUM INTO ANY PROTECTION DIODE!
INPUT BIAS CURRENT

CANCELLATION
VS-
FIGURE 27. INPUT PROTECTION DIODES
13
AN1298.2
May 27, 2009

20k
VIN
20k
TRANSFORMER
COUPLED SOURCE
IN+
VIN
INVOUT
IN+
IN-
VOUT
VOUT
8
FB+
Rf
FB-
VOUT
FB+
Rf
FB-
Rg
Rg
FIGURE 28.
FIGURE 30.
Input bias current from the IN+ and IN- inputs of the
Instrumentation Amplifiers must find a DC path to their home
(i.e., Ground). While it seems obvious to the casual user, this
is an often ignored principle when designing with an
Instrumentation Amplifier, and results in many telephone
calls to the Applications Engineer. Many voltage sources do
not provide a DC path to Ground such as thermocouples,
microphones, transformer coupled circuits, and AC coupled
circuits. Without a DC return path, the input bias current will
accumulate on any stray capacitance on the inputs until they
are clamped to the rails by the protection diodes. The output
of the Instrumentation Amplifier will slowly increase or
decrease until it saturates into the VS+ or VS- rail.
AC COUPLED SOURCE
VIN
2
47k
IN+
INVOUT 6
47k
8
VOUT
FB+
FB-
Rf
Rg
A DC return path as shown in the following circuits must be

supplied to provide a return path for the input bias current.
3
VIN
FIGURE 31.
IN+
INVOUT
10k
VOUT
FB+
Rf
FB-
Rg
An error budget can be calculated by summing the factors

which contribute to the output voltage error. Most of the error
sources are referred to the input and multiplied by the Gain
to get an output voltage error term as shown in the following.
Offset voltage: Normally instrumentation amplifiers have
two offset voltage specifications - an input offset voltage
(VOSI) and output offset voltage (VOSO) specification such
that the input offset voltage is multiplied by the gain, and the
output offset voltage exhibits unity gain to the output voltage.
Therefore, the output voltage error from offset voltage is:
V OUT = Gain V OSI + V OSO
FIGURE 29.
Due to the unique architecture of the Instrumentation

Amplifiers, there is only one offset voltage specification
required. The input offset voltage (VOSI) is the amount of
voltage applied the inputs terminals such that the voltage
across the FB is zero, or input offset voltage will be the
difference between the IN terminals and the FB terminals:
( IN+ IN+ ) = ( FB+ FB- ) + V OS
14
(EQ. 45)
(EQ. 46)
AN1298.2
May 27, 2009
V IB = R S I OS
(EQ. 48)
0.1Hz to 10Hz Noise: The error introduced by voltage can

be modeled the same as an input offset voltage, Vn. If noise
is required in a wider bandwidth than 0.1Hz to 10Hz, the
noise can be calculated by evaluating the Input Noise
Voltage Density (en) over the desired bandwidth. Multiplying
the rms noise by six will give a good approximation for the
peak-to-peak noise.
V OUT ( I OS ) = Gain R S I OS
(EQ. 49)
V OUT ( V n ) = Gain V n
V OUT ( V OSI ) = Gain V OSI
(EQ. 47)
Offset bias current: Similar to an Op Amp circuit, the input

resistance creates an error source that can be modeled the
same as offset voltage such that:
Gain Error: Gain error results from two factors. The first is
the basic gain deviation from the ideal gain equation, Gain =
(1 + Rf/Rg); for the EL8173 this error (E.g.) is typically
0.2%. Second is the tolerance (ERf and ERg) of the Rf and
Rg resistors which set the Gain.
Common Mode Rejection Ratio: The error introduced by

common mode voltage can be modeled the same as an
input offset voltage, VCMR.
CMRR = 20 log
10
V CMR = V CMV 10
( V CMR V CMV )
(EQ. 50)
( CMRR 20 )
V OUT = V IN ( 1 + R f R g ) [ 1 ( ER f + ER g + Eg ) ]
(EQ. 51)
V OUT ( CMRR ) = Gain V CMR
Rs
PROCESSOR LOAD
10A, MAX
0.005
10k
0.1F
(EQ. 54)
Temperature Drift: The effect of operating over the

expected temperature range must be included in all these
calculations based on the data sheet specifications.
(EQ. 52)
1.2V
DC/DC CONVERTER
OUTPUT
(EQ. 53)
+5V
10k
EL8171, EL8173, ISL28273, ISL28271
7
VS+
3 IN+
2 INVOUT
VOUT = 0V to + 2.5V
8 FB+
Rf
48.7k, 0.1%
5 FB- V S
4
GAIN = 50
Rg
1k, 0.1%
FIGURE 32.
TABLE 4. ERROR BUDGET CALCULATION
ERROR SOURCE
SPECIFIED VALUE
REFEREED TO OUTPUT
% FS ERROR
Offset voltage
400V
20mV
0.8%
Input Offset Current
0.5nA
0.25mV
0.01%
CMRR
104dB
0.24mV
0.01%
0.1Hz to 10Hz Noise
10V
0.5mV
0.02%
Gain Error
0.2%
0.2%
Rf, Rg Tolerance
0.1%
0.2%
Total Error
15
1.24%
AN1298.2
May 27, 2009

Example of an Error Budget Calculation
Consider the circuit shown in Figure 32 for a CPU core
voltage current monitor circuit operating at +25C.
The importance of an Error Budget as shown in Table 4 is
that it is shows the overall accuracy which can be expected
and which factors are determining the overall accuracy of
the circuit. In this circuit, the Offset voltage is the factor
which is driving the Total Error; if tighter accuracy is required
for the application, the offset term could be removed by
hardware calibration with a digital potentiometer or software
calibration. The Total Error could be reduced to 0.5% just by
decreasing the offset voltage term by a factor of 10.
within a few millivolts of the supply rails. At a 100k load, the

PMOS sources current and pulls the output up to 4mV below
the positive supply, while the NMOS sinks current and pulls the
output down to 4mV above the negative supply, or ground in
the case of a single supply operation. As the load current is
increased, the maximum output voltage will decrease as a
result of the voltage drop caused by the sourced load current
times the top MOSFET ON resistance. Likewise, the minimum
output voltage will increase as a result of the voltage drop
caused by the sink load current times FET ON resistance.
The current sinking and sourcing capability is internally
limited to about 26mA with a 5V supply.
Because of the independent pair of feedback terminals

provided by Intersils Instrumentation Amplifiers, the CMRR
is not degraded by any resistor mismatches. Hence, unlike a
three op amp and especially a two op amp instrumentation
amplifier, the Intersil solution will reduce the cost of external
components by allowing the use of 1% or more tolerance
resistors without sacrificing CMRR performance. The CMRR
will be greater than 100dB regardless of the tolerance of the
resistors used.
Care must be taken with excessive load capacitance, CLOAD.

As shown in the following graphs, excessive load capacitance
will cause excessive peaking in the frequency response. The
result will be ringing in the output voltage under transient
conditions, and potentially oscillations resulting from unstable
operation. If the Instrumentation Amplifiers are used in
applications where there may be large load capacitance
(cable driving, filters, FET gates, etc.), a suitable buffer should
be used on the output of the Instrumentation Amplifier.
The effects of loading the rail-to-rail output stage must also be

considered too since the output stage exhibits an ON state
resistance. A pair of complementary MOSFET devices with
approximately 50 ON resistance drives the output VOUT to
Noise calculations for the Instrumentation Amplifiers are very

similar to those for an op amp circuit. The noise model is shown
in the following where the Input Noise Voltage and Input Noise
Current noise sources are lumped into the IN+ terminal.
25
30
VS = 2.5V
25
MAGNITUDE (dB)
MAGNITUDE (dB)
20
VS =
15
VS =
10 A = 10
V
RL = 1k
C = 10pF
5 RL/R = 9.08
F G
RF = 178k
RG = 19.6k
0
100
1k
10k
100k
FREQUENCY (Hz)
1M
FIGURE 33. EL8171 FREQUENCY RESPONSE vs SUPPLY

VOLTAGE
20
CL = 27pF
15
A = 10
10 VV = 5V
S
RL = 10k
5 RF/RG = 9.08
RF = 178k
RG = 19.6k
0
100
1k
10k
100k
FREQUENCY (Hz)
1M
FIGURE 34. EL8171, EL8172 FREQUENCY RESPONSE vs

CLOAD
50
30
CL = 47pF
CL =
20
CL = 27pF
15
A = 10
10 VV = 5V
S
RL = 10k
R
5
F/RG = 9.08
RF = 178k
RG = 19.6k
0
100
1k
10k
100k
FREQUENCY (Hz)
CL =
1M
CL =
40
CL = 820pF
35
30
FIGURE 35. EL8171 FREQUENCY RESPONSE vs CLOAD
16
45
MAGNITUDE (dB)
25
MAGNITUDE (dB)
CL =
CL = 47pF
AV = 100
VS = 5V
RL = 10k
RF/RG = 99.02
RF = 221k
RG = 2.23k
25
100
1k
CL = 390pF
10k
100k
FREQUENCY (Hz)
1M
FIGURE 36. EL8172 FREQUENCY RESPONSE vs CLOAD
AN1298.2
May 27, 2009

en(V)
en(I1)
en(I2)
en(Rs)
en(Rfg)
IN+
IN-
Rs
VOUT
VOUT
FB+
Rf
FB-
Rg
NOISE MODEL
FIGURE 37.
Where: en(V) is the Input Noise Voltage over the desired

bandwidth en(I1) is the voltage noise generated by the Input
Noise Current over the desired bandwidth and the source
resistance (Rs):
The 1.57 term in the equations is the noise equivalent

bandwidth representing a 1st order roll-off equivalent as if
there is a brick wall filter at 1.57*Fh. If we have a brick wall
filter that cuts off right (infinitely steep) at Fh then this term is 1.
e n ( I1 ) = I IN R s
1st order = 1.57

2nd order = 1.11
3rd order = 1.05
4th order = 1.025
(EQ. 55)
en(I2) is the voltage noise generated by the Input Noise

Current over the desired bandwidth and the feedback and
gain resistors (Rf || Rg):
e n ( I2 ) = I IN R f || R g
(EQ. 56)
en(Rs) is the thermal noise over the desired bandwidth of Rs.

en(Rfg) is the thermal noise over the desired bandwidth of
Rf || Rg
Rs is the source resistance
e n = ( 1 + R f R g ) ( e n ( V ) + e n ( I1 ) + e n ( I2 ) + e n ( I2 ) + e n ( Rs ) + e n ( Rfg ) )
(EQ. 59)
The peak-to-peak output noise is typically 6 times the rms

value (rule of thumb).
Rf and Rg are the gain setting resistors

To calculate rms noise, N over a desired bandwidth:
N = N O ( F C ln ( F h F l ) + 1.57 F h F l )
To determine the total rms output noise from all the sources,
the rms summation is taken multiplied by the gain.
en ( P P ) = 6 en
(EQ. 60)
(EQ. 57)
eno(pp) = 6 * eno
where: NO is the specified noise density in nV/Hz

Fc is the corner frequency
Fh is the upper frequency of interest
Fl is the lower frequency of interest
To calculate resistor thermal noise over a desired bandwidth:
Nr =
4kTR ( 1.57 F h F l )
(EQ. 58)
where: R is the resistor value

k is Boltzmans Constant, 1.39*10-23
T is temperature in Kelvins
Fh is the upper frequency of interest
Fl is the lower frequency of interest
17
AN1298.2
May 27, 2009

+5V
Rb1
1k
Rb3
1k
+5V
R1
7.5k
R2
7.5k
IN+
7
VS+
INVOUT
Rb2
1k
Rb4
1k
VOUT + 0V to 2.5V
FB+
FB- VS-
Rf
100k
Rg
100k
FIGURE 38.
Example of Noise Calculation:

Consider the circuit shown in Figure 38 for a bridge amplifier operating in a 0.5Hz to 100Hz bandwidth with a full scale output
voltage of 2.V.
eN = 50nv/Hz
From the EL8170 data sheet specifications
Fc = 100Hz
From the EL8170 data sheet performance curves
iN = 0.1pA/Hz
From the EL8170 data sheet specifications
Fc = 50Hz
From the EL8170 data sheet performance curves
Rs = 8k
Balanced bridge Thevenin resistance + 7.5k resistor
Rfg = 990
Rf || Rg = 90.9k || 1k
e n ( V ) = 50nV Hz 100Hz L n ( 100Hz 0.5Hz ) + 1.57 100Hz 0.5Hz

= 0.81 V, rms
(EQ. 61)
e n ( I1 ) = 0.1pA Hz 50Hz L n ( 50Hz 0.5Hz ) + 1.57 100Hz 0.5Hz 8k

= 0.12 V, rms
(EQ. 62)
e n ( I2 ) = 0.1pAnV Hz 50Hz L n ( 50Hz 0.5Hz ) + 1.57 100Hz 0.5Hz 990

= 0.0014 V, rms
e n ( Rs ) =
(EQ. 63)
( 4 k 300K 8k ( 100Hz 0.5Hz ) )
= 0.12 V, rms
e n ( Rfg ) =
(EQ. 64)
( 4 k 300K 990 ( 100Hz 0.5Hz ) )
= 0.04 V, rms
(EQ. 65)
18
AN1298.2
May 27, 2009

2
+5V
e n = ( 1 + R f R g ) ( e n ( V ) + e n ( I1 ) + e n ( I2 ) + e n ( Rs ) + e n ( Rfg ) )
2
7
3
= ( 1 + 90.9k 1k ) (0.81V +0.012V +0.0014V +0.12V +0.04V )

= 100 0.82V
(EQ. 66)
= 82 Vrms
VIN
To determine the total rms output noise from all the sources,
the rms summation is taken multiplied by the gain.
Note that the total output noise is dominated by basic Input

Noise Voltage and higher source resistance could be used
without degrading the overall error resulting from noise.
e n ( P P ) = 6 82V
IN+
VS+
IN-
VOUT 6
VOUT
FB+
Rf
100k
FB- VS-
Rf
12k
Cx
0.1F
(EQ. 67)
= 492 V P P
GAIN = 100 BELOW 14Hz

GAIN = 100 BELOW 140Hz
Rg
1k
This represents an error of 0.02% for a 2.5V full scale output.

A very unique feature of the Intersil Instrumentation
Amplifiers is the ability to put a filter circuit in the feedback
network to shape the frequency response of the amplifier.
This ability is not possible with other monolithic
Instrumentation Amplifiers because they use a single
resistor at the input stage to set the gain. Adding filter circuits
in the feedback network of an Instrumentation Amplifier
implemented with discrete components (op amps and
resistors) is very difficult because capacitor mismatch will
result in very poor high frequency CMRR.
GAIN = 100
GAIN = 10
14Hz
Flp
140Hz
Fhp
FIGURE 39.
A complex impedance network can be added as shown in

the following for a low pass function. The low frequency gain
is set by Rf and Rg using the standard equation:
For this circuit, it can be shown that low frequency pole and
higher frequency zero are:
Gain = 1 + Rf R g
Flp = 1 ( 2 C x ( R f + R x ) )
(EQ. 68)
The Instrumentation Amplifiers are not unity gain stable; i.e.,

they require gains greater than 10 or 100 depending on the
device. Therefore, they must never be allowed at unity gain
even at high frequencies! If Rx was not included in this
circuit, Cx would dominate at high frequencies, and the
Instrumentation Amplifier would be unstable and oscillate.
Lab tests have shown that Cx >33pF is enough to cause an
oscillation. Adding Rx in series with Cx creates a zero in the
transfer function so that at higher frequencies Rx parallels Rf
so that the new Rf = 10.7k, and the gain at high frequency is
11.7 which is a stable condition. Lab tests have shown that
any value can be used for Cx with no oscillations.
19
Pole Frequency
= 1 ( 2 0.1F ( 100k + 12k ) )

= 14Hz
Flp = 1 ( 2 C x R x )
(EQ. 69)
Zero Frequency
= 1 ( 2 0.1F 12k )
= 140Hz
(EQ. 70)
AN1298.2
May 27, 2009

6
7
8
3
1
2
A2
A1
VIN+
SW0 CLOSED
V+ 10 +5V
SW1 CLOSED
4
INH
SW2 CLOSED
SW3 CLOSED
A2
A1
NO0
NO1
NO2
NO3
Com 9
U1
ISL43640
GND
Vcm
MEASURE VIN+ - VINMEASURE CMRR TO ZERO

MEASURE VOS TO ZERO
MEASURE 25mV CAL REFERENCE
VIN-
R2, 1M
A2
A1
NO0
NO1
NO2
NO3
GND
5
(VREF)
R3
100k
R1, 10k
REQ = 9900
V+ 10
+5V
INH 4
WRITE
PROTECT
U2
ISL43640
VOUT VIN
C2
0.01F
C1
10F
R9
309
R5
48.7k
R7
66.5k
R6
1k
-5V
U3
ISL6007DIB825
OFFSET CORRECTION (25mV)
VOUT
R8
150k, 1%
5 FB-
RW 5
50k
RL 6
2 +5V
GND
1 4
R4, 2k
VOUT 6
8 FB+
8
VCC
1 WP-L
RH 7
GND
U5 4
ISL95810
s
+5V
VS- 4
2 IN-
2 SCL
RP1
I2C BUS
3 SDA
Com 9
VS+ 7
3 IN+
+5V
6
7
8
3
1
2
U4
EL8173
+5V
8
VCC
7 RH
WP-L 1
5 RW
50k
6 RL
SCL 2
RP2
SDA 3
GND
4
R10
1.37k, 1% s
s
WRITE
PROTECT
I2C Bus
U6
ISL95810
PROGRAMMABLE GAIN, 90 TO 110
CALIBRATION REFERENCE (25mV)
FIGURE 40. ANALOG FRONT-END CIRCUIT
Application Circuits
Instrumentation Amplifier With Auto Zero and
Auto Gain Calibration
The circuit shown in Figure 40 shows an analog front-end
circuit with an Auto Zero and Auto Gain Calibration to eliminate
the offset voltage and gain errors of the EL8173. It is intended
to be part of an overall data acquisition system with an A/D
Converter and microprocessor to perform an auto zero/gain
software routine. Figure 40 does not include the A/D Converter
or processor hardware/software.
TABLE 5.
A2
A1
SWITCH
CLOSED
MODE
SWO
Measure the input voltage VIN+ - VIN-
SW1
Calibrate with external common mode

voltage applied
SW2
Calibrate offset voltage to zero
SW3
Calibrate gain with 25mV reference

voltage applied
During the calibration mode, analog switches S1 and S2

connect the inputs of the EL8173 to calibration source voltages
of zero volts, an external common mode voltage, or a 25mV
reference voltage. Digital potentiometer (D-Pot) U5 applies a
programmable offset voltage of 25mV to the FB+ pin of the
EL8173 to adjust the EL8173 output to zero voltages. Digital
potentiometer (D-Pot) U6 programs the gain of the EL8173
from 90 to 110 for a 2.5V output with the +25mV reference
voltage applied to the inputs.
20
Since the offset calibration voltage is operating at very close

to zero voltages (25mV), the driving point impedance is
kept very low (1k, R6) to avoid variations caused by the
increasing bias current. The configuration of U5, R5, and R7
is carefully selected so that the D-Pot never is operated at a
negative voltage.
The 25mV offset calibration source is obtained by
programming U5 with the appropriate digital code in
Equation 71.
1
1
5 -------------------------- ------R + R R
1
pot
2
Vcal = ----------------------------------------------------------1
1
1
------------------------- + ------- + ------R + R R
1
pot
2 R3
(EQ. 71)
The +25mV reference voltage is obtained with the ISL6007s

2.5V output voltage divided down by a factor of 100 with R1,
R2, and R3. The accuracy of the gain calibration is
determined by the accuracy of the ISL6007 and the
tolerance of resistors R1 and R2. Therefore, it is
recommended to use very low tolerance resistors for R1 and
R2, or use a precision resistor divider network.
The gain of the EL8173 is programmed by D-Pot, U6
according to Equation 72:
R 8 + R 9 + R 10
Gain = --------------------------------------------Code
R 10 + --------------- R g
255
150000 + 309 + 1370
Gain = -------------------------------------------------------Code
1370 + --------------- 309
255
151.7k
Gain = -------------------------------------------------1370 + 1.2 Code
(EQ. 72)
AN1298.2
May 27, 2009

Another complication of SPPT application is the large
temperature dependence of both total bridge resistance and
peizosensitivity (the ratio of bridge output to excitation
voltage times pressure). Bridge resistance increases with
temperature while peizosensitivity decreases. Some SPPT
designs (e.g. the Nova Sensor NPC-410 series) carefully
equalize these opposite-sign tempcos. The payoff comes
when such SPPTs are excited with constant current because
the increase with temperature of bridge resistance (and
therefore of bridge excitation voltage) then cancels the
simultaneous decrease of peizosensitivity.
Other nominal gains and gain adjustment range can be

made by changing the values of R8, R9, and R10.
Pressure Sensor Interface Circuit

Programmable Pressure Transducer Circuit
The silicon piezoresistive-bridge pressure transducer (SPPT)
is a dominant technology in automotive, industrial, medical,
and environmental pressure sensor applications. All SPPTs
share a similar architecture in which a thin (5m to 200m)
micro machined silicon diaphragm incorporates an implanted
piezoresistive Wheatstone-bridge strain-gauge. Applied
pressure bends the diaphragm, imbalances the strain gauge,
and thereby produces a differential output signal proportional
to the product of pressure times bridge excitation voltage.
A 10mV/psi pressure-proportional strain gauge signal is

outputted differentially on pins 2 and 4 of the sensor; this signal
is superimposed on a common mode voltage of 1.2V from the
bridge excitation voltage. The low level differential output
voltage is amplified by the EL8173 with a nominal gain set at
50. The high common mode rejection capability of the EL8173
eliminates the common mode output voltage of the bridge. The
bridge is biased from a constant current source (Q2) and two
digitally controlled potentiometers provide for zero (DPOT1)
and full scale (gain) adjustments (DPOT2).
SPPTs must be supported by appropriate signal conditioning

and calibration circuits. Finite elasticity limits the SPPT
diaphragm to relatively small deflections which generate only
1% modulation of the bridge resistance elements and low
signal output levels, creating the need for high gain, low-noise,
temperature-stable DC amplification. The signal conditioning
circuit must also include stable, high resolution, preferably
non-interactive, zero and span trims. The automation of the
calibration of the sensor circuit is an enormous benefit in the
production environment.
In the detailed circuit shown in Figure 41, the U2b and U3

circuit provides for the precision offset adjustment, via
DPOT1, of any transducer initial null offset error. To
+5V
R3
402
R2
402
CURRENT MIRROR FOR LOW HEADROOM

FROM +5V SUPPLY
Q2
DMMT3906
BRIDGE EXCITATION, 600A CURRENT SOURCE
U2a +5V
1/2 ISL28276
U1
+5V
IN OUT
GND
ISL60002-11
(1.200V)
Q1
2N3904
4k
4k
U2b
1/2 ISL28276
+5V DPOT VOLTAGE ALWAYS POSITIVE
R3
39.2k
DPOT1
1/2 X95820
50k, 256 TAPS
R6
20k
U3
EL8176
R4
54.9k
-5V
4k
R1
2k
Vbridge, MAX = 600A*6k = 3.6V
R5
20k
U4
EL8173
IN+
C1
1000pF
BUFFERED
+Vbridge
Zin = Zout = 4k, TYP

(2.5k TO 6k)
VS+
OUT+ 2
OUT- 4
IN+
IN-
IN-
+5V
4
s
IN-
4k
8
VS-
VOUT
VOUT
0.5V/PSI
FB+
FB-
R8
115k
GAIN = 40 TO 60
PS1
NPC-410
0PSI TO 5PSI
(25mV AT MAX Vbridge = 3.6V)
(10mV AT MAX Vbridge = 1.5V)
GAIN CALIBRATION CIRCUIT

R7
1k OFFSET CALIBRATION CIRCUIT
R9
1k
DPOT2
50k, 256 TAPS
1/2 X95820
R10
1.96k
-Vbridge
FIGURE 41.
21
AN1298.2
May 27, 2009

accomplish this, the bridge excitation voltage is
programmably attenuated by DPOT1 and applied to the FB+
pin of the EL8173. The range for the zero adjustment voltage
is from +25mV to -25mV. The resolution is 200V and is
proportional to the bridge excitation voltage, thus improving
the temperature stability of the zero adjustment.
The 10mV/psi bridge output signal is amplified by 50x to a
convenient 0.5V/psi output level with the EL8173 its
feedback and calibration network consisting of R8, R9, R10,
and DPOT2. The gain of U3 can be varied from 40 to 60 with
a resolution of 0.10.
Bridge bias is provided by the constant current circuit (U1, U2a,
and Q1) which sets a current in Q1 of 1.2 V/2k = 600A. A
current mirror (Q2, R2, R3) reflects the output current so as to
source the 600A into the top of a grounded bridge (PS1).
The net result of the combination of transducer and the
EL8173 circuitry is a signal conditioned precision pressure
sensor that is compatible (thanks to DPOT1 and DPOT2)
with full automation of the calibration process, is very low in
total power draw (<2mA), most of which goes to transducer
excitation and current mirror circuit.
Thermocouple Input with A/D Converter

Output
Thermocouples are the industry standard temperature
sensor for measuring a wide range of temperatures from
-250C to + 2300C. The four most popular thermocouple
types are shown in Table 6; however, any time two dissimilar
metals are placed in contact, a thermocouple is created via
the Seebeck Effect.
Thermocouples present several unique challenges when

interfacing them to a real world measurement system.
1. Thermocouples generate a very low output voltage that
must be amplified with a high gain amplifier. Each
thermocouple type requires a different gain when
interfacing to an A/D Converter with a fixed full scale
voltage, VFS/VoMAX.
2. Thermocouples do not generate an absolute voltage that
is proportional to temperature. Instead, they generate a
voltage that is a relative voltage that is the proportional to
the temperature difference between the hot end and the
cold end. All thermocouple tables showing output
voltage vs temperature are for the cold end placed in an
ice bath at 0C. Since it is very impractical to place an ice
bath on a PCB, electronic cold junction compensation is
used. Each thermocouple type requires a cold junction
compensation rate, dVO/dT.
3. The output voltage of a thermocouple is non-linear, and is
dependant on the type of thermocouple. Linearization is
most often done with diode break-point techniques or via
microprocessor software, and is not covered in this
Application Note.
The circuit shown in Figure 42 uses the unique features of
the Intersil EL8173 Instrumentation Amplifier to simplify the
Thermocouple interface to a high resolution A/D Converter
(U5). A programmable gain digital pot (U3) and
programmable temperature sensor (U2) allows digital
selection of the four most popular thermocouple types: E, J,
K, and T.
TABLE 6. POPULAR THERMOCOUPLE TYPES

TEMPERATURE RANGE
VO at TMIN
VO at TMAX
dVO/dT 0C to +50C
TYPE
MINIMUM
MAXIMUM
(mV)
(mV)
(V/C)
-200C
-328F
+900C
+1652F
-8.83
68.79
61.00
0C
+32F
+750C
+1382F
0.00
42.30
51.70
-200C
-328F
+1250C
+2282F
-5.89
50.64
40.50
-250C
-328F
+350C
+662F
-5.60
17.82
40.70
22
AN1298.2
May 27, 2009

U1
EL8173
E, J, K, T TYPE
THERMOCOUPLE
8Hz INPUT FILTER
VS+ 7
R1
1k
(VTC)
R3
(VCJC)
1M
R2
1k
+5V
I2C
BUS
SLAVE
ADDRESS BUS
(0101000x)
5
6
3
2
1
R7
4.53k
7 RH
1.6Hz LPF
s
ISL21400
OSC1
OSC2
16
13 AVDD DVDD 15
5 RW
R5
10.7k
6 RL
COLD JUNCTION COMPENSATION
R8
1.05k
SCLK 1
CLOCK
(VOUT)
12 VINHI
SDIO 3
DATA I/O
R6
150.0k
11 VINLO
SDO 2
DATA OUT
+5V
8
VCC
WP-L 1
SCL 2
50k
3
SDA
SYNC 19
10 VCM
8 VRLO
6 DGND
CS 4
DRDY 5
RST 18
SYNC
CS
DATA READY
RESET
MODE 20
9 VRHI
WRITE
PROTECT
GND
4
U3
s ISL95810
I2C BUS
+5V
2 VIN VOUT
GND
U4 1 4
ISL21009-25
PROGRAMMABLE GAIN
GAIN = 30 TO 150
+5V
7 AVSS
-5V
14 AGND
SCL
R4
SDA
7 357k
VOUT
A0
A1
C2
10F
A2 VSS
U2
VOUT
8 FB+
5 FB-
8
VCC
+5V
s
2 IN-
10Mhz
17
+5V
3 IN+ VS- 4
C1
10F
Y?
U5
HI7190
C3
0.01F
R9
2k
C4
10F
FIGURE 42.
The programmable gain amplifier (U1, U3) provide a gain

from 30 to 150 that is programmed via the I2C bus with the
digital pot for each of the thermocouple types as shown in
Table 7.
TABLE 7. THERMOCOUPLE TYPES
TC TYPE
MAX VOUT
GAIN
D-POT
CODE10
68.97mV
36.34
195
42.30mV
59.10
094
50.64mV
49.37
126
17.82mV
140.3
000
Cold junction compensation is provided by a programmable

reference/temperature sensor (U2) and resistor divider
network R4 and R5 according to the following table with
AV = 1 and N register = 0.
TABLE 8. COLD JUNCTION COMPENSATION
TC TYPE
VCJC (V)
M REGISTER
61.0
51.7
20
40.5
43
40.7
43
23
Low pass filters (R1, R2, C1) provide noise filtering with a
8Hz cut-off frequency. R3 is used for a return current path for
the EL8173 input bias current. An additional low pass filter
(R4, R5, C2) attenuates the ISL21400s output noise voltage
with a 1.6 Hz cut-off frequency.
A high resolution (24-bit) Sigma-Delta A/D Converter,
HI7190, converts the output of the instrumentation amplifier,
EL8173, with a full scale input voltage of 2.5V set by the
ISL21009-2.5 voltage reference.
Thermocouple Input with 4mA to 20mA

Output Current
Another output option for a thermocouple input circuit is an
industry standard 4mA to 20mA current transmitter. The
theory of operation for a 4mA to 20mA current transmitter
circuit is described in Intersil Application Note AN177 with
Figures 33, 34, and 35; this theory of operation applies to the
thermocouple circuit shown in Figure 43, and therefore, will
not be repeated.
AN1298.2
May 27, 2009

+5V
J-TYPE
THERMOCOUPLE
(51.7V/C)
U1
EL8173
8Hz INPUT FILTER
R1, 1k
R2, 1k
D2
BAT54C
+5V
PROG.
8
VCC
I2C BUS
U2
ISL21400
(VTC)
2 IN-
R3
1M
VOUT 6
(VCJC) 8
FB+
+5V
R14 R15
SCL
SDA
C1
10F
7
VS+
3 IN+ VS- 4
R4
357k
5 FB-
VOUT 7
5 SCL
(51.7V/C)
6 SDA
4 VSS
A0 A1 A2
R5
3 2 1
10.7k, 1%
SLAVE ADDRESS
(010100x)
RTN
PROG.
COLD JUNCTION COMPENSATION
GAIN = 58.6
U5
ISL60002BIH325Z-TK
LM2936M-5.0
U4
1 VOUT VIN 8
VOUT VIN
GND
GND
C3
C4
0.001F
10F
2 3 6 7
C5
4.7F
+5V
R8
U3
Q1
499k
EL8176
IRLL014N
7
(0V TO 2.5V)
3
6
R9
2
R13
127k R10
10
80.6k
4 R12
R6
100k
57.6k, 1%
D1
B140
+Vloop
7VDC TO 30VDC
LOOP
RESISTOR
(INTERNAL "GROUND")
R11
100
R7
1k, 1%
1.6Hz LPF
CURRENT TRANSMITTER
C2
10F
ISL21400 REGISTER VALUES

AV = 1, N = 0
J-TYPE
M = 20
VCJC = 51.7V/C
FIGURE 43.
The circuit uses the unique features of the Intersil EL8173

Instrumentation Amplifier to simplify the Thermocouple
interface to a 4mA to 20mA Current Transmitter circuit.
Since this is circuit is shown for a single J-type
thermocouple, a fixed gain of 58.6 is used so that the output
voltage of the EL8173 is +2.5V at the maximum
thermocouple temperature. The ISL21400 programmable
voltage reference/temperature sensor is used for cold
junction compensation. Since the ISL21400 has non-volatile
storage of the register values, it can be programmed either
prior to PCB assembly or programmed via the I2C bus as
shown in this schematic. It must be cautioned that the I2C
programming ground is not at the same potential as the
Internal Ground or loop supply ground; therefore, when
programming U2, the loop supply power supply or
associated grounds must not be connected, or the I2C
programming system must be floating off ground.
Low pass filters (R1, R2, C1) provide noise filtering with a
8Hz cut-off frequency. R3 is used for a return current path for
the EL8173 input bias current. An additional low pass filter
(R4, R5, C2) attenuates the ISL21400s output noise voltage
with a 1.6Hz cut-off frequency.
Since the 4mA to 20mA loop voltage can be as high as
24VDC, a high voltage linear voltage regulator (U5) is used
to generate an internal +5V supply.
24
RTD Input with A/D Converter Output

Another popular industry standard temperature sensor is the
RTD whose resistance varies with temperature, and is
typically specified with a nominal resistance at +25C. For
example, a PT100 RTD has a resistance of 100 at 0C.
The shape of the resistance vs temperature curve is
described by Equation 73, a second order equation, with a
unique alpha value as defined by DIN EN 60751. For a
PT100 RTD with alpha = 0.385%/ C:
2
RTD = R 0 ( 1 + A T + B T + C ( T 100 ) T )
(EQ. 73)
Where: A = 3.9083 E-3, B = -5.775 E-7, C = -4.183 E-12

below 0C and zero above 0C.
RTDs are typically biased with 1mA to 5mA to minimize selfheating effects; this low operating current generates very low
voltage levels shown in Table 9.
TABLE 9. TYPICALLY BIAS RTDs
TEMPERATURE
(C)
RTD
()
VRTD @ 1mA
(mV)
-40
84.3
84.3
100.0
100.0
+100
138.5
138.5
+200
175.8
175.8
AN1298.2
May 27, 2009

In the circuit shown in Figure 44, RTD excitation current is
supplied by R1 and R2 operating from +5V. It would appear
that this current is not accurate enough for a high precision
temperature measurement. And, that is true except for the
trick that is played by utilizing the ratiometric mode of
operation with the A/D Converter.
Since the RTD is often operated a great distance from

receiving electronics, the use of differential voltage sensing
is used to reduce the errors generated by high mode voltage
induced noise.
The circuit in Figure 44 shows an RTD interface to a high
resolution A/D Converter using an EL8173 Instrumentation
Amplifier to differentially sense the RTD output and provide
the proper gain for the input to the A/D Converter. Ratiometric
mode operation of the A/D Converter eliminates the error
introduced by variations in the RTD excitation current.
TABLE 10.
TEMP.
(C)
RTD
()
IEXT
(mA)
VRTD @ 1mA
(mV)
CODE
OUT10
-40
84.3
1.22
84.3
7 778 756
100.0
1.22
100.0
9 227 469
+100
138.5
1.21
138.5
12 780 044
+200
175.8
1.20
175.8
16 240 345
IEXT
Rw
+
VOUT
RTD
Rw
-
Rw
FIGURE 44.
R1
2k
+5V
Y1
R2
2k
Rw1
RTD
PT100
3-WIRE
U1
EL8173
VS+ 7
3 IN+
+5V
VS- 4
s
2 IN-
(VOUT)
VOUT 6
Rw2
+5V
8 FB+
R3
10k
5 FB-
Rw3
GAIN = 11
16
OSC2
13 AVDD
DVDD 15
+5V
9 VRHI
SCLK 1
CLOCK
8 VRLO
SDIO 3
DATA I/O
12 VINHI
SDO 2
DATA OUT
11 VINLO
SYNC 19
14 AGND
R4
1k
+5V
17
OSC1
10 VCM
GAIN = 11
Rw1, Rw2, Rw3 - LEAD RESISTANCE
#22 AWG WIRE - 0.0168/Ft
-5V
10MHz
CS 4
DRDY 5
6 DGND
RST 18
7 AVSS
MODE 20
SYNC
CS
DATA READY
RESET
U5
HI7190
24 BIT SIGMA DELTA
A/D CONVERTER
R5
10k
R6
1k
FIGURE 45.
25
AN1298.2
May 27, 2009

A/D CONVERTER
VCC
Code = 2N*(VOUT - 0)/(IEXT*R1)

Code = 2N*Gain*IEXT*RTD/(IEXT*R1)
REFHI
Code = 2N*Gain*RTD/R1
R1
Now, the output code is only dependant on the gain of the

EL8173 and value of R1, and the variations of IEXT are
cancelled out by the ratiometric operation of the A/D
Converter.
REFLO
Iext
Also, there is an error created by the wire resistance from

the RTD leads from the RTD to the voltage sensing point.
Therefore, RTDs are often connected with 3-wire and 4-wire
lead configurations to reduce the effect of wire resistance.
By far, the most common configuration is the 3-wire
connection, and many general purpose 3-wire RTDs are
available. Three different configurations for RTD wiring are
summarized in the following.
IN+
VOUT
Rtd
IN-
IN+
IN-
EL8173
GAIN
FIGURE 46.
In the simplified circuit shown in Figure 46, IEXT = VCC/(R1 +

RTD) and VRTD = IEXT*RTD, VOUT = Gain*IEXT*RTD
For the A/D Converter, the digital output code,
N
2 ( IN+ - IN- )
CODE = -------------------------------------------------REF HI REF LOW
(EQ. 74)
Where N = Resolution
However, even with a 3-wire configuration, there is still an

error associated with the voltage drop caused by the wire
resistance. The RTD circuit incorporates a technique which
provides 4-wire accuracy with a 3-wire RTD, and the effect of
wire resistance is eliminated completely.
The voltage drop created by the wire resistance, Rw, is
multiplied by the same gain as the EL8173, and then the
differential input of the A/D Converter (U5) subtracts off the
effect of the wire resistance, Rw.
REFHi - REFLo = IEXT*R1
Iext
Iext
Iext
Rw
Rw
Rw
RTD
PT100
2-WIRE
VOUT
Rw
RTD
PT100
3-WIRE
VOUT
Rw
Rw
VOUT = Iext*(RTD + 2*Rw)
ERROR = Iext*2*Rw
VOUT = Iext*(RTD + Rw)

ERROR = Iext*Rw
FIGURE 47A. 2-WIRE CONNECTION
FIGURE 47B. 3-WIRE CONNECTION
RTD
PT100
4-WIRE
Rw
VOUT
Rw
Rw
VOUT = Iext*RTD
ERROR = 0
FIGURE 47C. 4-WIRE CONNECTION
FIGURE 47.
26
AN1298.2
May 27, 2009

Rs
0.005
1.2V OUTPUT
10A
OUTPUT VOLTAGE
REMOTE SENSE AFTER Rs AT POINT OF LOAD

Ra
FB OR SENSE
POWER SUPPLY CIRCUIT
Rb
3.3V
R1
10k
R2
10k
EL8173
VS+
2 IN-
Ra AND Rb SET THE

OUTPUT VOLTAGE
3 IN+
C1
0.1F
VOUT 6
8 FB+
C2
0.1F
5 FBVS4
GAIN = 50
VOUT = 0V to +2.5V
0.25V/A
Rf
48.7k
Rg
1k
FIGURE 48.
Low Voltage High Side Current

Sense
Due to the rail-to-rail input stage of the EL8173, high side
current sensing is very easy to implement, as shown in
Figure 48.
This circuit is appropriate for any power supply circuit with or
without remote sense capability. The output current is
measured by a current sense resistor, Rs that is scaled for
the desired output voltage and resistor power rating. R1, R2,
C1, and C2 are a simple low pass filter to attenuate the
power supply output ripple and noise. Resistors Rf and Rg
set the gain of the EL8173 for the desired full scale output
voltage.
Rf
V OUT = I OUT R S 1 + ------R
(EQ. 75)
In this circuit, Equation 76 shows a full scale voltage of 2.5V.

1 + 48.7K
V OUT = I OUT 0.005 -------------------------
1K
V OUT = 0.25 I OUT
(EQ. 76)
An accurate output voltage is obtained since remote sense is

used by connecting Ra after the sense resistor, Rs. If remote
sense is not possible, care should be exercised to minimize
the voltage drop across Rs.
The previous circuit uses an external sense resistor to
monitor the output current. If the DC/DC is a buck converter
which uses an internal controller with current mode control,
27
there is often a current sense resistor used to monitor the

inductor current. If this is the case, the output current can be
measured with that current sense resistor since the average
value of the inductor current is equal to the load current in a
buck regulator.
The circuit shown in Figure 49 is an example of using the
current sense resistor, Rs, that is already a part of the current
mode control loop to sense load current. There is a ripple
voltage across Rs that is the inductor ripple current * Rs. The
inductor ripple current is usually 30% to 50% of the load
current and is set by the switching frequency and inductor
value. This ripple voltage is essential for the current mode
control loop, but must be filtered to obtain the output load
current; this filter is performed by R1, R2, C1, and C2. Notice
that even though the input voltage of the DC/DC converter is
+12V, the common mode voltage that is applied to the
EL8173 is the output voltage; in this case, 1.2V. As long as
the output voltage is <5V, the input voltage can be much
higher.
If the inductor current is sensed by using the switching FETs
ON resistance as a current sense element, this method is
not possible with the EL8173 circuit.
The output current can also be sensed by using the
inductors DCR (DC Resistance) as a current sense element
as shown in the following circuit. This example in Figure 50
shows using the EL7566, but this method applies to any
buck mode switching regulator.
AN1298.2
May 27, 2009

VIN = 12V
Q1
TG
CURRENT MODE
PWM CONTROLLER
Rs
0.005
L1
1.2V OUTPUT
10A
Cout
Q2
BG
+IS
-IS
3.3V
R1
10k
R2
10k
EL8173
VS+
2 IN3 IN+
C2
0.1F
C1
0.1F
VOUT 6
8 FB+
VOUT = 0V TO +2.5V
0.25V/A
Rf
48.7k
5 FBVS4
GAIN = 50
Rg
1k
FIGURE 49.
P/O EL7566
LX
+5V
L1
COILCRAFT, DO3316P-272HC
2.7H
DCR = 12m
2.5V OUTPUT
6A
C5
150F
EL7566 DEMO BOARD

+5V
R1
10k
R2
10k
7
VS+
EL8173
2 IN3 IN+
C1
0.1F
C2
0.1F
VOUT 6
VOUT = 0V to +3.0V
0.5V/A
8 FB+
5 FBVS-
Rf
40.2k
GAIN = 41.7
Rg
1k
FIGURE 50.
28
AN1298.2
May 27, 2009

sensing the output current. Due to the high currents, the use
of current sense resistors become very impractical due to
their low values to minimize their power dissipation. For
example, with a 50A output current, the current sense
resistor must be <400 to keep the power dissipation <1W.
In addition, it is very difficult from a PCB layout viewpoint to
break a high current power plane to insert a current sense
resistor, and that forces the plane to neck-down to a very
narrow current flow path.
In the circuit shown in Figure 50, the R1 and C1 filter is

extremely important because it remove the voltage square
wave (swinging between the input voltage and ground) that
is applied to the inductor. The values for R1 and C1 should
be selected to attenuate the signal to a level that is
appropriate for the VOUT noise that is acceptable.
Since the DCR of the inductor is being used as a current sense
resistor, there are several factors which degrade the accuracy
of this approach. First, most inductors are specified for only
maximum DCR; for example, the Coilcraft DO3316P-27HC
shown above is specified for a DCR of 12m, maximum. Actual
lab measurements should the DCR to be 9m. Vishay offers a
product line of inductors with a specified tolerance on the
inductor DCR; for example, IHLP2525CZ-07 product family
guarantees a DCR with 5% tolerance.
High current DC/DC converter outputs now take advantage

of advances in multi-phase DC/DC converters where a
multiple lower current DC/DC conversion stages are
connected in parallel to obtain the necessary high output
current. Rule of thumb operates each phase at 15A to 20A
so that for a 40A output current either 2- or 3-phases can be
operated in parallel.
Second, the inductors internal windings have a temperature

coefficient of +0.393%/C (copper wire) which can be a large
error source if the inductor is allowed to get hot from ambient
temperature or self-heating due to core losses and DCR
power loss. If the error from this source is critical to the
application, a thermistor could be mounted in close proximity
to the inductor and be used to compensate the temperature
coefficient of the copper windings.
With multi-phase DC/DC converters the output current of

each phase can be measured with a current sense resistor
or DCR current sensing. The output from each current sense
circuit is summed together to get the total load current. An
additional feature of this scheme is that the current balance
of each phase can be monitored. The circuit using a
ISL28273 (dual EL8173) current sense circuit is shown in
Figure 51 for a 30A, two phase circuit.
High current (>30A) DC/DC converter outputs for

microprocessor cores present very unique challenges for
VIN = 5V
Q1
L1
0.33H
VOUT = 1.2V AT 30A
Cout
Q2
U1
ISL28273
+5V
16
R1
10k
VS+
6 IN+A OUTA 2
R2
10k
5 IN-A
VIN = 5V
Q3
C1
0.1F
R5
61.9k
FB-A 4
C2
0.1F
L2
0.33H
U2
ISL6568
F = 600kHz
L1, L2:
IHLP-2525CZ-07
5% DCR TOLERANCE
DCR = 3.2m
R9
4.99k
TOTAL Iout
Vout = 0V to +3.0V
100mV/A
R6
1k
FB+A 3
Q4
PHASE 1 Iout
Vout1
200mV/A
R3
10k
11
R4
10k
12 IN-B
C3
0.1F
R10
4.99k
OUTB 15
IN+B
FB-B 13
C4
0.1F
FB+B 14
R7
61.9k
PHASE 2 Iout
Vout2
200mV/A
GAIN = 62.5
R8
1k
VS8
FIGURE 51.
29
AN1298.2
May 27, 2009

The output current of each phase is measured by the DCR
of L1 and L2 as explained in the previous example. VOUT1
and VOUT2 are proportional to the output current of each
phase with a scale factor of 200mV/A. The two outputs,
VOUT1 and VOUT2, are summed together with R9 and R10 to
give a total output current, Total IOUT, with a scale factor of
100mV/A.
This basic scheme can be extended to any number of
phases for extremely high output currents exceeding 100A.
Multiplexed Low Voltage Current

Sense
In a multiple voltage computer power supply, it is often
necessary to monitor the output current from each DC/DC
converter with an A/D Converter. When the EN pin of the
ISL28271 and ISL28272 are enabled (i.e., device shutdown),
the output stage goes into a high impedance state. This
allows multiple VOUT pins to be connected together for
multiplexed output applications. Since the output stage is in
a high impedance state, only one set of feedback resistors
(Rf, Rg) are required if all the amplifiers are operating with
the same gain. Likewise, if different gains are required for
each amplifier, separate feedback resistors can be used to
set a unique gain on each amplifier.
Figure 52 demonstrates the multiplexing scheme for a power
system with four output voltages; 1.2V at 20A, 1.8V at 10A,
3.3V at 4A, and 5.0V at 7.5A.
The dual instrumentation amplifier, ISL28271, is used to
minimize parts count and circuit size. Each power supply
load current is monitored with a low value current sense
resistor (RS1, RS2, RS3, and RS4) to minimize voltage drop
across the resistor. Input protection resistors (R1 to R8) limit
the input fault current to <5mA in case of a short circuit on
the OUT connection.
30
For this application, it is assumed VOUT would be measured

with a microprocessor A/D Converter with a full scale voltage
of 2.5V. Each channel is scaled for an output voltage, VOUT,
equal to 2.0V at maximum load current to provide an
overload measurement capability of 25%.
For each amplifier,
Sensed voltage, Vs = IOUT*Rs
VOUT = Gain*Vs
VOUT = Gain*Rs*IOUT
TABLE 11. SENSED VOLTAGE
VOUT AT
MAX LOAD
CURRENT
(V)
GAIN
EN
IOUT(AMPS)
VOUT
SENSITIVITY
(V/A)
20
0.10
2.0
100
10
0.20
2.0
100
4.0
0.50
2.0
100
7.5
0.27
2.0
134
The gains of the two amplifiers of U1 are both set to 100 by a

single feedback resistor divider network, R9 and R10. The
gains of U2 are different in order to get the same VOUT
sensitivity using standard current sense resistor values.
Gain A is set to 100 by R11 and R12, and Gain B is set to 134
by R13 and R14.
The EN lines (EN1, EN2, EN3, EN4) select the desired
measurement channel.
AN1298.2
May 27, 2009
Rs1 0.001
1.2V IN
1.2V OUT, 20A

Rs2 0.002
1.8V IN
R1
1k
EN1
+5V
16
R3
1k
R2
1k
R4
1k
1.8V OUT, 10A

U1
ISL28271
11
12
VS+
ENA
IN+A
IN-A
IN+B
IN-B
VOUTA
VS-
ENB
FB+A
FB-A
FB+B
FB-B
VOUTB
10
14
VOUT
15
R9
97.6k
13
EN2
GAIN A = GAIN B = 100
R10
1.0k
Rs3 0.005
3.3V IN
3.3V OUT, 4A
Rs4 0.002
5.0V IN
5.0V OUT, 7.5A

R5
1k
EN3
+5V
16
R6
1k
R7
1k
R8
1k
U1
ISL28271
11
12
VS+
ENA
IN+A
IN-A
IN+B
IN-B
VOUTA
VS-
ENB
FB+A
FB-A
FB+B
FB-B
VOUTB
10
14
EN4
13
15
R11
97.6k
R13
133k
R12
1.0k
R14
1.0k
GAIN A = 100
GAIN B = 133.5
FIGURE 52. MEASUREMENT OF POSITIVE AND NEGATIVE CURRENT FLOW
31
AN1298.2
May 27, 2009

LOAD CURRENT = 2A, MAX
X1 AND X2 MUST BE 0V TO +5V
Rs
0.01
X1
X2
R2
4.7k
R1
4.7k
+5V
U1
EL8170
+5V
7 VS+
4 VS-
D1
BAT54S
VOUT 6
2 IN-
VOUT = IOUT + 2
R3
250k
3 IN+
R5
100k
(20mv)
FB+
5
FBR4
1.0k
R6
1.0k
FIGURE 53. CURRENT MONITORED WITH LOW VALUE RESISTOR
Bi-Directional Current Sense
TABLE 12.
The use of the FB pins of the EL8170 make it an ideal choice

for a bi-directional current sense circuit for battery gas
gauging or current monitor in a H-bridge configuration as
shown in the following circuits.
In Figure 53, current is monitored with the use of a low value
resistor Rs. R1, R2, and D1 protect the EL8170 from
overvoltage which would be applied with excessive load
current or a short circuit on the output, X1 or X2. The
amplifier is set for a gain of 100 with R5 and R6. R4 and R5
offset the FB+ pin at 20mV to center 0A at mid-range of the
output voltage VOUT.
LOAD CURRENT (ILOAD)
VOUT
-2A
0.0V
0A
+2.0V
+2A
+4.0V
The range of the measured current can easily be changed

by proper selection of Rs, Gain and FB+ voltage.
The circuit in Figure 54 shows the EL8170 set-up as a
battery gas gauge to monitor both charging current and
discharging current.
In this circuit, when the battery is charging, the current in Rs
will be negative (i.e., flowing from X2 to X1). The EL8170
output voltage will be between 0V and +2V. When the
battery is being discharged, the current flow will be from X1
to X2, and the EL8170 output voltage will be between +2V
and +4V.
Sensed voltage is shown in Equation 77.

V S = I LOAD R S
V OUT = Gain ( V S + V FB+ )
V OUT = Gain ( I LOAD R S + V FB+ )
+5 R 4
V FB+ = --------------------R4 + R5
V OUT = 100 ( I LOAD 0.01 + 0.02 )

V OUT = ( I LOAD + 2 )
(EQ. 77)
32
AN1298.2
May 27, 2009
BATTERY CHARGER, POWER SUPPLY
D3
Rs
0.01
SYSTEM LOAD
X2
X1
D2
+5V
BT1
R1
4.7k
LITHIUM-ION
(4.2V)
R2
4.7k
+5V
U1
EL8170
7 VS+
4 VS-
D1
BAT54S
VOUT 6
2 IN-
VOUT = IOUT + 2
R3
250k
3 IN+
FB+
FB-
R5
100k
8 (20 mv)
5
R4
1.0k
R6
1.0k
FIGURE 54. EL8170 SETUP AS A BATTERY CHARGER
If a more direct measurement for the current polarity and

increased output voltage sensitivity is required, the circuit
shown in Figure 55 can be used.
In Figure 55, U1 is used to measure positive current flow (X1
to X2) and U2 is used to measure negative current flow (X2
to X1). The polarity of the current is detected by U3 which is
being used a zero crossing detect comparator. The EN pins
of the EL8170 (U1, U2) are used to turn on the proper
amplifier depending if the current flow is positive or negative.
In the above circuit, current is monitored with the use of a
low value resistor Rs. R1, R2, and D1 protect the EL8170s
from over-voltage which would be applied with excessive
load current or a short circuit on the output, X1 or X2. When
this bi-directional current sense circuit is used in a PWM
application such as a H-bridge, C1 and C2 can be added to
filter the PWM signal for an average current value.
Figure 56 shows the bi-directional current source circuit

configured to monitor the motor current in a H-bridge circuit.
The direction of the motor (CW, CCW) is monitored by the
polarity bit depending on the direction of current flow in the
motor. The rail-to- rail input capability of the EL8170 allows
current sensing at ground level (Q1 and Q4 ON) or at +5V
(Q3 and Q2 ON). If pulse width modulation is used to control
the speed of the motor, filter capacitors C1 and C2 should be
used to obtain the average value of the motor current. The
value of the capacitors should be selected based on the
PWM frequency and desired overall accuracy.
The amplifiers are set for a gain of 100 with R5 and R6. The
minimum sensed current is set by the EL8170 offset voltage.
V OS
I MIN = -----------RS
0.25mV
I MIN = --------------------0.01
(EQ. 78)
I MIN = 25mA
33
AN1298.2
May 27, 2009

Rs
0.01
X2
X1
R1
4.7k
D1
BAT54S
C1
SEE TEXT
R2
4.7k
+5V
C2
SEE TEXT +5V
U1
ISL28271
7 VS+
ENA 7
4 VS-
VOUTA 2
3 IN+
FB+A 3
2 IN-
FB-A 4
10k
+Iout AMP
+5V
U1
ISL28271
7 VS+
ENB 10
4 VS-
VOUTB 15
3 IN+
FB+B 14
2 IN-
FB-B 13
-Iout AMP
+5V
VOUT
1V/A
R3
100k
R4
1.0k
AV = 100
U2
ISL28271
7 VS+
ENA 7
4 VS-
VOUTA 2
3 IN+
FB+A 3
2 IN-
FBA- 4
+Iout
-Iout
Q1
2N7002
POLARITY DETECT
FIGURE 55. MEASUREMENT OF POSITIVE AND NEGATIVE CURRENT FLOW
34
AN1298.2
May 27, 2009

+5V
Q1
Q3
Rs
0.01
MOTOR
X2
VOUT
X1
POLARITY
VOUT = Imotor
CLOCKWISE = +5V
COUNTER CLOCKWISE = 0V
EL8170 CIRCUIT
Q2
Q4
(GAIN = 100)
FIGURE 56. BI-DIRECTIONAL CURRENT SOURCE CIRCUIT
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
35
AN1298.2
May 27, 2009
MICROCHIP MCP601/2/3/4 OPERATIONAL AMPLIFIER CROSS REFERENCE (AUGUST 2000)

Part #
Co
MCP
Part
#
1-CHANNEL DEVICES
MCP601
MCP
MCP603
MCP
AD8531
AD
601/3
AD8591
ADI
601/3
OPA337
BB
601/3
OPA340
BB
601/3
OPA343A
BB
601/3
OPA353
BB
601/3
ILC7611A-M
HA
601/3
ILC7611B-M
HA
601/3
ILC7611C-M
HA
601/3
ILC7612A-M
HA
601/3
ILC7612B-M
HA
601/3
ILC7612C-M
HA
601/3
ILC7611A-H
HA
601/3
ILC7611B-H
HA
601/3
ILC7611C-H
HA
601/3
ILC7612A-H
HA
601/3
ILC7612B-H
HA
601/3
ILC7612C-H
HA
601/3
LMC6081
NAT 601/3
LMC6081A
NAT 601/3
LMC7101A
NAT 601/3
LMC7101B
NAT 601/3
LMC6681A
NAT 601/3
LMC6681B
NAT 601/3
TLC2201
TI
601/3
TLC2201A
TI
601/3
TLV2270
TI
601/3
TLV2270A
TI
601/3
TLV2271
TI
601/3
TLV2271A
TI
601/3
TLV2460
TI
601/3
TLV2460A
TI
601/3
TLV2461
TI
601/3
TLV2461A
TI
601/3
2-CHANNEL DEVICES
MCP602
MCP
AD8532
AD
602
OP250
AD
602
AD8592
ADI
602
OPA2337
BB
602
OPA2343A
BB
602
OPA2353
BB
602
LMC6022
NAT
602
LMC6032
NAT
602
LMC6035
NAT
602
LMC6082
NAT
602
LMC6082A
NAT
602
LMC6482
NAT
602
LMC6482A
NAT
602
LMC6492A
NAT
602
LMC6492B
NAT
602
LMC662
NAT
602
LMC272
NAT
602
LMC6582A
NAT
602
LMC6582B
NAT
602
LMC6682A
NAT
602
LMC6682B
NAT
602
Drift
Vos
Ib
typ
over temp over temp
+/-uV/C
+/-uV
+/-pA
uV/V
CM
Range
min/maxV
CMRR
+/-uV
Vos
PSR
dB
Aol
25k
dB
Aol
5k
dB
GBWP
(typ)
MHz
SR
(typ)
V/us
DVout+
25k
mV
DVout+
5k
mV
DVout25k
mV
DVout5k
mV
Vn,typ
1kHz
nV/rt Hz
In,typ
1kHz
fA/rtHz
Isc
typ
mA
Vcc+
Min
V
Vcc+
Max
V
uA
2000
2000
25000
25000
3000
500
8000
8000
2000
5000
15000
2000
5000
15000
2000
5000
15000
2000
5000
15000
350
800
3000
7000
1000
3000
500
200
2500
1600
2500
1600
2000
1500
2000
1500
2
2
20
2
2.5
5
10
15
25
10
15
25
10
15
25
10
15
25
1
1
1
1.5
1.5(typ)
1.5
0.5
0.5
2
2
2
2
2
2
2
2
3000
3000
30000
3500
650
8180
10000
3000
7000
20000
3000
7000
20000
3000
7000
20000
3000
7000
20000
900
1300
5000
9000
2500
4500
650
350
2700
1900
2700
1900
2200
1700
2200
1700
60
60
60
60
60
60
600
400
400
400
400
400
400
400
400
400
400
400
400
4
4
100
100
100
100
60
60
60
60
178
178
5623
5623
125
120
200
150
100
100
100
100
100
100
316
316
316
316
316
316
177
177
562
1000
316
562
31.6
31.6
316
316
316
316
100
100
100
100
-0.3/3.8
-0.3/3.8
0/5
0-5
-0.2/3.8
-0.3/4.7
-0.3/4.7
-0.1/5.1
0.8/4.2
0.8/4.2
0.8/4.2
-0.1/5.3
-0.1/5.3
-0.1/5.3
1.3/3.7
1.3/3.7
1.3/3.7
0.5/5.3
0.5/5.3
0.5/5.3
-0.1-2.7
-0.1-2.7
-0.2/5.2
-0.2/5.2
0/5
0/5
0/2.7
0/2.7
0/3.7
0/3.7
0/3.7
0/3.7
-0.2/5.2
-0.2/5.2
-0.2/5.2
-0.2/5.2
75
75
38
38
74
80
74
60
76
70
70
76
70
70
66
60
60
66
60
60
75
75
65
65
70
65
90
90
60
60
60
60
71
71
71
71
100
100
100
103
100
122
86
80
80
86
80
80
100
100
95
95
104
104
92
92
92
92
95
95
84
100
97
92
80
76
76
80
76
76
91
91
88
88
88
88
86
86
86
86
2.8
2.8
3
3
3
5.5
5.5
44
0.48
0.48
0.48
0.48
0.48
0.48
1.4
1.4
1.4
1.4
1.4
1.4
1.3
1.3
1
1
1.2
1.2
1.8
1.8
5.1
5.1
5.1
5.1
4.4
4.4
4.4
4.4
2.3
2.3
5
5
1.2
6
6
22
0.16
0.16
0.16
0.16
0.16
0.16
1.6
1.6
1.6
1.6
1.6
1.6
1.5
1.5
1
1
1.2
1.2
2.5
2.5
10.5
10.5
10.5
10.5
1.8
1.8
1.8
1.8
50
50
125
20
50
50
100
100
100
100
100
100
100
100
100
500
500
100
200
500
500
500
500
500
500
300
300
150
150
300
300
200
200
200
200
100
100
100
100
50
50
125
20
50
50
100
100
100
100
100
100
100
100
100
500
500
100
200
500
500
500
500
500
500
180
180
200
200
50
50
200
200
200
200
100
100
100
100
29
29
45
45
26
25
25
9
100
100
100
100
100
100
100
100
100
100
100
100
22
22
37
37
32
32
8
8
147
147
147
147
11
11
11
11
0.6
0.6
50
50
0.6
3
3
4
10
10
10
10
10
10
10
10
10
10
10
10
0.2
0.2
1.5
1.5
0.5
0.5
0.6
0.6
0.6
0.6
0.6
0.6
0.13
0.13
0.13
0.13
20
20
9
50
50
80
13
13
11
11
100
100
100
100
2.7
2.7
2.5
2.5
2.5
2.5
2.7
2
2
2
2
2
2
2
2
2
2
2
2
4.5
4.5
2.7
15.5
1.8
1.8
4.6
4.6
2.5
2.5
2.5
2.5
2.7
2.7
2.7
2.7
5.5
5.5
6
5.5
5.5
5.5
5.5
10
10
10
10
10
10
10
10
10
10
10
10
15
15
15.5
2.7
10
10
16
16
5.5
5.5
5.5
5.5
6
6
6
6
325
325
1250
1250
1000
950
1250
8000
250
250
250
250
250
250
2500
2500
2500
2500
2500
2500
750
750
850
850
1240
1240
1500
1500
2000
2000
2000
2000
1300
1300
1300
1300
PDIP-8, SO-8
PDIP-8, SO-8
SO-8, SOT-23
SOT-23-5
PDIP, SO-8, SOT-23-8
PCIP, SO-8, SOT23-5
SOT-23, SO-8
SOT23-5, SO-8
PDIP-8, SO-8, TO-99
PDIP-8, SO-8, TO-99
PDIP-8, SO-8, TO-99
PDIP-8, SO-8, TO-99
PDIP-8, SO-8, TO-99
PDIP-8, SO-8, TO-99
PDIP-8, SO-8, TO-99
PDIP-8, SO-8, TO-99
PDIP-8, SO-8, TO-99
PDIP-8, SO-8, TO-99
PDIP-8, SO-8, TO-99
PDIP-8, SO-8, TO-99
PDIP-8, SOIC-8
PDIP-8, SOIC-8
PDIP, SOT-23
PDIP, SOT-23
PDIP, SO-8
PDIP, SO-8
PDIP, SO-8
PDIP, SO-8
PDIP-8, SO-8, MSOP-8
SO-8, SOT23-5
SO-8, SOT23-5
PDIP-8, SO-8, SOT23-6
2000
25000
7500
25000
3000
8000
8000
9000
9000
5000
350
800
3000
750
3000
6000
3000
7000
1000
3000
1000
3000
20
2
5
2.5
2.5
2.5
1
1
1
1
1
1
1.3
3.3
1.5(typ)
1.5
1.5(typ)
1.5
3000
8100
30000
3500
8180
10000
11000
11000
6000
900
1300
3700
1350
3800
6800
3300
9000
1350
3700
2500
4500
60
60
60
60
60
600
200
200
90
4
4
4
4
200
200
4
64
20
20
178
5623
1000
5623
125
200
150
200
200
200
177
177
562
316
562
708
316
562
316
562
316
562
-0.3/3.8
0/5
0/5
0-5
-0.2/3.8
-0.3/4.7
-0.1/5.1
0/3
0/3
0.3/4.2
-0.1-2.7
-0.1-2.7
0/5
0/5
0/5
0/5
0/3
-0.2/3.5
0/5
0/5
0/5
0/5
75
38
45
38
74
74
60
63
63
63
75
75
65
70
65
63
70
65
70
65
70
65
100
100
100
122
99
100
100
95
120
84
100
92
94
106
100
91
91
92(typ)
92(typ)
105
80
60
60
88
88
2.8
3
1
3
3
5.5
44
0.35
1.4
1.4
1.3
1.3
1.5
1.5
1.5
1.5
1.4
2
1.2
1.2
1.2
1.2
2.3
5
2.2
5
1.2
6
22
0.11
1.1
1.5
1.5
1.5
1.3
1.3
1.3
1.3
1.1
2.5
1.2
1.2
1.2
1.2
50
100
125
50
50
600
100
100
100
500
500
200
800
800
300
200
200
200
200
180
150
150
150
150
150
50
100
125
50
50
60
100
100
100
500
500
200
250
250
200
200
200
180
180
150
20
200
200
200
200
29
45
45
45
26
25
9
42
22
27
22
22
37
37
37
37
22
25
30
30
32
32
0.6
50
50
50
0.6
3
4
0.2
0.2
0.2
0.2
0.2
60
60
0.2
1.5
500
500
0.5
0.5
20
100
9
50
80
21
21
8
13
13
11
11
11
11
22
16
6
6
2.7
3
2.5
2.5
2.5
2.7
5
5
5
4.5
4.5
3
3
2.5
2.5
5
2.7
1.8
1.8
1.8
1.8
5.5
5
6
5.5
5.5
5.5
15
15
15
15
15
15.5
15.5
15.5
15.5
15
10
10
10
10
10
325
1250
1250
1250
1000
1250
8000
140
1600
800
750
750
700
700
875
875
650
3200
1240
1240
1240
1240
PDIP-8, SO-8, TSSOP

SO-8, PDIP, TSSOP
SO-8, TSSOP
SOIC-10
PDIP, SO-8, SOT-23-8
SO-8, MSOP-8
SO-8, MSOP-8
PDIP-8, SO-8
PDIP-8, SO-8
SO-8, MSOP-8, BUMP-8
PDIP-8, SOIC-8
PDIP-8, SOIC-8
PDIP, SO-8, CDIP, SSOP
PDIP, SO-8, CDIP, SSOP
PDIP, SO-8
PDIP, SO-8
PDIP-8, SO-8
PDIP-8, SO-8, MSOP
PDIP, SO-8
PDIP, SO-8
PDIP-14, SO-14
PDIP-14, SO-14
* Unless otherwise specified, VDD = 5V, VSS = GND, TA = 25C, VCM = VDD/2
Iq
Package
MICROCHIP MCP601/2/3/4 OPERATIONAL AMPLIFIER CROSS REFERENCE (AUGUST 2000)(CONTINUED)

Part #
Co
MCP
Part
#
Vos
+/-uV
Drift
Vos
Ib
typ
over temp over temp
+/-uV/C
+/-uV
+/-pA
2-CHANNEL DEVICES (CONTINUED)

TLC2262
TI
602
2500
2
TLC2262A
TI
602
950
2
TLC2262C
TI
602
2500
2
TLC27
TI
602
10000
1.7
TLC27A
TI
602
5000
1.7
TLC27B
TI
602
2000
1.7
TLV2721
TI
602
1
TLC2202
TI
602
1000
1
TLC2202A
TI
602
500
TLC2272
TI
602
2500
2
TLC2272A
TI
602
950
2
TLV2272
TI
602
2500
2
TLV2272A
TI
602
1600
2
TLV2273
TI
602
2500
2
TLV2273A
TI
602
1600
2
TLV2462
TI
602
2000
2
TLV2462A
TI
602
1500
2
TLV2463
TI
602
2000
2
TLV2463A
TI
602
1500
2
4-CHANNEL DEVICES
MCP604
MCP
2000
2
AD8534
AD
604
25000
OP450
AD
604
7500
AD8594
ADI
604
25000
20
OPA4343A
BB
604
8000
OPA4353
BB
604
8000
5
LMC6036
NAT
604
5000
2.5
LMC6084
NAT
604
350
1
LMC6084A
NAT
604
800
1
LMC6494A
NAT
604
3000
1
LMC6494B
NAT
604
6000
1
LMC660
NAT
604
3000
1.3
LMC6584A
NAT
604
1000 1.5(typ)
LMC6584B
NAT
604
3000
1.5
LMC6684A
NAT
604
1000 1.5(typ)
LMC6684B
NAT
604
3000
1.5
TLC2264
TI
604
2500
2
TLC2264A
TI
604
950
2
TLC2264C
TI
604
2500
2
TLC2272A
TI
604
950
2
TLC2274
TI
604
2500
2
TLV2274
TI
604
2500
2
TLV2274A
TI
604
1600
2
TLV2275
TI
604
2500
2
TLV2275A
TI
604
1600
2
TLV2464
TI
604
2000
2
TLV2464A
TI
604
1500
2
TLV2465
TI
604
2000
2
TLV2465A
TI
604
1500
2
CM
Range
min/maxV
CMRR
uV/V
PSR
dB
Aol
25k
dB
Aol
5k
dB
GBWP
(typ)
MHz
SR
(typ)
V/us
DVout+
25k
mV
DVout+
5k
mV
DVout25k
mV
DVout5k
mV
Vn,typ
1kHz
nV/rt Hz
In,typ
1kHz
fA/rtHz
Isc
typ
mA
Vcc+
Min
V
Vcc+
Max
V
uA
Iq
Package
3000
1500
3000
13000
9000
3500
3000
150
700
3000
1500
2700
1900
2700
1900
2200
1700
2200
1700
500
500
100
2000
2000
2000
150
150
150
100
100
100
100
60
60
60
60
100
100
100
316
316
316
100
100
100
100
100
316
316
316
316
100
100
100
100
0/4
0/4
0/4
-0.2/4
-0.2/4
-0.2/4
0/4
0/2.7
0/2.7
0/4
0/4
0/3.7
0/3.7
0/3.7
0/3.7
-0.2/5.2
-0.2/5.2
-0.2/5.2
-0.2/5.2
70
70
70
65
65
65
70
75
75
70
70
60
60
60
60
71
71
71
71
98
98
98
88
88
88
104
104
84
84
92
92
92
92
70
88
88
86
86
86
86
0.71
0.71
0.71
0.525
0.525
0.525
0.51
1.9
1.9
2.18
2.18
5.1
5.1
5.1
5.1
4.4
4.4
4.4
4.4
0.55
0.55
0.55
0.43
0.43
0.43
0.25
3.6
3.6
10.5
10.5
10.5
10.5
1.8
1.8
1.8
1.8
150
150
150
1800
1800
1800
250
300
300
150
150
200
200
200
200
100
100
100
100
150
150
150
50
50
50
300
300
300
120
50
50
150
150
200
200
200
200
100
100
100
100
12
12
12
32
32
32
19
8
8
9
9
147
147
147
147
11
11
11
11
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.13
0.13
0.13
0.13
100
100
100
100
4.4
4.4
4.4
4
4
4
2.7
4.6
4.6
4.4
4.4
2.5
2.5
2.5
2.5
2.7
2.7
2.7
2.7
16
16
16
16
16
16
10
16
16
16
16
5.5
5.5
5.5
5.5
6
6
6
6
250
250
250
280
280
280
150
1300
1300
1500
1500
2000
2000
2000
2000
1300
1300
1300
1300
SOIC, PDIP, TSSOP

SOIC, PDIP, TSSOP
SOIC, PDIP, TSSOP
PDIP-8, SO-8
PDIP-8, SO-8
PDIP-8, SO-8
SOT23-5
PDIP, SO-8
PDIP, SO-8
PDIP-8, SO-8
PDIP-14, SO-14, TSSOP-14
3000
8100
30000
8180
10000
6000
900
1300
3800
6800
3300
1350
3700
2500
4500
3000
1500
3000
1500
3000
2700
1900
2700
1900
2200
1700
2200
1700
60
60
60
60
60
600
90
4
4
200
200
4
20
20
500
500
100
150
150
100
100
100
100
60
60
60
60
178
5623
1000
5623
200
150
200
177
177
562
708
316
316
562
316
562
100
100
100
100
100
316
316
316
316
100
100
100
100
-0.3/3.8
0/5
0/5
0-5
-0.3/4.7
-0.1/5.1
0.3/4.2
-0.1-2.7
-0.1-2.7
0/5
0/5
0/3
0/5
0/5
0/5
0/5
0/4
0/4
0/4
0/4
0/4
0/3.7
0/3.7
0/3.7
0/3.7
-0.2/5.2
-0.2/5.2
-0.2/5.2
-0.2/5.2
75
38
45
38
74
60
63
75
75
65
63
70
70
65
70
65
70
70
70
70
70
60
60
60
60
71
71
71
71
100
100
122
100
100
98
98
98
84
84
92
92
92
92
95
120
84
92
100
92(typ)
92(typ)
105
60
60
88
88
86
86
86
86
2.8
3
1
3
5.5
44
1.4
1.3
1.3
1.5
1.5
1.4
1.2
1.2
1.2
1.2
0.71
0.71
0.71
2.18
2.18
5.1
5.1
5.1
5.1
4.4
4.4
4.4
4.4
2.3
5
2.2
5
6
22
1.5
1.5
1.5
1.3
1.3
1.1
1.2
1.2
1.2
1.2
0.55
0.55
0.55
3.6
3.6
10.5
10.5
10.5
10.5
1.8
1.8
1.8
1.8
50
100
50
50
150
150
150
100
100
100
500
200
300
200
200
180
150
150
150
150
150
150
200
200
200
200
100
100
100
100
50
100
50
50
150
150
150
100
100
100
500
200
200
180
180
150
200
200
200
200
300
300
300
150
150
200
200
200
200
100
100
100
100
29
45
45
45
25
9
27
22
22
37
37
22
30
30
32
32
12
12
12
9
9
147
147
147
147
11
11
11
11
0.6
50
50
50
3
4
0.2
0.2
0.2
60
60
0.2
500
500
0.5
0.5
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.13
0.13
0.13
0.13
20
100
50
80
8
13
13
11
11
22
6
6
100
100
100
100
2.7
3
2.5
2.5
2.7
2.7
4.5
4.5
2.5
2.5
5
1.8
1.8
1.8
1.8
4.4
4.4
4.4
4.4
4.4
2.5
2.5
2.5
2.5
2.7
2.7
2.7
2.7
5.5
5
6
5.5
5.5
15
15
15
15.5
15.5
15
10
10
10
10
16
16
16
16
16
5.5
5.5
5.5
5.5
6
6
6
6
325
1250
1250
1250
1250
8000
675
750
750
875
875
550
1240
1240
1240
1240
250
250
250
1500
1500
2000
2000
2000
2000
1300
1300
1300
1300
PDIP-14, SO-14
PDIP-14, SO-14
SO-14
SOIC-16, TSSOP-16
SSOP-16
SSOP-16, SO-14
SO-14, TSSOP
PDIP-14, SOIC-14
PDIP-14, SOIC-14
PDIP-14, SO-14
PDIP-14, SO-14
PDIP-14, SO-14
PDIP-14, SO-14
PDIP-14, SO-14
PDIP-16, SO-16
PDIP-16, SO-16
SOIC-14, PDIP-14, TSSOP-14
PDIP-8, SO-8
MICROCHIP MCP606/7/8/9 OPERATIONAL AMPLIFIER CROSS REFERENCE (AUGUST 2000)

Part #
Co
1-CHANNEL DEVICES
MCP606
MCHP
MCP608
MCHP
AD8541
ADI
OP196G
ADI
LT1636
LTC
LT1782
LTC
LTC1636MS8
LTC
LTC1636N8
LTC
LTC1636S8
LTC
LMC7111B
NAT
LMC7111A
NAT
LMC6061A
NAT
OPA336
BB
OPA336A
BB
OPA241
BB
LMC6041
NAT
LMC6061
NAT
OP193E
ADI
OP193F
ADI
ILC7611A-L
HA
ILC7611B-L
HA
ILC7611C-L
HA
ILC7612A-L
HA
ILC7612B-L
HA
ILC7612C-L
HA
LMC6041A
NAT
MAX4040
MAX
MAX4041
MAX
TLC1078I
TI
2-CHANNEL DEVICES
MCP607
MCHP
AD8542
ADI
LMC6572A
NAT
LMC6572B
NAT
OP296G
ADI
OP296H
ADI
OPA2336
BB
OPA2336A
BB
OPA2241
BB
LMC6462A
NAT
LMC6462B
NAT
LMC6062A
NAT
OP293E
ADI
OP293F
ADI
MAX4042
MAX
MAX4043
MAX
OP290E
ADI
OP290F
ADI
OP290G
ADI
TLC1079I
TI
LMC6062
NAT
4-CHANNEL DEVICES
MCP609
MCHP
AD8544
ADI
LMC6574A
NAT
LMC6574B
NAT
OP496G
ADI
OP496H
ADI
MCP
Part
#
Vos
+/-uV
Ib
over temp
+/-pA
PSRR
Db
CM
Range
min/maxV
CMRR
dB
Aol
25k
dB
Aol
5k
dB
GBWP
(typ)
MHz
SR
(typ)
V/us
DVout+
25k
mV
DVout+
5k
mV
DVout25k
mV
DVout5k
mV
Vn,typ
1kHz
nV/rt Hz
Isc
typ
mA
Vcc+
Min
V
Vcc+
Max
V
uA
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
606/8
250
250
6000
300
225
800
225
225
225
7000
3000
800
125
500
250
6000
350
75
150
2000
5000
15000
2000
5000
15000
3000
1500
1500
450
80
80
100
50000
8000
15000
8000
8000
8000
20
20
4
60
60
25000
4
4
15000
20000
400
400
400
400
400
400
4
20000
20000
2000
80
80
65
85
90
90
90
90
90
60
68
75
80
80
90
62
75
100
97
80
80
80
80
80
80
68
75
75
75
-0.3-3.8
-0.3-3.8
0-5
0-5
0-4
0-18
0-4
0-4
0-4
0/5
0/5
-0.1-2.7
-0.2/4
-0.2/4
0-4.2
0/3
-0.1-2.7
0-4
0-4
0.6/4.4
0.6/4.4
0.6/4.4
-0.3/5.3
-0.3/5.3
-0.3/5.3
0/3
0-5
0-5
-0.2/4
75
75
40
65
84
68
84
84
84
60
70
75
80
80
80
62
75
100
100
76
70
70
76
70
70
68
70
70
70
105
105
86
104
106
103
103
100
100
100
100
98
100
106
106
86
80
80
86
80
80
100
74
74
108
100
100
112
106
106
106
90
90
100
0.155
0.155
1
0.35
0.2
0.2
0.11
0.11
0.11
0.05
0.05
0.1
0.1
0.1
0.035
0.075
0.1
0.035
0.035
0.044
0.044
0.044
0.044
0.044
0.044
0.075
0.09
0.09
0.085
0.08
0.08
0.92
0.3
0.07
0.07
0.07
0.07
0.07
0.027
0.027
35
0.03
0.03
0.01
0.02
35
0.012
0.012
0.016
0.016
0.016
0.016
0.016
0.016
0.02
0.04
0.04
0.035
50
50
150
50
500
500
500
500
100
100
100
130
900
900
100
100
100
100
100
100
80
90
90
1800
100
100
100
700
500
100
100
70
70
200
50
50
70
10
500
500
500
500
100
100
100
130
160
160
100
100
100
100
100
100
80
60
60
25
100
100
100
550
500
100
100
70
70
200
38
38
42
26
52
50
52
52
52
110
110
83
40
40
45
83
83
65
65
100
100
100
100
100
100
83
70
70
17
17
4
25, 50
30
15
15
15
7
7
13
5
5
24, 4
22
13
8
8
22
25
25
2.5
2.5
2.5
3
3
3
2.7
2.7
2.7
5
5
4.5
2.3
2.3
2.7
5
4.5
3
3
2
2
2
2
2
2
5
2.4
2.4
3
5.5
5.5
6
12
30
12.5
44
44
44
15
15
15
5.5
5.5
36
15
15
36
36
10
10
10
10
10
10
15
5.5
5.5
16
25
25
65
60
55
55
55
55
55
50
45
32
32
32
30
26
24
22
22
20
20
20
20
20
20
20
20
20
17
607
607
607
607
607
607
607
607
607
607
607
607
607
607
607
607
607
607
607
607
250
6000
3000
7000
300
800
125
500
250
500
3000
800
100
250
1500
1500
200
300
5000
850
350
80
100
10
10
50000
50000
60
60
25000
200
200
4
15000
20000
20000
20000
2000
4
80
65
67
60
85
85
80
80
90
70
65
75
100
97
75
75
105
105
100
70
75
-0.3-3.8
0-5
0/3.7
0/3.7
0-5
0-5
-0.2/4
-0.2/4
0-4.2
0/5
0/5
-0.1-2.7
0-4
0-4
0-5
0-5
0-4
0-4
0-4
-0.2/4
-0.1-2.7
75
40
63
60
65
65
80
76
80
70
65
75
100
96
70
70
90
80
80
70
75
105
86
114(typ)
114(typ)
104
104
100
90
100
128(typ)
128(typ)
100
106
106
74
74
100
98
97
108
100
100
90
90
100
0.155
1
0.22
0.22
0.35
0.35
0.1
0.1
0.035
0.05
0.05
0.1
0.035
0.035
0.09
0.09
0.02
0.02
0.02
0.085
0.1
0.08
0.92
0.09
0.09
0.3
0.3
0.03
0.03
0.01
35
0.012
0.012
0.04
0.04
0.05
0.05
0.05
0.035
35
50
40
50
150
150
100
100
100
25
50
900
900
90
90
800
800
800
1800
100
100
250
250
700
700
500
500
200
50
40
60
70
70
100
100
100
25
50
160
160
60
60
0.05
0.05
0.05
25
100
100
250
250
550
550
500
500
200
38
42
45
45
26
26
40
40
45
80
80
83
65
65
70
70
83
17
2.5
2.5
4
4
5
5
24, 4
19
19
13
8
8
25
25
13
2.5
2.5
2.7
2.7
3
3
2.3
2.3
2.7
3
3
4.5
3
3
2.4
2.4
3
3
3
3
4.5
5.5
6
11
11
12
12
5.5
5.5
36
5
5
15
36
36
5.5
5.5
30
30
30
16
15
25
65
60
60
60
60
32
32
30
27.5
27.5
23
22
22
20
20
20
20
20
17
16
609
609
609
609
609
250
6000
3000
7000
300
800
80
100
10
10
50000
50000
80
65
67
60
85
85
-0.3-3.8
0-5
0/3.7
0/3.7
0-5
0-4
75
40
63
60
65
65
105
86
114(typ)
114(typ)
104
104
100
0.155
1
0.22
0.22
0.35
0.35
0.08
0.92
0.09
0.09
0.3
0.3
50
20
50
150
150
100
100
150
250
700
700
50
30
60
70
70
100
100
150
250
550
550
38
42
45
45
26
26
17
2.5
2.5
4
4
2.5
2.5
2.7
2.7
3
3
5.5
6
11
11
12
12
25
65
60
60
60
60
Iq
Package

SOIC-8, SOT-23-5
8-PDIP, 8-SO
8-PDIP, 8-SO, 8-MSOP
SOT23-5, SOT23-6
MSSOP-8
PDIP-8
SO-8
PDIP-8, SOIC-8
SOT-23, PDIP, SO-8
SOT-23, PDIP, SO-8
8-PDIP, 8-SO
PDIP-8, SO-8
PDIP-8, SOIC-8
8-PDIP, 8-SO
8-PDIP, 8-SO
PDIP-8, SO-8, TO-99
PDIP-8, SO-8, TO-99
PDIP-8, SO-8, TO-99
PDIP-8, SO-8, TO-99
PDIP-8, SO-8, TO-99
PDIP-8, SO-8, TO-99
PDIP-8, SO-8
8-SO, 8-uMAX, SOT23-5
8-SO, 8-uMAX
PDIP, CDIP, SO-8, PLCC-19
SOIC-8, TSSOP-8
PDIP, SO-8, SSOP
PDIP, SO-8, SSOP
8-PDIP, 8-SO, 8-TSSOP
PDIP, SO-8, MSOP-8
PDIP, SO-8, MSOP-8
8-PDIP, 8-SO
PDIP, SO-8
PDIP, SO-8
PDIP-8, SOIC-8
14-PDIP, 16-SO
8-PDIP, 8-SO
8-SO, 8-uMAX
14-SO, 10-uMAX
8-PDIP, 16-SO, 8-HER, LCC
CDIP-14, SO-14, PLCC-19, PDIP-14
PDIP-8, SOIC-8
SOIC-14, TSSOP-14
PDIP-14, SO-14
PDIP-14, SO-14
MICROCHIP MCP606/7/8/9 OPERATIONAL AMPLIFIER CROSS REFERENCE (AUGUST 2000)(CONTINUED)

4-CHANNEL DEVICES (CONTINUED)
OPA4336A
BB
609
500
OPA4241
BB
609
250
LMC6464A
NAT
609
500
LMC6464B
NAT
609
3000
LMC6064A
NAT
609
800
OP493E
ADI
609
125
OP493F
ADI
609
275
MAX4044
MAX
609
2000
LMC6064
NAT
609
350
LMC6044
NAT
609
6000
LMC6044A
NAT
609
3000
60
25000
200
200
4
15000
20000
20000
4
80
90
70
65
75
100
97
75
75
62
68
-0.2/4
0-4.2
0/5
0/5
-0.1-2.7
0-4
0-4
0-5
-0.1-2.7
-0.1/2.7
-0.1/2.7
80
80
70
65
75
96
96
70
75
62
68
100
100
128(typ)
128(typ)
100
106
106
74
100
94
100
90
100
0.1
0.035
0.05
0.05
0.1
0.035
0.035
0.09
0.1
0.1
0.1
0.03
0.01
35
0.012
0.012
0.04
35
0.01
0.015
100
100
25
50
900
900
90
130
80
70
200
100
100
25
50
160
160
60
130
80
70
200
40
45
80
80
83
65
65
70
83
83
83
5
24, 4
19
19
13
8
8
25
13
13
15
2.3
2.7
3
3
4.5
3
3
2.4
4.5
4.5
4.5
5.5
36
5
5
15
36
36
5.5
15
15.5
15.5
32
30
27.5
27.5
23
22
22
20
19
18.75
16.25
PDIP-14, SSOP-16
14-PDIP, SO-14
PDIP-14, SO-14
PDIP-14, DO-14
PDIP-14, SOIC-14
8-PDIP, 8-SO
14-PDIP, 16-SO
14-SO
PDIP-14, SOIC-14
PDIP-14, SO-14
PDIP-14, SO-14
Microchip Technology Inc. 2355 W. Chandler Blvd. Chandler, AZ 85224-6199 480-792-7200 FAX 480-792-9210 See us on the Web: www.microchip.com
The Microchip name, logo and PIC are registered trademarks of Microchip Technology Inc. in the USA and other countries. All other trademarks mentioned herein are property of their respective companies.
2000, Microchip Technology Inc. All rights reserved. Printed in the USA. 08/00 DS11176B
Application Report
SLOA058 November 2000
A Single-Supply Op-Amp Circuit Collection

Bruce Carter
Op-Amp Applications, High Performance Linear Products
One of the biggest problems for designers of op-amp circuitry arises when the circuit must
be operated from a single supply, rather than 15 V. This application note provides
working circuit examples.
Contents
Introduction ................................................................................................................................... 3
1.1 Split Supply vs Single Supply.................................................................................................... 3
1.2 Virtual Ground........................................................................................................................... 4
1.3 AC-Coupling ............................................................................................................................. 4
1.4 Combining Op-Amp Stages ...................................................................................................... 5
1.5 Selecting Resistor and Capacitor Values .................................................................................. 5
Basic Circuits ................................................................................................................................ 5
2.1 Gain.......................................................................................................................................... 5
2.2 Attenuation ............................................................................................................................... 6
2.3 Summing .................................................................................................................................. 9
2.4 Difference Amplifier .................................................................................................................. 9
2.5 Simulated Inductor.................................................................................................................... 9
2.6 Instrumentation Amplifiers ...................................................................................................... 10
Filter Circuits ............................................................................................................................... 12
3.1 Single Pole Circuits................................................................................................................. 13
3.1.1 Low Pass Filter Circuits .............................................................................................................13
3.1.2 High Pass Filter Circuits.............................................................................................................13
3.1.3 All-Pass Filter ............................................................................................................................14
3.2 Double-Pole Circuits ............................................................................................................... 15

3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
Sallen-Key.................................................................................................................................15
Multiple Feedback (MFB)...........................................................................................................16
Twin T .......................................................................................................................................17
Fliege ........................................................................................................................................20
Akerberg-Mossberg Filter ..........................................................................................................22
BiQuad ......................................................................................................................................24
State Variable............................................................................................................................25
4 References................................................................................................................................... 25
Appendix A Standard Resistor and Capacitor Values ................................................................. 26
1
2
3
4
5
6
Figures
Split Supply (L) vs Single Supply (R) Circuits ..................................................................................3
Single-Supply Operation at Vcc/2....................................................................................................4
AC-Coupled Gain Stages ................................................................................................................6
Traditional Inverting Attenuation With an Op Amp ...........................................................................6
Inverting Attenuation Circuit ............................................................................................................7
Noninverting Attenuation .................................................................................................................8
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7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Inverting Summing Circuit ...............................................................................................................9

Subtracting Circuit...........................................................................................................................9
Simulated Inductor Circuit .............................................................................................................10
Basic Instrumentation-Amplifier Circuit..........................................................................................11
Simulated Instrumentation-Amplifier Circuit...................................................................................11
Instrumentation Circuit With Only Two Op Amps...........................................................................12
Low-Pass Filter Circuits.................................................................................................................13
High-Pass Filter Circuits................................................................................................................14
All-Pass Filter Circuit .....................................................................................................................14
Sallen-Key Low- and High-Pass Filter Topologies.........................................................................16
Multiple-Feedback Topologies.......................................................................................................17
Single Op-Amp Twin-T Filter in Band-Pass Configuration .............................................................18
Single Op-Amp Twin-T Filter in Notch Configuration .....................................................................18
Dual-Op-Amp Twin-T Low-Pass Filter ...........................................................................................19
Dual-Op-Amp Twin-T High-Pass Filter ..........................................................................................19
Dual-Op-Amp Twin-T Notch Filter .................................................................................................20
Low-Pass Fliege Filter...................................................................................................................20
High-Pass Fliege Filter ..................................................................................................................21
Band-Pass Fliege Filter .................................................................................................................21
Notch Fliege Filter .........................................................................................................................22
Akerberg-Mossberg Low-Pass Filter .............................................................................................22
Akerberg-Mossberg High-Pass Filter.............................................................................................23
Akerberg-Mossberg Band-Pass Filter............................................................................................23
Akerberg-Mossberg Notch Filter....................................................................................................24
Biquad Low-Pass and Band-Pass Filter ........................................................................................24
State-Variable Four-Op-Amp Topology .........................................................................................25
Tables
Normalization Factors .....................................................................................................................8
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1 Introduction
There have been many excellent collections of op-amp circuits in the past, but all of them focus
exclusively on split-supply circuits. Many times, the designer who has to operate a circuit from a
single supply does not know how to do the conversion.
Single-supply operation requires a little more care than split-supply circuits. The designer should
read and understand this introductory material.
1.1 Split Supply vs Single Supply

All op amps have two power pins. In most cases, they are labeled VCC+ and VCC-, but sometimes
they are labeled VCC and GND. This is an attempt on the part of the data sheet author to
categorize the part as a split-supply or single-supply part. However, it does not mean that the op
amp has to be operated that way it may or may not be able to operate from different voltage
rails. Consult the data sheet for the op amp, especially the absolute maximum ratings and
voltage-swing specifications, before operating at anything other than the recommended
power-supply voltage(s).
Most analog designers know how to use op amps with a split power supply. As shown in the left
half of Figure 1, a split power supply consists of a positive supply and an equal and opposite
negative supply. The most common values are 15 V, but 12 V and 5 V are also used. The
input and output voltages are referenced to ground, and swing both positive and negative to a
limit of VOM, the maximum peak-output voltage swing.
A single-supply circuit (right side of Figure 1) connects the op-amp power pins to a positive
voltage and ground. The positive voltage is connected to VCC+, and ground is connected to VCCor GND. A virtual ground, halfway between the positive supply voltage and ground, is the
reference for the input and output voltages. The voltage swings above and below this virtual
ground to the limit of VOM. Some newer op amps have different high- and low-voltage rails,
which are specified in data sheets as VOH and VOL, respectively. It is important to note that there
are very few cases when the designer has the liberty to reference the input and output to the
virtual ground. In most cases, the input and output will be referenced to system ground, and the
designer must use decoupling capacitors to isolate the dc potential of the virtual ground from the
input and output (see section 1.3).
+SUPPLY
+SUPPLY
HALF_SUPPLY
-SUPPLY
Figure 1.
Split Supply (L) vs Single Supply (R) Circuits
A common value for single supplies is 5 V, but voltage rails are getting lower, with 3 V and even
lower voltages becoming common. Because of this, single-supply op amps are often rail-to-rail
devices, which avoids losing dynamic range. Rail-to-rail may or may not apply to both the input
and output stages. Be aware that even though a device might be specified as rail-to-rail, some
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specifications can degrade close to the rails. Be sure to consult the data sheet for complete
specifications on both the inputs and outputs. It is the designers obligation to ensure that the
voltage rails of the op amp do not degrade the system specifications.
1.2 Virtual Ground

Single-supply operation requires the generation of a virtual ground, usually at a voltage equal to
Vcc/2. The circuit in Figure 2 can be used to generate Vcc/2, but its performance deteriorates at
low frequencies.
+Vcc
+Vcc
R1
100 k
R2
100 k
Figure 2.
Vcc/2
C1
0.1 F
Single-Supply Operation at VCC/2
R1 and R2 are equal values, selected with power consumption vs allowable noise in mind.
Capacitor C1 forms a low-pass filter to eliminate conducted noise on the voltage rail. Some
applications can omit the buffer op amp.
In what follows, there are a few circuits in which a virtual ground has to be introduced with two
resistors within the circuit because one virtual ground is not suitable. In these instances, the
resistors should be 100 kW or greater; when such a case arises, values are indicated on the
schematic.
1.3 AC-Coupling
A virtual ground is at a dc level above system ground; in effect, a small, local-ground system has
been created within the op-amp stage. However, there is a potential problem: the input source
and output load are probably referenced to system ground, and if the op-amp stage is connected
to a source that is referenced to ground instead of virtual ground, there will be an unacceptable
dc offset. If this happens, the op amp becomes unable to operate on the input signal, because it
must then process signals at and below its input and output rails.
The solution is to ac-couple the signals to and from the op-amp stage. In this way, the input and
output devices can be referenced to ground, and the op-amp circuitry can be referenced to a
virtual ground.
When more than one op-amp stage is used, interstage decoupling capacitors might become
unnecessary if all of the following conditions are met:
The first stage is referenced to virtual ground.
The second stage is referenced to virtual ground.
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There is no gain in either stage. Any dc offset in either stage is multiplied by the gain in
both, and probably takes the circuit out of its normal operating range.
If there is any doubt, assemble a prototype including ac-coupling capacitors, then remove them
one at a time. Unless the input or output are referenced to virtual ground, there must be an
input-decoupling capacitor to decouple the source and an output-decoupling capacitor to
decouple the load. A good troubleshooting technique for ac circuits is to terminate the input and
output, then check the dc voltage at all op-amp inverting and noninverting inputs and at the
op-amp outputs. All dc voltages should be very close to the virtual-ground value. If they are not,
decoupling capacitors are mandatory in the previous stage (or something is wrong with the
circuit).
1.4 Combining Op-Amp Stages

Combining op-amp stages to save money and board space is possible in some cases, but it
often leads to unavoidable interactions between filter response characteristics, offset voltages,
noise, and other circuit characteristics. The designer should always begin by prototyping
separate gain, offset, and filter stages, then combine them if possible after each individual circuit
function has been verified. Unless otherwise specified, filter circuits included in this document
are unity gain.
1.5 Selecting Resistor and Capacitor Values

The designer who is new to analog design often wonders how to select component values.
Should resistors be in the 1- decade or the 1-M decade? Resistor values in the 1-k to
100-k range are good for general-purpose applications. High-speed applications usually use
resistors in the 100- to 1-k decade, and they consume more power. Portable applications
usually use resistors in the 1-M or even 10-M decade, and they are more prone to noise.
Basic formulas for selecting resistor and capacitor values for tuned circuits are given in the
various figures. For filter applications, resistors should be chosen from 1% E-96 values (see
Appendix A). Once the resistor decade range has been selected, choose standard E-12 value
capacitors. Some tuned circuits may require E-24 values, but they should be avoided where
possible. Capacitors with only 5% tolerance should be avoided in critical tuned circuits use 1%
instead.
2 Basic Circuits
2.1 Gain
Gain stages come in two basic varieties: inverting and noninverting. The ac-coupled version is
shown in Figure 3. For ac circuits, inversion means an ac-phase shift of 180. These circuits
work by taking advantage of the coupling capacitor, CIN, to prevent the circuit from having dc
gain. They have ac gain only. If CIN is omitted in a dc system, dc gain must be taken into
account.
It is very important not to violate the bandwidth limit of the op amp at the highest frequency seen
by the circuit. Practical circuits can include gains of 100 (40 dB), but higher gains could cause
the circuit to oscillate unless special care is taken during PC board layout. It is better to cascade
two or more equal-gain stages than to attempt high gain in a single stage.
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R2
INVERTING
+Vcc
Gain = R2/R1
R3 = R1||R2
for minimum error due
to input bias current
Cin
R1
Vin
Vout
+
R3
Vcc/2
+Vcc
NONINVERTING
Cin
Gain = 1 + R2/R1
Input Impedance = R1||R2
Vin
+
-
Vout

R2
R1
Vcc/2
Figure 3.
AC-Coupled Gain Stages
2.2 Attenuation
The traditional way of doing inverting attenuation with an op-amp circuit is shown in Figure 4, in
R2
INVERTING
+Vcc
Gain = R2/R1
R3 = R1||R2
Cin
R1
Vin
Vout
R3
Vcc/2
Figure 4.
Traditional Inverting Attenuation With an Op Amp
which R2 < R1. This method is not recommended, because many op amps are unstable at gains
of less than unity. The correct way to construct an attenuation circuit1 is shown in Figure 5.
This circuit is taken from the design notes of William Ezell
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Rf
INVERTING
+Vcc
Component values
normalized to unity
Cin
RinA 1
RinB 1
Vin
Vout
R3
Vcc/2
Figure 5.
Inverting Attenuation Circuit
A set of normalized values of the resistor R3 for various levels of attenuation is shown in
Table 1. For nontablated attenuation values, the resistance is:
R3 =
VO V IN
2 2(VO V IN )
To work with normalized values, do the following:
Select a base-value of resistance, usually between 1 kW
Divide Rin in two for RinA and RinB.
Multiply the base value for Rf and Rin by 1 or 2, as shown in Figure 5.
Look up the normalization factor for R3 in the table below, and multiply it by the base-value
of resistance.
and 100 kW
for Rf and Rin.
For example, if Rf is 20 k, RinA and RinB are each 10 k, and a 3-dB attenuator would use a
12.1-k resistor.
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Table 1.
Normalization Factors
DB Pad
Vout/Vin
0
0.5
1
2
2
3.01
3.52
4
5
6
6.02
7
8
9
9.54
10
12
12.04
13.98
15
15.56
16.90
18
18.06
19.08
20
25
30
40
50
60
1.0000
0.9441
0.8913
0.7943
0.7079
0.7071
0.6667
0.6310
0.5623
0.5012
0.5000
0.4467
0.3981
0.3548
0.3333
0.3162
0.2512
0.2500
0.2000
0.1778
0.1667
0.1429
0.1259
0.1250
0.1111
0.1000
0.0562
0.0316
0.0100
0.0032
0.0010
R3
8.4383
4.0977
0.9311
1.2120
1.2071
1.000
0.8549
0.6424
0.5024
0.5000
0.4036
0.3307
0.2750
0.2500
0.2312
0.1677
0.1667
0.1250
0.1081
0.1000
0.08333
0.07201
0.07143
0.06250
0.05556
0.02979
0.01633
0.005051
0.001586
0.0005005
Noninverting attenuation can be performed with a voltage divider and a noninverting buffer as
shown in Figure 6.
NONINVERTING
+Vcc
Component values
normalized to unity
Cin
R1
Vin
+
R2
Vcc/2
Figure 6.
Noninverting Attenuation
Vout
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2.3 Summing
An inverting summing circuit (Figure 7) is the basis of an audio mixer. A single-supply voltage is
seldom used for real audio mixers. Designers will often push an op amp up to, and sometimes
beyond, its recommended voltage rails to increase dynamic range.
Noninverting summing circuits are possible, but not recommended. The source impedance
becomes part of the gain calculation.
INVERTING
Cin1
R1A
Cin2
R1B
CIin3
R1C
R2
Vin1
Vout = R2(Vin1/R1 + Vin2/R2 +

Vin3/R3)
= R1A||R1B||R1C||R2
+Vcc
Vin2
Vin3
Vout
+
R3
Vcc/2
Figure 7.
Inverting Summing Circuit
2.4 Difference Amplifier

Just as there are summing circuits, there are also subtracting circuits (Figure 8). A common
application is to eliminate the vocal track (recorded at equal levels in both channels) from stereo
recordings.
R2
For R1 = R3 and R2 = R4:

Vout = (R2/R1)(Vin2 Vin1)
R1||R2 = R3||R4
Vin1
+Vcc
Cin1
R1
+
Vin2
Cin2
Vout
R3
R4
Vcc/2
Figure 8.
Subtracting Circuit
2.5 Simulated Inductor

The circuit in Figure 9 reverses the operation of a capacitor, thus making a simulated inductor.
An inductor resists any change in its current, so when a dc voltage is applied to an inductance,
the current rises slowly, and the voltage falls as the external resistance becomes more
significant.
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+Vcc
L = R1*R2*C1
C1
Vin1
+
R2
Vout
Vcc/2
R1
Figure 9.
Simulated Inductor Circuit
An inductor passes low frequencies more readily than high frequencies, the opposite of a
capacitor. An ideal inductor has zero resistance. It passes dc without limitation, but it has infinite
impedance at infinite frequency.
If a dc voltage is suddenly applied to the inverting input through resistor R1, the op amp ignores
the sudden load because the change is also coupled directly to the noninverting input via C1.
The op amp represents high impedance, just as an inductor does.
As C1 charges through R2, the voltage across R2 falls, so the op-amp draws current from the
input through R1. This continues as the capacitor charges, and eventually the op-amp has an
input and output close to virtual ground (Vcc/2).
When C1 is fully charged, resistor R1 limits the current flow, and this appears as a series
resistance within the simulated inductor. This series resistance limits the Q of the inductor. Real
inductors generally have much less resistance than the simulated variety.
There are some limitations of a simulated inductor:
One end of the inductor is connected to virtual ground.
The simulated inductor cannot be made with high Q, due to the series resistor R1.
It does not have the same energy storage as a real inductor. The collapse of the magnetic
field in a real inductor causes large voltage spikes of opposite polarity. The simulated
inductor is limited to the voltage swing of the op amp, so the flyback pulse is limited to the
voltage swing.
2.6 Instrumentation Amplifiers

Instrumentation amplifiers are used whenever dc gain is needed on a low-level signal that would
be loaded by conventional differential-amplifier topologies. Instrumentation amplifiers take
advantage of the high input impedance of noninverting op-amp inputs.
The basic instrumentation amplifier topology is shown in Figure 10.
10
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+Vcc
Vin-
R1
R2
+Vcc
R5
ASSUMES Vin- AND Vin+

REFERENCED TO Vcc/2
-
R7
R1 = R3 (matched)
R2 = R4 (matched)
R5 = R6
Gain = R2/R1 (1 + 2R5/R7)
Vout
+Vcc
R6
Vin+
R3
+
R4
Vcc/2
Figure 10. Basic Instrumentation-Amplifier Circuit

This circuit, and the other instrumentation amplifier topologies presented here, assume that the
inputs are already referenced to half-supply. This is the case with strain gauges that are
operated from Vcc. The basic disadvantage of this circuit is that it requires matched resistors;
otherwise, it would suffer from poor CMRR (see for example, Op Amps for Everyone[3]).
The circuit in Figure 10 can be simplified by eliminating three resistors, as shown in Figure 11.
+Vcc
Vin-
R1
R2
+Vcc

REFERENCED TO Vcc/2
-
R1 = R3 (matched)
R2 = R4 (matched)
Gain = R2/R1
Vout
+Vcc
Vin+
R3
+
R4
Vcc/2
Figure 11. Modified Instrumentation-Amplifier Circuit
11
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Here, the gain is easier to calculate, but a disadvantage is that now two resistors must be
changed instead of one, and they must be matched resistors. Another disadvantage is that the
first stage(s) cannot be used for gain.
An instrumentation amplifier can also be made from two op amps; this is shown in Figure 12.
R1

REFERENCED TO Vcc/2
R2
Vcc/2
R1 = R4 (matched)
R2 = R3 (matched)
Gain = 1 + R1/R2
Vin -
R3
R4
+Vcc
+Vcc
Vout
Vin+
Figure 12. Instrumentation Circuit With Only Two Op Amps

However, this topology is not recommended because the first op amp is operated at less than
unity gain, so it may be unstable. Furthermore, the signal from Vin- has more propagation delay
than Vin+.
3 Filter Circuits
This section is devoted to op-amp active filters. In many cases, it is necessary to block dc
voltage from the virtual ground of the op-amp stage by adding a capacitor to the input of the
circuit. This capacitor forms a high-pass filter with the input so, in a sense, all these circuits have
a high-pass characteristic. The designer must insure that the input capacitor is at least 100 times
the value of the other capacitors in the circuit, so that the high-pass characteristic does not come
into play at the frequencies of interest in the circuit. For filter circuits with gain, 1000 times might
be better. If the input voltage already contains a Vcc/2 offset, the capacitor can be omitted.
These circuits will have a half-supply dc offset at their output. If the circuit is the last stage in the
system, an output-coupling capacitor may also be required.
There are trade-offs involved in filter design. The most desirable situation is to implement a filter
with a single op amp. Ideally, the filter would be simple to implement, and the designer would
have complete control over:
12
The filter corner / center frequency
The gain of the filter circuit
The Q of band-pass and notch filters, or style of low-pass and high-pass filter (Butterworth,
Chebyshev, or Bessell).
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Unfortunately, such is not the case complete control over the filter is seldom possible with a
single op amp. If control is possible, it frequently involves complex interactions between passive
components, and this means complex mathematical calculations that intimidate many designers.
More control usually means more op amps, which may be acceptable in designs that will not be
produced in large volumes, or that may be subject to several changes before the design is
finalized. If the designer needs to implement a filter with as few components as possible, there
will be no choice but to resort to traditional filter-design techniques and perform the necessary
calculations.
3.1
Single Pole Circuits

Single-pole circuits are the simplest filter circuits. They have a roll off of 20 dB per decade.
3.1.1 Low Pass Filter Circuits

Typical low-pass filter circuits are shown in Figure 13.
C1
R2
INVERTING
Fo = 1/(2pR2C1)
Gain = R2/R1
+Vcc
Cin
R1
Vin
Vout
Vcc/2
+Vcc
Cin
R1
Vin
+
Vout
NONINVERTING
Fo = 1/(2pR1C1)
Gain = 1 + R3/R2
C1
R3
R2
Vcc/2
Figure 13. Low-Pass Filter Circuits
3.1.2 High Pass Filter Circuits

Typical high-pass filter circuits are shown in Figure 14.
13
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+Vcc
C1
Vin
NONINVERTING
Vout
R1
Gain = 1
Fo = 1/(2pR1C1)
Vcc/2
+Vcc
C1
Vin
+
Vout
NONINVERTING
Fo = 1/(2pR1C1)
Gain = 1 + R3/R2
R3
R1
R2
Vcc/2
Figure 14. High-Pass Filter Circuits
3.1.3 All-Pass Filter

The all-pass filter passes all frequencies at the same gain. It is used to change the phase of the
signal, and it can also be used as a phase-correction circuit. The circuit shown in Figure 15 has
a 90phase shift at F(90). At dc, the phase shift is 0, and at high frequencies it is 180.
+Vcc
C1
Vin1
R1 = R2 = R3 = R
F(90) = 1/(2pR*C1)
R2
Vout
Vcc/2
R1
Figure 15. All-Pass Filter Circuit
14
R3
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3.2 Double-Pole Circuits

Double-pole op-amp circuit topologies are sometimes named after their inventor. Several
implementations or topologies exist. Some double-pole circuit topologies are available in a
low-pass, high-pass, band-pass, and notch configuration. Others are not. Not all topologies and
implementations are given here: only the ones that are easy to implement and tune.
Double-pole or second-order filters have a 40-dB-per-decade roll-off.
Commonly the same component(s) adjust the Q for the band-pass and notch versions of the
topology, and they change the filter from Butterworth to Chebyshev, etc. for low-pass and highpass versions of the topology. Be aware that the corner frequency calculation is only valid for the
Butterworth versions of the topologies. Chebyshev and Bessell modify it slightly.
When band-pass and notch filter circuits are shown, they are high-Q (single frequency) types. To
implement a wider band-pass or notch (band-reject) filter, cascade low-pass and high-pass
stages. The pass characteristics should overlap for a band-pass and not overlap for a
band-reject filter.
Inverse Chebyshev and Elliptic filters are not shown. These are beyond the scope of a circuit
collection note.
Not all filter topologies produce ideal results the final attenuation in the rejection band, for
example, is greater in the multiple-feedback filter configuration than it is in the Sallen-Key filter.
These fine points are beyond the scope of an op-amp circuit collection. Consult a textbook on
filter design for the merits and drawbacks of each of these topologies. Unless the application is
particularly critical, all the circuits shown here should produce acceptable results.
3.2.1 Sallen-Key
The Sallen-Key topology is one of the most widely-known and popular second-order topologies.
It is low cost, requiring only a single op amp and four passive components to accomplish the
tuning. Tuning is easy, but changing the style of filter from Butterworth to Chebyshev is not. The
designer is encouraged to read references [1] and [2] for a detailed description of this topology.
The circuits shown are unity gain changing the gain of a Sallen-Key circuit also changes the
filter tuning and the style. It is easiest to implement a Sallen-Key filter as a unity gain
Butterworth.
15
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+Vcc
+Vcc
LOW PASS
C1
R3
Unity Gain
Butterworth
Vin
R3 = R4 (HIGH)
R1 = R2
C1 = 2C2
Fo = 2 / (4pR1C2)
Cin
R1
R2
+
-
C2
Vout
R4
R1
HIGH PASS
Unity Gain
Butterworth
Vin
C1 = C2
R1 = R
R = 2R1
Fo = 2 / (4pR1C1)
C1
+Vcc
C2
+
-
Vout
R2
Vcc/2
Figure 16. Sallen-Key Low- and High-Pass Filter Topologies
3.2.2 Multiple Feedback (MFB)

MFB topology is very versatile, low cost, and easy to implement. Unfortunately, calculations are
somewhat complex, and certainly beyond the scope of this circuit collection. The designer is
encouraged to read reference [1] for a detailed description of the MFB topology. If all that is
needed is a unity gain Butterworth, then these circuits will provide a close approximation.
16
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+Vcc
LOW PASS
C1
R2
Unity Gain Butterworth

Fo = 1/(2RC)
R1 = R2 = R/2
R3 = R/(22)
C1 = C
C2 = 4C
Cin
R1
R3
Vin
Vout
C2
Vcc/2
+Vcc
HIGH PASS
C2
Unity Gain Butterworth

Fo = 1/(2RC)
R1 = 0.47R
R2 = 2.1R
C1 = C2 = C3 = C
R2
C1
Vin
C3
Vout
R1
Vcc/2
+Vcc
C1
BAND PASS
Gain = 2.3 dB
Fo = 1/(2.32RC)
R1 = 10R
R2 = 0.001R
R3 = 100R
C1 = 10C
C2 = C
R3
Cin
R1
Vin
C2
Vout
R2
Vcc/2
Figure 17. Multiple-Feedback Topologies
3.2.3 Twin T
The twin-T topology uses either one or two op amps. It is based on a passive (RC) topology that
uses three resistors and three capacitors. Matching these six passive components is critical;
fortunately, it is also easy. The entire network can be constructed from a single value of
resistance and a single value of capacitance, running them in parallel to create R3 and C3 in the
twin-T schematics shown in Figure. Components from the same batch are likely to have very
similar characteristics.
17
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3.2.3.1 Single Op-Amp Implementations

R1
R2
C3
Vcc/2
BAND PASS
R3
C1
R1 = R2 = R
C1 = C2 = C
R3 = R/2
C3 = 2C
Fo = 1/(2pRC)
Cin
C2
+Vcc
Vin
R4
Gain controlled by R4 and R5

R4 > 100 * R5
Q hard to control; need mismatched
Resistors; also affects gain
Vout
R5
Vcc/2
Figure 18. Single Op-Amp Twin-T Filter in Band-Pass Configuration

The bandpass circuit will oscillate if the components are matched too closely. It is best to
de-tune it slightly, by selecting the resistor to virtual ground to be one E-96 1% resistor value off,
for instance.
+Vcc
C1
NOTCH
C1 = C2 = C
C3 = 2C
R1 = R2 = R
R3 = R/2
Fo = 1/(2pRC)
C2
+Vcc
R4
R3
Cin
Vin
R4 = R5: HIGH
The only control over Q
is by mismatching R3
Vcc/2
+
C3
R5
R1
R2
Figure 19. Single Op-Amp Twin-T Filter in Notch Configuration
18
Vout
SLOA058
3.2.3.2 Dual-Op-Amp Implementations

Typical dual op-amp implementations are shown in Figures 20 to 22
LOW PASS
+Vcc
R1 = R2 = R
C1 = C2 = C
R3 = R/2
C3 = 2C
Fo = 1/(2pRC)
+Vcc
R6
Cin
R1
R2
Vin
Vout
R7
Unity Gain
R4 < R5/2 Chebyshev
R4 = R5/2 Butterworth
R4 > R5/2 Bessel
C3
+Vcc
R6 = R7: HIGH
R3
R4
C1
C2
Vcc/2
R5
Vcc/2
Figure 20. Dual-Op-Amp Twin-T Low-Pass Filter

+Vcc
HIGH PASS
R1
R1 = R2 = R
C1 = C2 = C
R3 = R/2
C3 = 2C
Fo = 1/(2pRC)
R2
Vout
Vcc/2
C3
Unity Gain
R4 < R5/2 Chebyshev
R4 = R5/2 Butterworth
R4 > R5/2 Bessel
+Vcc
R3
R4
C1
Vin
C2
R5
Vcc/2
Figure 21. Dual-Op-Amp Twin-T High-Pass Filter
19
SLOA058
+Vcc
+Vcc
NOTCH
R6
R1 = R2 = R
Vin
C1 = C2 = C
R3 = R/2
C3 = 2C
Fo = 1/(2pRC)
R6 = R7 > 20*R
CIN
R1
R2
Vout
+
C3
R7
+Vcc
Q controlled by
ratio of R5 and R4
R4 = 0.05*R5: high Q
R4 = 0.5*R5 low: Q
R3
C1
R4
C2
R5
Vcc/2
Figure 22. Dual-Op-Amp Twin-T Notch Filter
3.2.4 Fliege
Fliege is a two-op-amp topology (Figures 2326), and therefore more expensive than one-opamp topologies. There is good control over the tuning and the Q and style of filter. The gain is
fixed at two for low-pass, high-pass, and band-pass filters, and unity for notch.
+Vcc
Cin
R2
Vin
LOW PASS
R2 = R3 = R
C1 = C2 = C
R4 = R5, not critical
Fo = 1/(2pRC)
Gain fixed at 2
R1 = R/2 Butterworth
R1 > R/2 Chebyshev
R1 < R/2 Bessel
R1
R3
C2
+Vcc
R4
+
R5
Vcc/2
Figure 23. Low-Pass Fliege Filter
20
Vout
C1
SLOA058
+Vcc
C1
Vin
+
Vout
HIGH PASS
R1
R2 = R3 = R
C1 = C2 = C
Fo = 1/(2pRC)
R2
C2
Vcc/2
R3
+Vcc
Gain fixed at 2
R1 > R/2 Chebyshev
R1 < R/2 Bessel
R4
R5
Vcc/2
Figure 24. High-Pass Fliege Filter

+Vcc
Cin
R1
Vin
BAND PASS
Vout
Gain fixed at 2
R1 controls Q
low R1 => low Q
high R1 => high Q
R1 should be > R/5
R2 = R3 = R
C1 = C2 = C
Fo = 1/(2pRC)
C1
R2
C2
Vcc/2
R3
+Vcc
R4
R5
Vcc/2
Figure 25. Band-Pass Fliege Filter
21
SLOA058
+Vcc
Cin
C1
Vin
NOTCH
+
Vout
R1
R3 = R4 = R5 = R6 = R
C1 = C2 = C
Fo = 1/(2pRC)
R1 = R2 = R*10/2
No control over Q
Gain fixed at 1
R2
R3
C2
Vcc/2
R4
R6
+Vcc
R5
Figure 26. Notch Fliege Filter
3.2.5 Akerberg-Mossberg Filter

This is the easiest of the three-op-amp topologies to use (Figures 2730). It is easy to change
the gain, style of low-pass and high-pass filter, and the Q of band-pass and notch filters. The
notch filter performance is not as good as that of the twin T notch, but it is less critical.
R5
LOW PASS
R2 = R3 = R4 = R5 = R
C1 = C2 = C
Fo = 1/(2pRC)
+Vcc
R2
R6
C1
Unity Gain: R = R1
Other Gain: R/R1
C2
+
+Vcc
+Vcc
Vcc/2
Cin
R3
R1
Vin
+
-
R6 > R/2 Chebyshev
R6 < R/2 Bessel
Vcc/2
R4
+
Vcc/2
Figure 27. Akerberg-Mossberg Low-Pass Filter
22
Vout
SLOA058
R5
HIGH PASS
Vcc/2
R2=R3=R4=R5=R
C2=C3=C
Fo=1/(2pRC)
+Vcc
R2
R1
R6
C2
R6 > R/2 Chebyshev
R6 < R/2 Bessel
C3
+
+Vcc
+Vcc
R3
Vcc/2
Unity Gain:
C1=C, R1=R
Other Gain:
R1/R AND C1/C
R4
+
+
C1
Vcc/2
Vout
Vcc/2
Vin
Figure 28. Akerberg-Mossberg High-Pass Filter
BAND PASS
R5
R2 = R3 = R4 = R5 = R
C1 = C2 = C
Fo = 1/(2pRC)
Unity Gain:
R1 = R6
Other Gain:
R6/R1
+Vcc
R2
R6
C1
C2
+
+Vcc
+Vcc
R3
Vcc/2
R1, R6 also control Q

low values, low Q
high values, high Q
R4
Vcc/2
Vout
Vcc/2
Cin
R1
Vin
Figure 29. Akerberg-Mossberg Band-Pass Filter
23
SLOA058
R5
NOTCH
Vcc/2
R1=R2=R3=R4=R5=R6=R
C1 = C2 = C3 = C
Fo = 1/(2RC)
+Vcc
R6
R2
R7
C1
R/2 < R7 < 2 x R

R7 controls Q
low value, low Q
high value, high Q
C2
+
+Vcc
+Vcc
R3
Vcc/2
R4
R1
Vout
Vcc/2
Vcc/2
Cin
C3
Vin
Figure 30. Akerberg-Mossberg Notch Filter
3.2.6 BiQuad
Biquad is a well know topology (Figure 31). It is only available in low-pass and band-pass
varieties. The low-pass filter is useful whenever simultaneous normal and inverted outputs are
needed.
R4
R1
C1
C2
+Vcc
Cin
+Vcc
+Vcc
R3
Vin
R6
R2
R5
VBPout
V+LPout
Vcc/2
LOW PASS
BAND PASS
R1 = R2 = R
R4 = R/2
C1 = C2 = C
Fo = 1/(2pRC)
R1 = R2 = R5 = R
R6 = about R/2, not critical
C1 = C2 = C
Fo = 1/(2pRC)
R4 > R/2 Chebyshev
R4 < R/2 Bessell
Unity Gain: R3 = R
Other Gain: R/R3
R3 = R4 unity gain
Gain = R4/R3
R4 also controls Q
low value, low Q
high value, high Q
Figure 31. Biquad Low-Pass and Band-Pass Filter
24
VLPout
SLOA058
3.2.7 State Variable

State variable is a three to four op-amp topology. The fourth op-amp is only required for notch
filters. It is also very easy to tune, and it is easy to change the style of lowpass and highpass,
and easy to change the Q of the bandpass and notch. Unfortunately, it is not as nice a topology
as Akerberg-Mossberg. The same resistor is used for gain and style of filter / Q, limiting control
of the filter. There is probably not a lot of reason to use this topology, unless simultaneous
lowpass, highpass, bandpass, and notch outputs are required by the application.
R5
C1
R2
R10
+Vcc
Cin
C2
+Vcc
R1
+Vcc
R3
Vin
+Vcc
R4
R8
Vcc/2
Vcc/2
Vcc/2
R9
R7
R6
Vcc/2
HPout
R1=R2=R3=R4=R5=R6=R8=R9=R10=R
C1 = C2 = C
Fo = 1/(2RC)
BPout
Unity Gain: R7 = R
Other Gain: R7/R
BP and NOTCH
R7 high value, high Q
R7 low value, low Q
NOTCH
LPout
LP and HP
R7 > R/2 Chebyshev
R7 < R/2 Bessel
R8, R9 ,R10 and 4th

op amp only used
for notch
Figure 32. State-Variable Four-Op-Amp Topology
4 References
1.
Active Low Pass Filter Design, Texas Instruments Application Report, Literature Number
SLOA049
2.
Analysis Of The Sallen-Key Architecture, Texas Instruments Application Report,

Literature Number SLOA024A.
3.
Op Amps for Everyone, Ron Mancini (Ed.), Chapter 12, Texas Instruments Literature
Number SLOD006
25
SLOA058
Appendix A Standard Resistor and Capacitor Values

E-12 Resistor / Capacitor Values
1.0, 1.2, 1.5, 1.8, 2.2, 2.7, 3.3, 3.9, 4.7, 5.6, 6.8, and 8.2; multiplied by the decade value.

1.0, 1.1, 1.2, 1.3, 1.5, 1.6, 1.8, 2.0, 2.2, 2.4, 2.7, 3.0, 3.3, 3.6, 3.9, 4.3, 4.7, 5.1, 5.6, 6.2, 6.8, 7.5,
8.2, and 9.1; multiplied by the decade value.

1.00, 1.02, 1.05, 1.07, 1.10, 1.13, 1.15, 1.18, 1.21, 1.24, 1.27, 1.30, 1.33, 1.37, 1.40, 1.43, 1.47,
1.50, 1.54, 1.58, 1.62, 1.65, 1.69, 1.74, 1.78, 1.82, 1.87, 1.91, 1.96, 2.00, 2.05, 2.10, 2.15, 2.21,
2.26, 2.32, 2.37, 2.43, 2.49, 2.55, 2.61, 2.67, 2.74, 2.80, 2.87, 2.94, 3.01, 3.09, 3.16, 3,24, 3.32,
3.40, 3,48, 3.57, 3.65, 3.74, 3.83, 3.92, 4.02, 4.12, 4.22, 4,32, 4.42, 4,53, 4.64, 4.75, 4.87, 4.99,
5.11, 5.23, 5.36, 5.49, 5.62, 5.76, 5.90, 6.04, 6.19, 6.34, 6.49, 6.65, 6.81, 6.98, 7.15, 7.32, 7.50,
7.68, 7.87, 8.06, 8.25, 8.45, 8.66, 8.87, 9.09, 9.31, 9.53, 9.76; multiplied by the decade value.
26
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to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customers applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
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LM101,LM103

AN-32 FET Circuit Applications

Literature Number: SNOA620

FET Circuit Applications

FET Circuit Applications

Sample and Hold With Offset Adjustment

Long Time Comparator

JFET AC Coupled Integrator

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C1995 National Semiconductor Corporation

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This FETVM replaces the function ot the VTVM while at the

HI-FI Tone Control Circuit (High Z Input)

amp-operated feedback type tone control circuit.

Differential Analog Switch

(b25 to a 125 C), this makes it an unusual but ideal choice

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This preamplifier provides proper loading to a reluctance

Negative to Positive Supply Logic Level Shifter

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Ultra-High Gain Audio Amplifier

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FET Nixie* Drivers

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JFET-Bipolar Cascode Circuit

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and Q2 IGSS (k100 pA) as the only discharge paths. Q2

Wein Bridge Sine Wave Oscillator

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High Impedance Low Capacitance Wideband Buffer

High Impedance Low Capacitance Amplifier

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Stable Low Frequency Crystal Oscillator

This Colpitts-Crystal oscillator is ideal for low frequency

0 to 360 Phase Shifter

DTL-TTL Controlled Buffered Analog Switch

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L2 e 10T */8 DIA */4 LONG

20 MHz OSCILLATOR PERFORMANCE

Low Distortion Oscillator

is excellent when a low harmonic content is required for a

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The FM3954 monolithic-dual provides an ideal low-offset,

High Toggle Rate High Frequency Analog Switch

This commutator circuit provides low impedance gate drive

This 4-channel commutator uses the 2N4091 to achieve low

voltage accurately reflects the power supply current flow.

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