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Design of Reflectionless Vias Using Neural

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IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 31, NO. 1, FEBRUARY 2008

211

Design of Reflectionless Vias Using Neural

Network-Based Approach
Ku-Teng Hsu, Wei-Da Guo, Guang-Hwa Shiue, Chien-Min Lin, Member, IEEE,
Tian-Wei Huang, Senior Member, IEEE, and Ruey-Beei Wu, Senior Member, IEEE

AbstractAs the data rate is significantly increased, the effect of

via discontinuity on the signal integrity of printed circuit boards
has become more prominent and nonnegligible. In this paper, the
artificial neural network approach to efficient design of reflectionless via structures with single-ended interconnections is presented.
Full-wave analysis is employed to characterize the via structures,
from which the empirical representation is derived using a neural
network method with the physical parameters as inputs and the
electrical characterization as the output. With the accurate and
fast neural network models of desired via structures, one can
rapidly determine the solution space of the feasible geometries
with minimized reflection noise. The proposed approach is finally
validated by the time-domain simulation results and time-domain
reflection experiments.
Index TermsArtificial neural network (ANN), geometric design rules, reflection noise, sensitivity, signal integrity, time-domain
reflection (TDR), via structure.

I. INTRODUCTION

S signal rates rise to the multigigabit range, the influence

of via discontinuities on the signal integrity of printed circuit boards has become more and more significant and nonnegligible. In common cases, the via may cause a negative reflection
pulse that distorts the quality of digital signals and even the resultant eye diagram. By utilizing high-impedance interconnects,
the nonideal effects of the via structures that present an overall
capacitive property can be alleviated [1]. Since the electrical behavior of the via depends on the relative geometry, an alternative and more comprehensive idea to directly search for the solution space of the physical dimension over which its effective
impedance is matched to the specific system impedance will be
realized in this paper.
In order to account for the high-frequency effects of via discontinuities, the lumped-circuit models are usually established

Manuscript received November 14, 2006; revised March 30, 2007. This work
was supported in part by the National Science Council, R.O.C., under Grant
NSC 95-2213-E-002-016 and in part by the Taiwan Semiconductor Manufacturing Company. This work was recommended for publication by Associate Editor M. Cases upon evaluation of the reviewers comments.
K.-T. Hsu is with ASUSTek Computer, Inc., 11259 Taipei, Taiwan, R.O.C.
W.-D. Guo, T.-W. Huang, and R.-B. Wu are with the Department of
Electrical Engineering and Graduate Institute of Communication Engineering, National Taiwan University, 10617 Taipei, Taiwan, R.O.C. (e-mail:
f92942062@ntu.edu.tw; rbwu@ew.ee.ntu.edu.tw).
G.-H. Shiue is with JinWen University of Science and Technology, Taipei,
Taiwan, R.O.C.
C.-M. Lin is with the Packaging Core Competence Department, Advanced
Assembly Division, Taiwan Semiconductor Manufacturing Company, Ltd.,
30077 Taiwan, R.O.C. (e-mail: chienmin_lin@tsmc.com).
Color versions of some of the figures in this paper are available online at
http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TADVP.2007.908033

with reference to the geometry of via structures. Several works

on the circuit-model extractions of single-ended vias have been
proposed [2][4]. In general, the -type equivalent circuit model
that can be calculated from the full-wave simulation is enough
to characterize the electrical behavior of the via structure if only
the length is small as compared with the signal wavelength.
Although the full-wave simulation can lead to accurate
model results and provides a simple approach to analyzing
the signal integrity issues caused by the via holes such as the
reflection noise or ground-bounce noise [5], the tremendous
computational effort makes the characterization impractical
for efficient circuit design. Moreover, it is also difficult to
apply this approach to the design of varied structures because
the mapping between the geometry parameters and electrical
properties is still unknown.
An extensive literature is devoted to approximating the
unknown mapping by curve fitting. The commonly used fitting functions might be the polynomials, rational functions,
and trigonometric functions. However, they are not suitable
for dealing with the high-dimensional and highly nonlinear
problems. In recent years, electromagnetically trained artificial
neural network (EM-ANN) approaches have gained wide
recognition due to greater robustness and better approximation
[6], [7]. The applications of EM-ANNs include the modeling
of spiral inductors [8] and the via structure [9], automatic
impedance matching [10], microstrip circuit design [11], and
optimization of microwave circuits [12]. Accurate and fast
neural models can be developed from the simulated EM data
and thus speed up the circuit design with EM-level accuracies.
This paper elaborates the EM-ANN idea to find the so-called
electrical solution space for the design of low reflection noise
via structures. After a brief statement of the problem, Section II
describes the modeling of a via with single-ended signaling interconnect. The ANN developed with the simulated EM data is
given in Section III. Then, the low-reflection design of via structures is available using the neural network model in Section IV,
with the time-domain simulated and experimental validation in
Section V. At last, conclusions are addressed in Section VI.
II. MODELING OF VIA DISCONTINUITIES
Fig. 1 depicts the geometry and the notable physical parameters of the single-ended via structure. For the via in a single
ground plane and in the common case that its length is much
smaller than the wavelength, say smaller than one-tenth wavelength, of the operating frequencies, it can be modeled by a
-type equivalent circuit as shown in Fig. 2 [2]. Note that the
excess capacitance takes the charge density on the via barrel and

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Fig. 1. Physical structure of single-ended via transition. (a) 3-D view. (b) Side
view. (c) Top view.
Fig. 3. Single-ended S-parameter of test structure.

Fig. 2.

 -type equivalent circuit of via.

via pad into account. The increase in current return path due to
the via appearance denotes the excess inductance.
Both the capacitance and inductance values are accessible to
, anti-pad
the geometry parameters such as via pad radius
, and barrel radius
. Decreasing the via pad and
radius
via barrel radius, but increasing the anti-pad radius, results in
the reduction of capacitance because the capacitive coupling between the via conductive material and ground plane is getting
smaller. However, the inductance becomes larger with the increase in anti-pad radius, which leads to a longer current return
path on the ground plane.
For the given two-port network, the admittance matrix [Y] is
chosen here and can be characterized by full-wave simulation.
The via structure is located within the transmission lines and
the source excitation is incident from the time-domain reflection (TDR) side as displayed in Fig. 1(a). Moreover, the physical lengths of the lines are in general longer than one-quarter
wavelength of the desired frequency to ensure that the higher
order modes excited at the interface do not degrade the simulation accuracy. After the admittance matrix of the via structure is
obtained by de-embedding the connected transmission lines, the
lumped- element values are thus determined, respectively, as
(1)
and
(2)
and series
By the balance between its shunt capacitance
inductance
, the effective via impedance is given by

(3)

To verify the accuracy of the -type equivalent circuit, its

S-parameters are compared with those obtained from full-wave
simulation. Take, for example, the structures given in Fig. 1
with the lengths of upper and lower microstrip lines both being
mm,
mm,
400 mm and the via dimensions of
mm, and
mm, full-wave analysis indicates
that the equivalent circuit extracted at 5 GHz is characterized
nH and the lumped caby the lumped inductance
pF. Although the equivalent circuit is
pacitance
acquired at the specific frequency of 5 GHz, it can still well estimate the via performance over a wider frequency range. Since
the inductance and capacitance values are inaccessible to the
frequency that is not extremely high, the validity of a -type
equivalent circuit is expectable over a frequency bandwidth.
The comparison of S-parameters between the equivalent circuit and full-wave analysis are shown in Fig. 3. As can be seen,
the modeling results are close to those of full-wave analyses
from 0.1 to 8 GHz and almost fit the full-wave simulation especially at 5 GHz. Fig. 3 reveals that the deviation error of the
equivalent circuit increases at higher frequency because the inductance as well as capacitance will become more and more
dependent on the frequency and its -type equivalent circuit is
no longer valid. For the via discontinuity with length
mm, the equivalent circuit is under a 3-dB error of -parameters compared with the full-wave simulation from 0.1 to 8 GHz.
Thus, the via performance can be well estimated if the via length
is smaller than 1/15 of the wavelength, as a rule of thumb.
III. ANN MODELING
Though full-wave characterization can yield accurate results,
it incurs much higher computational expense. In order to alleviate the iteration cost of full-wave analyses while retaining
the EM-level accuracy, the EM-ANN approach is attractive in
modeling the complex and nonlinear problems since the neural
network possesses the learning capability of the arbitrarily nonlinear mappings between the input and output parameters [9]. A
neural network is trained using the training data sets to adjust
the network parameters and checked with the testing data sets
to correlate with the generalization of prediction profile. The

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HSU et al.: DESIGN OF REFLECTIONLESS VIAS USING NEURAL NETWORK-BASED APPROACH

213

back-propagation algorithm [13]. Assume that the accumulated

error function is given by

(5)

Fig. 4. ANN architecture.

training procedure is a self-organizing process designed to obtain an appropriate set of connection weights that the error of
the output parameters is acceptable.

where denotes the adjustable weights,

denotes the error
function of the th output parameters, and is the number of
output parameters.
The purpose of neural network training is that the accumulated error function can be lowered to the acceptable value by the
modification in weights. For the LevenbergMarquardt backpropagation algorithm, the second-order Taylors series is applied and the connection weights are updated according to the
first-order as well as the second-order gradient of the error func. For simplicity, the gradient function can be acquired
tion
, given by
in terms of the Jacobian matrix

A. ANN Structure

(6)

The neural network used in this paper employs the tool kit
built in Matlab [13]. Its architecture consists of three layers as
shown in Fig. 4: one input layer, one hidden layer, and one
output layer. Neurons
connected to each other
with the adjustable weights are the basic processing elements
of the network. The process of neurons between the hidden
layer and the output layer is different. For the hidden layer, the
weighted inputs to each neuron are accumulated and then passed
through the logarithmic sigmoid activation function

(4)
to determine the response of the neuron. Nevertheless, in the
output layer, the output response of each neuron is just the accumulation of its weighted inputs.
The logarithmic sigmoid activation function allows the
hidden layer to model the complex inputoutput relationship.
The complexity of the ANN structure will increase when the
additional neurons are added to the hidden layer. A network
without enough neurons cannot map the complex inputoutput
relationships. However, a network with too many neurons tends
to over-fit the training data and lacks the generalization. An
important issue for ANN modeling is thus the proper selection
of neurons. First, the architecture of the three-layer neural
network with fewer neurons of the specific activation function
is determined. The neurons of the hidden layer are increased
step by step until the desired accuracy is achieved.

B. ANN Training
ANN training is the procedure of updating connection
weights to minimize the error between the outputs of the
network and the expected outputs. The neural network learns
from the samples of inputoutput data such as training data
sets. The learning rule here involves the LevenbergMarquardt

and
(7)
The back-propagation is then employed to calculate the Jacobian matrix. Each connection weight is adjusted by
(8)
which can be computed with the gradient
The parameter
function
and
is given by
(9)
denotes the weight value at the th training iteration,
where
is the identity matrix, and is an adaptive value according to
the training process.
The performance of the neural network is evaluated and quantified by the mean-square error, given by

MSE

(10)

where is the expected output response obtained from full-wave

simulation, and is the neural model response. The error tolerance is set to be 0.0001 for the termination of training.
After training, the neural model can well fit the performance
.
of training data sets with the accuracy of MSE
Though the error of the neural model is acceptable for training
data sets, it may be invalid for other data sets, and thus the
model lacks generalization. To avoid this, randomly selected
samples such as testing data sets must be employed to check
the prediction error. The successfully trained ANN model must
make sure that both the training error and prediction error are
below the error tolerance.

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Fig. 5. Block diagram of ANN model for the via structure.

TABLE I
DIMENSION RANGE OF DESIGNED PHYSICAL PARAMETERS

Fig. 6. Comparison of neural model results with full-wave results.

C. ANN Modeling
In this paper, the goal of neural network modeling is to
develop a precise mapping of the relationship between the
via layout parameters and the effective via impedance. Fig. 5
shows the block diagram of the neural network model. The
via structure and physical parameters under consideration have
been shown in Fig. 1. Let the dielectric constant
of the
substrate be 4.4. Since the effective via impedance depends
only on the geometry of the via structure, the radius of via
, anti-pad
, and via pad
are all normalized
barrel
and then served as the input parameters
to the via length
of the ANN.
Table I lists the dimension range of each layout parameter
taken into account. There are 54 different via structures to be
uniformly selected over the range as listed in Table I and the
effective via impedances are calculated by the full-wave solver.
These 54 data vectors, which serve as training data sets, are then
used to train the artificial neural network. By the same scheme,
30 different via structures are arbitrarily selected over the same
range and analyzed by a full-wave simulator. The trained neural
network is then tested with the 30 data vectors, which serve as
the testing data sets, for the observation of prediction error.
The prediction error defined here is that the discrepancy in
the analyzed and predicted via impedances cannot be larger
than 5%. The number of neurons in the hidden layer is selected
according to the accuracy of the neural network model. After
the ANN model is successfully trained and tested, there are
three neurons in the hidden layer. The corresponding difference between the EM-simulated impedances and ANN- computed impedances are evaluated at 0.67 for the averaging error
and 0.47 for the standard deviation. Fig. 6 shows the comparison between the EM-simulated and ANN-modeled values
with 54 training data vectors as well as 30 testing data vectors.
These results indicate the EM-ANNs ability in capturing the
inputoutput relationships. The developed model may now be
used in the design of reflectionless via structures.

IV. DESIGN OF REFLECTIONLESS VIA HOLES

A. Electrical Solution Space
Signal reflection takes place when it propagates through discontinuities such as via holes or similar structures. As encountered by a rising signal, any via discontinuity with its effective
impedance lower than the impedance of interconnect transmission lines creates a negative reflection. Conversely, a positive reflection is induced by a signal via with higher impedance. The
reflection noise will distort the signals and the eye-diagram integrity at the probing ends. Thus, a thoughtless design of via
holes on printed circuit boards may degrade the signal integrity
of an interconnection.
Reflection noise associated with the effective impedance of
interconnection will depend on the rising time of the signal and
the physical structures of via connectors. Since the impedance
mismatch between the transmission lines and via connectors is
the major cause of reflection issues, a reflectionless via can be
achieved by appropriately designing its geometry parameters to
match the desired impedance.
For the via structure shown in Fig. 1, the equivalent circuit and
effective via impedances can be derived by the full-wave simulator. It is found that the via impedance will change according
to the physical parameters such as the barrel radius , anti-pad
radius
, and via-pad radius
. Larger via impedance can
be achieved by increasing the anti-pad radius or decreasing the
via-pad radius and via-barrel radius, owing to the higher inductance and lower capacitance values. Though the full-wave solver
can be employed to sweep the physical parameters for the adaptive design of via structures, the time-consuming iterations with
full-wave simulations are inefficient and impracticable. To enhance the design feasibility, the ANN model is thus developed
instead of the repetitive trials on full-wave simulations.
Once the neural network model is successfully developed,
the output response of the network can be formularized as the
combination function of the neurons activation function with
adaptive weights and arbitrary physical parameters. To reduce

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HSU et al.: DESIGN OF REFLECTIONLESS VIAS USING NEURAL NETWORK-BASED APPROACH

TABLE II
VARIOUS VIA DIMENSIONS WITH DIFFERENT EFFECTIVE IMPEDANCES (VIA LENGTH L

215

= 50 MM, " = 4:4, BARREL RADIUS R = 20 MM)

Fig. 7. Via impedance over via- and anti-pad radius ratio.

Fig. 8. Design range for 50-

via structures.

the reflection noises from signal vias, the neural model is used
to sweep the physical parameters over the dimension range as
listed in Table II and determine the physical dimension range
where the via structure has effective impedance close to the
characteristic impedance of transmission lines.
For the dimension range of physical parameters under the
design consideration, the via impedance is most sensitive to the
via-pad and anti-pad radius. The suitable design area for the
expected via impedance can thus be graphically represented by
the physical parameters of via-pad and anti-pad radius. With
, there are 10 000
the constant barrel radius ratio of
different via structures composed of the 100 different sets of
via-pad and anti-pad radii to be swept by the ANN model. Fig. 7
shows the sensitivity plots of effective via impedances over
and
the dimension range of the via-pad radius ratio
, provided that
.
anti-pad radius ratio
Using the results obtained in Fig. 7, the model is able to help
design the single-ended via structures for the expected via
impedance more efficiently.

mm, and dielectric constant of the substrate

, the 50- microstrip line of length 2 cm is designed
with the line width
mm and thickness
mm. Since
ratio is equal to 0.4, the via impedance is available
the
and
in
directly from the parameter sets of
Fig. 7.
It is noted that the major reflection noise attributed to the
impedance mismatch and the via connector with an impedance
near 50 is expected to cause the least reflection noise. Moreover, any via discontinuity with effective impedance below 50
will result in a negative reflection such that the magnitude of
the reflection noise decreases with increasing via impedance.
On the contrary, a positive reflection is induced by the higher
impedance of a signal via and can be lowered by decreasing
the via impedance. It is worth noting that the transmitted wave
will exhibit positive ramped pulse at the TDT end regardless of
the impedance level, but with slower signal transition. The occurrence can be attributed to the finite time constant of the via
discontinuities.
In order to observe the changes in reflection noise, the via
structures with effective via impedances ranging from 20 to
100 are divided into five groups. Various via structures are arbitrarily selected in each impedance group as listed in Table II
and analyzed with the time-domain solver. Let the rising time
of input signal be 100 ps and the amplitude be 0.5 V. Fig. 9
shows the time-domain simulation results of TDR waveforms

B. Time-Domain Simulation
To demonstrate the electrical solution space shown in
Figs. 7 and 8, the 3-D finite integration simulator [14] is used
to investigate the time-domain waveforms of the via connectors with different effective impedances. For the via structure
mm, barrel
given in Fig. 1 with the via length

radius

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Fig. 11. Measured TDR waveforms for via discontinuities.

Fig. 9. Simulated TDR waveforms for various via sizes listed in Table II.

Fig. 10. Photos of three test structures for via design.

for a selected via structure in each of the five groups. When the
effective via impedance is higher than the desired impedance of
50 , a positive reflection noise occurs but decreases with decreasing via impedance. On the other hand, the via connector
with effective impedance below 50 yields a negative reflection noise.
Finally, it can be found that the via structures designed with
reference to the colored region in Fig. 8 have the minimum
noise. As a result, the electrical solution space for designing via
connectors with the least reflection noise is verified by the 3-D
finite integration simulator in the time domain.
V. EXPERIMENTAL VALIDATION
A single-ended via in a single ground plane is fabricated to
investigate the reflection noise due to via discontinuities. For the
structure depicted in Fig. 1, the design parameters are set to be
mm,
mm,
mm,
mm,
, and the microstrip line lengths
mm. The anti-pad
and
radius is selected in reference to Fig. 7 with
mm and the photos of the three cases are displayed in Fig. 10.
Both the time- and frequency-domain experiments are focused
on the reflection noise due to via discontinuities for verifying
the electrical solution space, as shown in Fig. 8.
By using TEK/CSA8000B, a time-domain reflectometer, the
experimental verification is performed while the ramped step
pulse of 0.5 V and rising time about 50 ps is applied for the excitation on the input port 1. As demonstrated in Fig. 11, the TDRmeasured reflection noise corresponding to the high- impedance

Fig. 12. Measured S -parameters for via discontinuities.

mm is about 13 mV. Conversely,

via connector with
mm causes
the low-impedance via connector with
reflection noise of about 22 mV. However, the via structure
mm which lies within the shaded region in Fig. 8
with
indeed causes a smaller reflection noise of less than 2 mV in
magnitude. Meanwhile, the 5-mV reflection noise occurring before or after the appearance of the via effect is the result of the
discontinuity due to the SMA connectors.
For the frequency-domain verification, the -parameters are
measured from 0.3 to 8 GHz using Agilent E5071B VNA, a
of the
network analyzer, and shown in Fig. 12. Overall, the
mm is 10 dB less than that with
via connector with
and 70 mm. It is also apparent that the corresponding
frequency interval between two consecutive resonance peaks is
only one half of the other cases. Since the resonance of the -parameter is due to the multiple reflections over the total signal
path, the reason for the phenomenon should be that the reflections in the well-designed structure occur only at the locations
of the two SMA connectors. Besides, the reflection is small and

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HSU et al.: DESIGN OF REFLECTIONLESS VIAS USING NEURAL NETWORK-BASED APPROACH

thus the measured data are more susceptible to the measurement

errors.
Both the time-domain and frequency-domain experiments
presented in Figs. 11 and 12, respectively, indicate that the
design of via connectors with the least reflection noise can
be achieved by selecting physical parameters according to the
ANN model proposed in this paper.

VI. CONCLUSION
In this paper, the design technique of employing an ANN for
constructing reflectionless via structures is proposed, examined,
and validated. Based on the EM-ANN approach, the relationship
between the physical parameters and the effective via impedances can be formularized as the combination sets of neurons
activation functions. Therefore, the time-consuming iterations
of full-wave simulations can be alleviated by the neural model
for its efficiency. Using the concept of impedance matching, the
design of reflectionless vias can be achieved by sweeping the parameters with the aid of the neural network model. Finally, the
design rules of expected via impedances are derived and verified with simulations and experiments.
A systematic procedure is established, offering convenience
for designing reflectionless via structures without resorting to
the time-consuming full-wave simulator. The sensitivity of design parameters is also gauged to explore the feasible solution
space within the boundary limit of physical dimensions. By
the addressed procedure, the discontinuity problems of passive
components such as the via, bend, or package pin can be improved in the prelayout design and postlayout verification.

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Ku-Teng Hsu was born in Taipei, Taiwan, R.O.C., in

1981. He received the B.S. degree in communication
engineering from the National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 2004, and the M.S.
degree in communication engineering from the National Taiwan University, Taipei, Taiwan, R.O.C., in
2006.
He has worked on signal/power integrity analysis
of high-speed digital interconnects at ASUSTek
Computer, Inc., since January 2007.

Wei-Da Guo was born in Taoyuan, Taiwan, R.O.C.,

on September 25, 1981. He received the B.S. degree
in communication engineering from the Chiao-Tung
University, Hsinchu, Taiwan, R.O.C., in 2003. He is
currently working toward the Ph.D. degree in communication engineering at National Taiwan University, Taipei, Taiwan.
His research interests include computational electromagnetics and SI/PI issues in the design of highspeed digital systems.

Guang-Hwa Shiue was born in Tainan, Taiwan,

R.O.C., in 1969. He received the M.S. degree in
electrical communication engineering from National
Taiwan University of Science and Technology,
Taipei, Taiwan, R.O.C., in 1997, and the Ph.D.
degree in communication engineering from National
Taiwan University, Taipei, Taiwan, R.O.C., in 2006.
He is currently an Assistant Professor with the
Electronics Department, JinWen University of
Science and Technology, Taipei, Taiwan, R.O.C. His
research interests include numerical techniques in
electromagnetics, microwave planar circuits, signal/power integrity (SI/PI) and
electromagnetic interference/compatibility (EMI/EMC) for high-speed digital
systems, and electrical characterization of system-in-package.

Chien-Min Lin (M92) received the B.S. degree

in physics from National Tsing Hua University,
Hsinchu, Taiwan, R.O.C., the M.S. degree in electrical engineering from National Taiwan University,
Taipei, R.O.C., and the Ph.D. degree in electrical
engineering from the University of Washington,
Seattle.
He was with IBM for the xSeries server development and Intel Corporation for the advanced platform
design. In January 2004, he joined Taiwan Semiconductor Manufacturing Company, Ltd., as a Technical
Manager in the packaging design and assembly validation. He has been working
on Computational Electromagnetics for the designs of microwave device and
rough surface scattering, signal integrity analysis for high-speed interconnect,
and electrical characterization of system-in-package.

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IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 31, NO. 1, FEBRUARY 2008

Tian-Wei Huang (S91M98SM02) received the

B.S. degree in electrical engineering from National
Cheng Kung University, Tainan, Taiwan, R.O.C., in
1987, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Los Angeles (UCLA), in 1990 and 1993, respectively.
In 1993, he joined the TRW RF Product Center,
Redondo Beach, CA. His research has focused on
the design and testing of MMICs and RF integrated
circuits (RFICs). During 1998 and 1999, he was
with Lucent Technologies, working on the local
multipoint distribution system (LMDS) fixed wireless systems. From 1999 to
2002, he was involved in the RF/wireless system testing at Cisco Systems. In
August 2002, he joined the faculty of the Department of Electrical Engineering,
National Taiwan University, Taipei, Taiwan, R.O.C. His current research
interests are MMIC/RFIC design, packaging, and RF system-on-chip (SOC)
integration.

Ruey-Beei Wu (M91SM97) received the B.S.E.E.

and Ph.D. degrees from National Taiwan University,
Taipei, Taiwan, R.O.C., in 1979 and 1985, respectively.
In 1982, he joined the faculty of the Department
of Electrical Engineering, National Taiwan University, where he is currently a Professor and the Department Chair. He is also with the Graduate Institute
of Communications Engineering established in 1997.
From March 1986 to February 1987, he was a Visiting Scholar at IBM, East Fishkill Facility, NY. From
August 1994 to July 1995, he was with the Electrical Engineering Department,
University of California, Los Angeles. He was also appointed Director of the
National Center for High-Performance Computing (19982000) and has served
as Director of Planning and Evaluation Division since November 2002, both
under the National Science Council. His areas of interest include computational
electromagnetics, microwave and millimeter-wave planar circuits, transmission
line and waveguide discontinuities, and interconnection modeling for computer
packaging.

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