DECOUPLED DOUBLE SYNCHRONOUS

REFERENCE FRAME PHASE LOCKED LOOP

EE646
BY

Department of Electronics and Electrical

Engineering
IIT Guwahati

BASIC OF PLL (synchronization techniques)

The most widely accepted synchronization solution to a time-varying signal can
be described by the basic structure as shown, where the difference between
phase angle of the input and that of the output signal is measured by the phase
detection (PD) and passed through the loop filter (LF). The LF output signal
drives the voltage-controlled oscillator (VCO) to generate the output signal,
which could follow the input signal.

TYPES OF PLL
1. Synchronous Frame PLL (SF-PLL)
2. PQ-PLL
3. DSF-PLL
4. DSOGI-PLL
5. SSI-PLL
6. E-PLL
7. M-PLL
8. Q-PLL

DDSRF-PLL
The double SRF is composed of two rotating reference frames: dq+1, rotating

with the positive direction and whose angular position is + , and dq-1, rotating

with the negative direction and whose angular position is .

Three-phase asymmetrical voltage can be expressed as the set of symmetrical

voltage as :

U +1, U -1, U 0, +1, -1, 0 are amplitude and initial phase of the positive
sequence, negative sequence, and zero sequence component of three-phase
voltage, respectively. In order to eliminate the influence of the zero sequence
components, three-phase voltage can be transformed to the coordinate
system.

The above equations can be transform to double synchronous

coordinate(double synchronous transform) system as:

Double synchronous coordinate system includes two rotating coordinate system.

Positive synchronous rotating coordinate system dq +1 rotates anti-clockwise at
w angular velocity, rotation angle is , and negative synchronous rotates
clockwise at -w angular velocity, rotation angle is -. Voltage diagram is as

If phase is locked, then

' wt
sin(wt ) wt
cos(wt ) 1((wt (wt )2/2);
Substituting approximated values we obtain

It can be seen that there is double frequency component in

unbalance voltage after transformation and double
synchronous transform. In order to get dc component of
positive sequence component in each phase, cross

decoupling algorithm was applied to eliminate the double

frequency.

How decouple circuit works we will see next

Low-pass filtering link is applied to reduce harmonics brings to
synchronous phase lock loop. Through extracting positive
sequence component, U*q , so the amplitude, phase and
frequency of positive sequence, negative sequence component
can be accurately output by the phase lock loop.
Though it is proposed above that there is double frequency component in
unbalance voltage after transformation and double synchronous transform
and can be eliminated by cross
decoupling algorithm, the effect is not
ideal so we add a new method called IDDSRF (improved).

It can be seen from above equation that error signal does not contain ripple.

DECOUPLING SIGNAL IN THE DSRF

To introduce the DN, one supposes a voltage vector consisting of two generic
components rotating with n and m frequencies respectively, where m and n
can be either positive or negative.

We are going to consider two rotating reference frames, dqn and dqm , whose
angular positions are n' and m' , respectively, being ' the phase angle detected
by the PLL. Finally, it is assumed '=t, where is the fundamental utility
frequency. Therefore, the voltage vector can be expressed on these reference
frames as follows:

In order to cancel the oscillations in the dqn axes signals, the decoupling cell
(DC) OR Decoupling network is used.

Logically, for a correct operation of both DCs it is necessary to design

some mechanism to determine the value of Vsdn , Vsqn , Vsdm and Vsqm
. Keeping this goal in mind, the decoupling network (DN) is proposed as
above. In this DN, the LPF block is a low-pass filter such as

LPF Wf / Wf S

For analysis of the DN we use two signals

Multiplication in time domain gives convolution in frequency domain, implies-

In time domain:

Taking

A(t)= -B(t) ; C =1 ;
This state-space model corresponds to a multiple-input multiple-output (MIMO)
linear time variant system. Since the analytic solution of this system is highly
complex.
So response is evaluated using n = +1 and m = -1 and for further simplification
we substitute

1 0, 1 0;

CONTREOL SYSTEM OF DDSRF-PLL

The above equation decreases exponentially with k and system is oscillatory so
to make the system stable we choose k such that system become underdamped.
Here we see the response (Vs+1) with respect to time for different values of k.

It seems logical to establish k =0.707, since the dynamic response is fast enough
and does not appear oscillations in the amplitude estimation of Vs+1. Where it
is assumed 't. Taking into account that ' is obtained by means of the PLL in
the real system.
The higher value assigned to k, the faster response. Nevertheless it is necessary
to note that transitory error in the system response will be also higher, which
can give rise to an unstable behaviour of the detection system. This justifies

why the value of k should not be too high in order to reduce oscillations in the
response and make the detection system more stable.

Logically, after the stabilization period, which is approximately

equal to a grid period, the signal Vsq+1 is equal to zero. Initially
under unbalance condition phase detected by PLL was not
accurate.

Comparison of SRF and DDSRF-PLL

Shunt active power filter (SAPF):
The main circuit of the SAPF is a two-level four-leg voltage
source inverter (VSI). The compensation current detection
algorithm is SRF method. Calculation of reference voltages and
3D direct PWM method are adopted in the control system. In
order to test the compensation performance, SRF-PLL and
DDSRF-PLL are used.

If the SAPF does not provide compensation to the system, the source currents
would be the same as the load currents. Reactive current, current harmonics and
neutral current is necessary to be compensated. Thus SRPF is used to provide

accurate compensation in the system under unbalance condition and DDSRFPLL provides accurate positive sequence phase.

RESULT:
It can be seen that IDDSRF-PLL eliminates the double frequency component,
restrains the influence negative sequence component brings to phase-lock link,
and accurately detect the harmonic current in the grid under asymmetry and
distortion circumstances; low-pass filter LPF is inserted in the phase lock link of
IDDSRF-PLL method.