Ref: V15/QTN/2264

Dated : 24-Oct-2015

THE PRINCIPAL,
INDIRA INSTITUTE OF ENGINEERING & TECHONOLOGY,
NO.1.V.G.R. GARDEN,
V.G.R. NAGAR,
PANDUR,
THIRUVALLUR - 631 203.

Kind Attn. : HOD OF ECE DEPARTMENT

Dear Sir,
As desired by you, we are pleased to enclose our QUOTATION for your favorable consideration.
We believe that you will find our offer as quite attractive and cost effective to your needs.
Incase you require any further clarifications or details please do feel free to contact us.
Looking forward to receive your valuable order
Thanking you and assuring of our best services.
Yours faithfully,
For Vi Microsystems Pvt. Ltd.,

AUTHORISED SIGNATURE

Ref: V15/QTN/2264

Dated : 24-Oct-2015

QUOTATION
UNIVERSITY
: ANNA UNIVERSITY [CHENNAI - REGULATIONS 2013]
DEPARTMENT
: ECE
SUBJECT
: EC6612 VLSI DESIGN LABORATORY
SEMESTER
: VI
SL.NO NAME OF THE EXPERIMENT NAME OF THE MODULE MODULE NO
TO BE USED
FPGA BASED EXPERIMENTS
1
HDL based design entry and
simulation of simple counters, state
machines, adders (min 8 bit) and
multipliers (4 bit min).
2
Synthesis, P&R and post P&R
ISE WEBpack / ISE
simulation of the components
Foundation
simulated in (I) above. Critical
paths and static timing analysis
results to be identified. Identify
and verify possible conditions
under which the blocks will fail to
work correctly
3
Hardware fusing and testing of
Cyclone IV Trainer Kit
VPTB-23
each of the blocks simulated in (I).
Use of either chipscope feature
(Alternatively)
(Alternatively)
(Xilinx) or the signal tap feature
(Altera) is a must. Invoke the PLL Spartan 6 Trainer Kit
VPTB-20
and demonstrate the use of the PLL
module for clock generation in
FPGAs.
IC DESIGN EXPERIMENTS: (BASED ON CADENCE / MENTOR GRAPHICS /
EQUIVALENT)
4
Design and simulation of a simple
5 transistor differential amplifier.
Measure gain, ICMR, and CMRR
5
Layout generation, parasitic
extraction and resimulation of the
circuit designed in (I)
6
Synthesis and Standard cell based
design of an circuits simulated in
1(I) above. Identification of critical
paths, power consumption
7
For expt (c) above, P&R, power
and clock routing, and post P&R
simulation.
8
Analysis of results of static timing
analysis

FPGA BASED EXPERIMENTS.

1. HDL based design entry and simulation of simple counters, state machines, adders (min
8 bit) and multipliers (4 bit min)
&
2. Synthesis, P&R and post P&R simulation of the components simulated in (I) above.
Critical paths and static timing analysis results to be identified. Identify and verify
possible conditions under which the blocks will fail to work correctly.
ISE WEBpack / ISE Foundation
3. Hardware fusing and testing of each of the blocks simulated in (I). Use of either
chipscope feature (Xilinx) or the signal tap feature (Altera) is a must. Invoke the PLL and
demonstrate the use of the PLL module for clock generation in FPGAs.
CYCLONE IV TRAINER KIT [VPTB-23]
Specifications:
*

*
*
*
*
*
*

*
*
*
*
*
*
*
*
*
*

EP4CE22 Based on Altra Cyclone IV FPGA features:

#
28848 Logic cells
#
594 Kb of Embedded RAM
#
62 Nos of Embedded multiplier
16 Nos. of digital input using slide switches with LED indication
16 Nos. of digital output using discrete LEDs
16 2 LCD is provided for display the text message.
One Reset Switch
One switch for giving manual clock
FPGA configuration through
#On-board Xilinx USB to JTAG Programmer with isolation to configure
FPGA
#On board Flash Prom XCF04S (programmable through USB to JTAG
programmer) Cashew jacket for 5V power supply
Total 186 I/O Pins: 100 Pins used for integrating peripheral like LED, Switches
etc., balance pins are available to user in 3nos of 20 pin header.
1 No of 26 pin header to interface VLIM cards like Traffic Light Controller / Onboard TLC factory settable.
On board programmable PLL oscillator from1 MHz using jumpers
4 Nos of 7 segment LED display
One relay and Buzzer provided.
Stepper & DC motor drive provided on board (Motor Optional)
4x4 matrix key provided
Housed in a sleek plastic cabinet with built in SMPS 5V/2A.
Compatible with Xilinx ISE Foundation / Web PACK Software. (Version 12.1and
above)
SPI Based Analog to Digital Converter
#
Resolution
:
12 bits
#
Number of Channel :
2 Channels
#
Input Range
:
0 to 5V
#
Speed
:
1 Msps
SPI Based Digital to Analog converter
#
Resolution
:
12 bits
#
Number of Channel :
2 Channel

#
#

Output Range
Speed

:
:

0 to 5V
8.5 S settling time
Rs.
20,100.00+
VAT @ 5%

NOTE : ALTERA QUARTUS-2 SOFTWARE Free Download by institution

(ALTERNATIVELY)
SPARTAN 6 TRAINER KIT

[VPTB-20]

Specifications:

XC6SLX16 based on Xilinx Spartan-6 FPGA features

# 14579 Logic cells
# 2278 kb of distributed RAM
# 136 Kb of Block RAM
# 32 NOS of DSP Slices
# 2 NOS of Clock Management Tiles (CMT)
# 2 NOS of Memory Controller Block (MCB)
# 186 User I/O lines
16 Nos of digital input using slide switches with LED indication
16 Nos of digital output using discrete LEDs
16 2 LCD is provided for display the text message
One Reset Switch
One switch for giving manual clock
FPGA configuration through
On Board Xilinx USB to JTAG Programmer with isolation to configure FPGA
On Board Flash Prom XCF04S (Programmable through USB to JTAG programmer)
Cashew jacket for 5V power supply
Total 186 I/O Pins: 100 Pins used for integrating peripheral like LED, Switches etc.,
balance pins are available to user in 3 nos of 20 pin header.
1 No of 26 pin header to interface VLIM cards like Traffic Light Controller / On- board
TLC factory settable.
On board programmable PLL oscillator from 1MHz to 100Mhzusing jumpers
4 Nos of 7 segment LED display
One relay and Buzzer provided
Stepper & DC motor drive provided on board (Motor Optional)
4 4 matrix key provided
SPI Based Analog to Digital Converter
# Resolution
: 12 bits
# Number of Channel : 2 Channel
# Input Range
: 0 to 5V
# Speed
: 1Msps
SPI Based Digital to Analog Converter
# Resolution
: 12 bits
# Number of Channel : 2 Channel
# Input Range
: 0 to 5V
# Speed
: 8.5 S setting time
Housed in a sleek plastic cabinet with built in SMPS 5V/ 2A

Compatible with Xilinx ISE Foundation / Web PACK Software (Version 12.1 and above)
Rs.
19,400.00 +
VAT @ 5%

NOTE: XILINX SOFTWARE SHOULD BE PROVIDED BY THE

INSTITUTION

Terms & Conditions

01
02
03

VAT
Validity of offer
Terms of payment

04

Delivery

05
06
07

Warranty
Annual Maintenance
Charges (AMC)
Insurance

Extra @ 5 %
90 Days from the date of quotation
50 % advance along with PO & 40 % against Performa
invoice and 10 % after delivery and Installation
10 12 Weeks from the date of receipt of techno
commercial clear and firm purchase order.
One year from the date of delivery
After expiry of warranty period 10 % will be charged for
every year.
Paid by Vi Microsystems Pvt Ltd

08
09

Packing & Forwarding

Installation

Extra @ 2 %
Free of cost

For Vi Microsystems Pvt. Ltd.

AUTHORISED SIGNATURE.
TIN NO.:33891580314
CST NO.:42596