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TECHNOLOGIES
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Jane Lin-Li
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Cheryl Coupe, Chris Ciufo
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IN THE NEWS
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For anyone worried about the next generation of engineers,
can be reassured as 15-year old Nathan Han (pictured)
receives the Gordon E Moore Award from Intel. The Boston
teenager won the $75,000 prize for devveloping a machine
learning software tool to study mutations of a gene linked to
breast cancer. Also honored at this years Intel International
Science and Engineering Fair, were Lennart Kleinwort of
Germany and Shannon Lee of Singapore who each received
$50,000 prizes as Intel Foundation Young Scientist Awards.
winners Lennart Kleinwort (15) of Germany and Shannon
Lee (17) of Singapore each received prizes of US$50,000
from the Intel Foundation.
Scientists at the University of Reading have found a link
between thunderstorm activity and streams of high energy
particles accelerated by the solar wind. The findings provide
evidence that particles from space help trigger lightning
bolts.
The researchers propose that the electrical properties of the
air are altered as the incoming charged particles from the
solar wind collide with the atmosphere.
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IP
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where and how the sign-off happens between the IP and SoC
designers create design issues that affect the final products
performance and release. IP designers often validate their IPs
in isolation with expectations of near ideal operating conditions.
SoCs are verified and signed off with mostly abstracted or in many
cases black-box views of IPs. But as more and more high speed
and noise sensitive IPs get placed next to each other or next to
the core digital logic failure conditions that were not considered
emerge. This worsens when these IPs share one or more power and
ground supply domains. For example, when a bank of high speed
DDR IPs are placed next to a bank of memories, the switching
of the DDR can generate sufficient noise on the shared ground
network that can adversely affect the operation of the memory.
As designs migrate to smaller technology nodes, especially those
using FinFET based technologies this gap in the design closure
process is going to worsen the power noise and reliability closure
process.
DDR memory blocks are becoming a greater and greater portion
of a chip as the portion of functionality implemented in firmware
increases. Bob Smith, Senior VP of Marketing and Business
Development at Uniquify makes the case for a system view of
memories.
DDR IP is used in a wide variety of ASIC and SoC devices
found in many different applications and market segments. If the
device has an embedded processor, then it is highly likely that
the processor requires access to external DDR memory. This
access requires a DDR subsystem (DDR controller, PHY and
IP
IO) to manage the data traffic flowing to and from the embedded
processor and external DDR memory.
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IP
and it takes several iterations to make the IP you got work the
way you want it to work. In addition, this process is extremely
tool-dependent.
Finally, there are system level issues like interoperability, interface
and controls (how does the IP talk to the rest of the SoC). A
very important, often overlooked factor is the communication
between the IP providers and the SoC implementation houses
there are documents outlining integration guidelines, but without
an automated process that takes in all that information, a lot
could be lost in translation.
The issue of how well a third party IP has been verified will
always hunt designers unless the industry finds a way to make
IP as trustworthy as the TI 7400 and equivalent parts of the
early days. Bernard Murphy, CTO at Atrenta observed: One
area that doesnt get a lot of air-time is how a SoC verification
team goes about debugging a problem around an IP. You have the
old challenge is this our bug or the IP developers bug? If the
developer is down the hall, you can probably resolve the problem
quickly. If they are now working for your biggest competitor, good
luck with that. If this is a commercial IP, you work with an apps
guy to circle around possibilities: maybe you are using it wrong,
maybe you misunderstood the manual or the protocol, may be
they didnt test that particular configuration for that particular
use-case Then they bring in their expert and go back through
the cycle until you converge on an answer. Problem is, all this
burns a lot of time and youre on a schedule. Is there a way to
compress this debug cycle?
He offers the following suggestion. One important class of
things to check for is the above didnt test that configuration for
that use-case. This is where synthesized assertions come in. These
are derived automatically by the IP developer in the course of
verifying the IP. They dont look like traditional assertions (long,
complex sequences of dependencies). They tend to be simpler,
often non-obvious, and describe relationships not just at the
boundary of the IP but also internal to the IP. Most importantly,
they encode not just functionality but also the bounds of the usecases in which the IP was tested. Think of it as a signature for the
function plus the verification of that function.
Thomas L. Anderson, VP of Marketing at Breker Verification
Systems pleads: integrate, but verify. He argues that The truth
is that most SoC teams trust integration too much and verify too
little. Many SoC products hit the market only after two or three
iterations through the foundry. This costs a lot of money and risks
losing market windows to competitors. Most SoC teams follow a
five-step verification process:
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www.si2.org
DAC Issue 2014t
ADVERTORIAL
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IP ISSUES
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Low power, wireless communications and small form factor are keys
to driving IoT applications. In many ways, these are closely related
to some wearable applications in that they use similar sensors and
common software libraries for communication, data abstraction and
signature recognition.
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TeraHz (THz) technology holds a great deal of promise for imaging and
sensing, wireless Gbit/s communications and millimeter-wave radar.
There have been several breakthroughs already this year that have added
to the anticipation, writes Caroline Hayes, Senior Editor.
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he gang of three, or the Grand Alliance, refers to the cooperation of foundry, IP and EDA companies to make
14nm FinFET a reality. Caroline Hayes, Senior Editor, asked
Steve Carlson, Director, office of Chief Strategy Officer, Cadence
Design, what was required to bring about FinFET harmony.
EDA (Cadence) has made some critical contributions in the rollout of enablement for FinFET:
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parts can often justify the additional design and test expenses
of delivering the same functionality as a single SOC.
The other major reason to go with an SIP is to improve the yield
of large area chips at the leading edge of fab processing. Since
defects/area tend to be relatively high with a new fab process,
very large chip designs will have relatively low yield at first but
then will improve as the fab learns how to reduce both random
and systematic yield limiters. The recent excellent example of
this trend is the Xilinx Vertex-7 FPGA which splits the chip
into four sub-chips and then uses a silicon interposer for SIP
re-integration. We may expect that a next-generation of the
product would be build in a single SOC after the yield improves,
at which point Xilinx would be expected to extend the product
line with additional functionality added in using multi-chip SIP.
FAN-OUT WLP
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DOT.ORG
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Agnisys, Inc.
CONTACT INFORMATION
Agnisys, Inc.
1255 Middlesex St. Unit I
Lowell, MA - 01851
Tel: 1855-VERIFYY
Fax: 1-978-349-6949
www.agnisys.com
Verication
Verication
IDesignSpec
CONTACT INFORMATION
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TECHNICAL SPECS
Cyclizing of print-on-change simulation vector les,
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INDUSTRIES SERVED
Audio, Automotive, Consumer Products, Defense,
Industrial, Entertainment, Networking, Telephony, Telecommunications, Wireless
CONTACT INFORMATION
Source III, Inc.
3941 Park Drive
Suite #20-342
El Dorado Hills, CA
95762
USA
tel: 916-941-9403
fax: 916-941-9404
corp@sourceiii.com
www.sourceiii.com
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Real Intent
Meridian CDC
Verication
Verication
BENEFITS
Highest capacity to enable CDC verication on
PLATFORMS SUPPORTED
Meridian CDC is supported on RedHat Enterprise Linux
5.0 (64-bit) and later operating systems.
FEATURES
Automatic design environment capture from designs
or SDC constraints
Comprehensive clock intent inference and analysis
catches clock and reset issues
Metastability aware formal analysis veries control
and data stability
Flexible top-down and bottom-up analysis to accommodate different design methodologies
XXXDIJQEFTJHONBHDPN
CONTACT INFORMATION
Real Intent
990 Almanor Ave. Suite 220
Sunnyvale, CA 94070
USA
Tel: 408-830-0700
Fax: 408-737-1962
info@realintent.com
www.realintent.com
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WORKSHOP HIGHLIGHTS
Verilog and SystemVerilog for Design and Synthesis:
Verication
Verication
Comprehensive training on the synthesizable portions of Verilog and SystemVerilog, with emphasis
on proper coding styles for optimal simulation and
synthesis results.
training on the SystemVerilog constructs used by
advanced verication methodologies, including OOP,
constrained random stimulus, and coverage.
Mastering SystemVerilog UVM: Enables engineers
WORKSHOP TYPES
On-site Workshops: Held at your facility, at a time
DAC-2014 ANNOUNCEMENTS
Sutherland HDLs acclaimed SystemVerilog train-
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INDUSTRIES SERVED
Automotive, Consumer Products, Defense, Industrial,
Healthcare, Networking, Security, Telecommunications
CONTACT INFORMATION
Sutherland HDL, Inc.
22805 SW 92nd Place
Tualatin, Oregon 97062
United States
Tel: +1-503-692-0898
info@sutherland-hdl.com
www.sutherland-hdl.com
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Mixel, Inc.
Mixels MIPI M-PHY
Organizations: GSA, MIPI Alliance
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distance (m)
TECHNICAL SPECS
Supports HS modes GEAR 1-3, series A and B with
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INDUSTRIES SERVED
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IP - Core
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exibility, DC balanced coding scheme, etc)
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can be traded-off against recovery time
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CONTACT INFORMATION
Mixel, Inc.
97 East Brokaw Road, Suite 250
San Jose, CA 95112
United States
Tel: 408-436-8500
marketing@mixel.com
www.mixel.com
4FNJDPOEVDUPS5FDIOPMPHJFTt
Byte Slice N
Byte Slice 1
Organizations: GSA
The TCI DDR 4/3 PHY is a high-performance, scalable
system using a radically new architecture that
continuously and automatically adjusts each pin
individually, correcting skew within byte lanes. This
state-of-the-art tuning acts independently on each
pin, data phase and chip select value. Read data
eye and gate timing are also continuously adjusted.
Automatic training is included for multi-cycle read
gate timing and write leveling, write data eye timing,
and internal and external (on DRAM) Vref setting.
DQS
Gate
Training
Gating/
Slave DLL
Multi-cycle
DLL
Write
Leveling
Read
Data Eye
Per Rank
Write
Data Eye
Per Rank
DQ
Jitter & Measurement
Clock
Deskew
Clock
Deskew
Training Interface
MEMORY CONTROLLER
Read FIFO
PLL
Byte Slice 0
Write FIFO
Command Address FIFO
Loop Back/
PRBS
Read/Write Training
Vref Training
Eye Diagram
TDR
SDR Tuning
FEATURES
Multi-cycle
DLL
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Flexibility
Timing Closure
Instrumentation
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IP - Core
IP - Core
Command/Address
EASY INTEGRATION
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The PHY has been designed from the ground up to
provide extensive, automatic and continuous tuning.
Each pin constantly adjusts separate read data eyes for
even and odd data phases, taking jitter into account.
Tuning is also done separately for each chip select
value. Pervasive tuning is the key to performance.
/0"44&.#-:3&26*3&%
The IP is delivered as a completely assembled hard
macro. It is fully tested and veried with state-of-theart timing analysis. Through a careful, joint process,
the I/O ring and package are co-designed prior to
PHY delivery, so that the PHY can be fully described,
veried and delivered as a whole. Tremendous
exibility is allowed and no assembly is required.
AUTOMATIC TRAINING
DDR4 systems require a great deal of training to
function properly. The TCI PHY, combined with
an appropriate controller, does all of the required
training with almost no user interaction. Low
overhead, incremental training can be done at the
users discretion to achieve even higher data rates.
Automatic training includes multi-cycle read gate
training and write leveling, and read and write
data eye centering. DDR4 systems require internal
Vref and external Vref (on DRAM) adjustment,
which the TCI PHY performs automatically
using very sophisticated algorithms.
TOOLS
TCI uses many proprietary tools to achieve
a level of quality, exibility and automation
unseen in mixed-signal design, and not
currently available in this type of hard IP.
-08&3*/(1"$,"(&"/%#0"3%$0454
Simpler and cheaper (fewer layer) chip packages and
boards can be designed by eliminating the need for
matched trace lengths, and by allowing for tremendous
exibility in the I/O ring/package co-development.
By intentionally skewing adjacent pins, lower cost
power delivery systems can be used, and wire
bond packages can be used at a higher speed.
MEASUREMENT RESOURCES FOR
$)"3"$5&3*;"5*0/
The PHY contains many resources that can be set
up to quickly characterize a new chip, a package or a
customers PCB board. Per pin measurements include:
DQ switching jitter, read DQS jitter, read data eye,
write data eye, Vref sensitivity and ight times. Pin
and pattern weaknesses can be found quickly, without
expensive lab equipment. Using an appropriate
controller, the DDR interface can be fully characterized
without CPU interaction.
IP - Core
IP - Core
TIMING CLOSURE
To make timing closure of the DDR 4/3 PHY to
the memory controller faster, two elements are
employed: 1) the interface from PHY to memory
controller is localized and optimized for easy
timing, and 2) the clock to the memory controller
is driven by the PHY and is internally deskewed,
minimizing clock-to-clock uncertainty.
TEST
The PHY includes a full speed read/write BIST, which
tests the complete read and write paths of every
pin simultaneously with pseudo-random data. The
PHY design kits include industry-standard boundary
scan chains and all the appropriate views for DFT.
CONTACT INFORMATION
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VIEWPOINT
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N
atural resource depletion and environmental challenges threaten all life. Can technologies like the
IoT help to reduce the human footprint on Planet Earth?
Technology is often seen as both a blessing and a curse. Many
people believe that technological advances only accelerate our
dwindling natural resources. How can science and technology
be used to reduce consumption on a global scale? To answer
these questions, John Blyler talked with Ramez Naam, a fellow at the Institute for Ethics and Emerging Technologies.
Naam is a computer scientist, former CEO of Apex nanotechnoloiges and Microsoft team leader. His latest book is titled;
The Infinite Resource The Power of Ideas on a Finite
Planet. JB
Blyler: Technology is often seen as a mechanism that
increases the depletion of resources, e.g., consumers
consume more not less with technology. Can technology
really be used to drive innovation and conserve resources?
Naam: Tech absolutely can increase
our resource use and our rate of pollution. But used intelligently it can
turn things around. In the 70s we
had massive smog. We were punching a hole in the ozone layer. We
had rivers literally catching on fire.
We had acid rain. Now the air and
water in the US are the cleanest theyve been in decades.
We invented new ways to run air conditioners and refrigerators that are allowing the ozone layer to recover.
And the average American uses less oil and less water
each year than at any time since the 1960s.
Look ahead and we can see more opportunities. We have
to beat climate change, and technology has to play a huge
role in that. People want energy. Civilization needs energy. So were going to need to keep innovating in things
like solar and wind and batteries and more ways to be
efficient in energy use so we can phase out coal and oil
and natural gas while keeping civilization moving.
All of that depends on progress in science and technology.
Blyler: What are some of the hard policy choices we
need to make in order to win the race between innovation and resource depletion?
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VIEWPOINT
into the atmosphere. Down the road, data from that sort
of device can be used to figure out the cheapest time to
charge an electric car, or even to give energy back from
the car to the grid, or to give the grid data about how and
when to balance load across sites.
The second case I think well see a huge impact of is environmental sensors. Sensors are getting cheaper, smaller, and less
power-hungry all the time. That means we can start to use
them in big ways to look for environmental toxins, to monitor the health of forests, to track endangered species and catch
poachers.
Any way you cut it, the ability to get more data about our world
and the objects in it is going to help us conserve.
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Blyler: Lets switch gears to talk about your works of science
fiction. What do you see as the difference between fiction and
non-fiction? Why does Sci-Fi apeal to you and most technical professionals?
Naam: Science fiction fires the imagination. It frees of from
the constraints of the current world we live in, and lets us imagine new ones. And thats tremendously exciting.
The big difference for me is where I focus. In my non-fiction I
tend to zoom out and tell the big picture story of how all the
pieces fit together. In my science fiction, theres a big picture
backdrop, but Im always telling the story through the lens of
people who are being swept along in some way that powerfully
affects them personally. The first rule in fiction is to never let
the reader put the book down.
Blyler: Thank you.
John Blyler covers todays latest high-tech, R&D and even
science fiction in blogs, magazine articles, books and videos. He is an experienced physicist, engineer, journalist,
author and professor who continues to speak at major conferences and before the camera. John is the Chief Content
Officer for Extensionmedia, which includes the brands
Chip Design, Solid State Technology, Embedded Intel and others.
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