FIGURE 21

8051 block diagram

The 8051 Microcontroller, 4e

By I. Scott MacKenzie and Raphael C.-W. Phan

2007 Pearson Education, Inc.

Pearson Prentice Hall
Upper Saddle River, NJ 07458

FIGURE 22

8051 pinouts

The 8051 Microcontroller, 4e

By I. Scott MacKenzie and Raphael C.-W. Phan

2007 Pearson Education, Inc.

Pearson Prentice Hall
Upper Saddle River, NJ 07458

FIGURE 23

Driving the 8051 from a TTL oscillator

The 8051 Microcontroller, 4e

By I. Scott MacKenzie and Raphael C.-W. Phan

2007 Pearson Education, Inc.

Pearson Prentice Hall
Upper Saddle River, NJ 07458

FIGURE 24

Circuitry for I/O ports

The 8051 Microcontroller, 4e

By I. Scott MacKenzie and Raphael C.-W. Phan

2007 Pearson Education, Inc.

Pearson Prentice Hall
Upper Saddle River, NJ 07458

FIGURE 25

Relationship between oscillator clock cycles, states, and the machine cycle

The 8051 Microcontroller, 4e

By I. Scott MacKenzie and Raphael C.-W. Phan

2007 Pearson Education, Inc.

Pearson Prentice Hall
Upper Saddle River, NJ 07458

FIGURE 26

Summary of the 8031 memory spaces

The 8051 Microcontroller, 4e

By I. Scott MacKenzie and Raphael C.-W. Phan

2007 Pearson Education, Inc.

Pearson Prentice Hall
Upper Saddle River, NJ 07458

FIGURE 27

Summary of the 8051 on chip data memory

The 8051 Microcontroller, 4e

By I. Scott MacKenzie and Raphael C.-W. Phan

2007 Pearson Education, Inc.

Pearson Prentice Hall
Upper Saddle River, NJ 07458

FIGURE 28

Multiplexing the address bus (low-byte) and data bus

The 8051 Microcontroller, 4e

By I. Scott MacKenzie and Raphael C.-W. Phan

2007 Pearson Education, Inc.

Pearson Prentice Hall
Upper Saddle River, NJ 07458

FIGURE 29

Accessing external code memory

The 8051 Microcontroller, 4e

By I. Scott MacKenzie and Raphael C.-W. Phan

2007 Pearson Education, Inc.

Pearson Prentice Hall
Upper Saddle River, NJ 07458

FIGURE 210

Read timing for external code memory

The 8051 Microcontroller, 4e

By I. Scott MacKenzie and Raphael C.-W. Phan

2007 Pearson Education, Inc.

Pearson Prentice Hall
Upper Saddle River, NJ 07458

FIGURE 211

Timing for MOVX instruction

The 8051 Microcontroller, 4e

By I. Scott MacKenzie and Raphael C.-W. Phan

2007 Pearson Education, Inc.

Pearson Prentice Hall
Upper Saddle River, NJ 07458

FIGURE 212

Interface to 1K RAM

The 8051 Microcontroller, 4e

By I. Scott MacKenzie and Raphael C.-W. Phan

2007 Pearson Education, Inc.

Pearson Prentice Hall
Upper Saddle River, NJ 07458

FIGURE 213

Address decoding

The 8051 Microcontroller, 4e

By I. Scott MacKenzie and Raphael C.-W. Phan

2007 Pearson Education, Inc.

Pearson Prentice Hall
Upper Saddle River, NJ 07458

FIGURE 214

Overlapping the external code and data spaces

The 8051 Microcontroller, 4e

By I. Scott MacKenzie and Raphael C.-W. Phan

2007 Pearson Education, Inc.

Pearson Prentice Hall
Upper Saddle River, NJ 07458

FIGURE 215

8032/52 memory spaces

The 8051 Microcontroller, 4e

By I. Scott MacKenzie and Raphael C.-W. Phan

2007 Pearson Education, Inc.

Pearson Prentice Hall
Upper Saddle River, NJ 07458

FIGURE 216

Two circuits for system reset. (a) Manual reset (b) Power-on reset.

The 8051 Microcontroller, 4e

By I. Scott MacKenzie and Raphael C.-W. Phan

2007 Pearson Education, Inc.

Pearson Prentice Hall
Upper Saddle River, NJ 07458