Introduction

Objectives

Vedic Multiplier

Compressors

Parallel MAC unit

Future plans

Parallel Multiplier - Accumulator Based on

Vedic Mathematics
Presented by : Jithin.s (cb.en.p2vld13013)
Guided by : Mr.E.Prabhu
Amrita Viswa Vidhyapeetham

08-December-2014

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Parallel Multiplier - Accumulator Based on Vedic Mathematics

Introduction

Objectives

Vedic Multiplier

Compressors

Parallel MAC unit

Future plans

Overview
1 Introduction
2

Objectives

3 Vedic Multiplier

RTL Schematic
4 Compressors

Higher Order Compressor

RTL 4:2 Compressor
Architecture
5 Parallel MAC unit
6 Future plans

s
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Parallel Multiplier - Accumulator Based on Vedic Mathematics

Introduction

Objectives

Vedic Multiplier

Compressors

Parallel MAC unit

Future plans

Introduction
In Vedic mathematics multiplier is designed by using Urdhwa
Tiryakbyam.
Urdhwa Tiryakbyam is the simplest and fastest multiplication
algorithm.
Compared to modified booth multiplier algorithm Vedic
multiplier has less power dissipation and high speed operation.
By replacing modified booth with Vedic multiplier in MAC
unit performance can be improved.

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Parallel Multiplier - Accumulator Based on Vedic Mathematics

Introduction

Objectives

Vedic Multiplier

Compressors

Parallel MAC unit

Future plans

Objectives

Design of Urdhwa Tiryakbyam based multiplier.

To Optimize Vedic multiplier by using compressors.
To implement parallel MAC unit by using compressor based
Vedic multipliers.
Compare the delay parameter of existing MBA based parallel
MAC with proposed architecture.

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Parallel Multiplier - Accumulator Based on Vedic Mathematics

Introduction

Objectives

Vedic Multiplier

Compressors

Parallel MAC unit

Future plans

Vedic Multiplier

Vedic partial product addition stage contains number of full

adders and half adders .
Parallel Multiplier - Accumulator Based on Vedic Mathematics

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Introduction

Objectives

Vedic Multiplier

Compressors

Parallel MAC unit

Future plans

RTL Schematic

RTL Schematic

Vedic multiplier
4 Bit
8 Bit

Area(um)
593.1
3026.8

Delay(ns)
1.97
3.82
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Parallel Multiplier - Accumulator Based on Vedic Mathematics

Introduction

Objectives

Vedic Multiplier

Compressors

Parallel MAC unit

Future plans

Compressors

(a) Normal addition

(b) 4:2 compressor

20 percent improvement of speed.

Parallel Multiplier - Accumulator Based on Vedic Mathematics

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Introduction

Objectives

Vedic Multiplier

Compressors

Parallel MAC unit

Future plans

Higher Order Compressor

Higher Order Compressor

By using 4:2 compressor : 7 XOR gate delay

By using Normal 5 bit adder : 9 XOR gate delay
Parallel Multiplier - Accumulator Based on Vedic Mathematics

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Introduction

Objectives

Vedic Multiplier

Compressors

Parallel MAC unit

Future plans

RTL 4:2 Compressor

RTL 4:2 Compressor

(a) RTL Schematic 4:2

Compressor
4:2
7:2

Area(um)
73.3
251

(b) RTL Schematic 7:2

Delay(ns)
Addition
.
.52
5 Bit
.93
10 Bit

Area
81.2
267

Delay
.7
1.17
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Parallel Multiplier - Accumulator Based on Vedic Mathematics

Introduction

Objectives

Vedic Multiplier

Compressors

Parallel MAC unit

Future plans

Architecture

Compressor based Vedic Multiplier

Vedic Mul.
4 Bit

Area(um)
593.1

Delay(ns)
Compressor
.
1.97
4 Bit

Area
585

Delay
1.77
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Parallel Multiplier - Accumulator Based on Vedic Mathematics

Introduction

Objectives

Vedic Multiplier

Compressors

Parallel MAC unit

Future plans

Parallel MAC unit

* Booth encoder
* good timing * decrease delay
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Parallel Multiplier - Accumulator Based on Vedic Mathematics

Introduction

Objectives

Vedic Multiplier

Compressors

Parallel MAC unit

Future plans

Vedic partial product addition

(b) Partial product addition

(a) Vedic encoder

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Parallel Multiplier - Accumulator Based on Vedic Mathematics

Introduction

Objectives

Vedic Multiplier

Compressors

Parallel MAC unit

Future plans

Vedic encoder

(b) Partial product addition

(a) Vedic encoder

Booth encoder Delay
Partial product addition

.47ns
Vedic encoder Delay
.
1.13ns
Partial product addition

Parallel Multiplier - Accumulator Based on Vedic Mathematics

.17ns
1.07ns

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Introduction

Objectives

Vedic Multiplier

Compressors

Parallel MAC unit

Future plans

Final delay comparison

100 numbers multiplication
(Vedic encoder delay + partial product addition delay )x100
(1.06+.17)x100 = 123ns
(Booth encoder delay + partial product delay )x100
(1.13 + .47)x100 = 160ns
Improvement in speed about 25 percent in proposed MAC unit.

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Parallel Multiplier - Accumulator Based on Vedic Mathematics

Introduction

Objectives

Vedic Multiplier

Compressors

Parallel MAC unit

Future plans

Future plans
Design of ALU by using the proposed MAC unit and Nikhilam
Sutra based squarer circuit.
Transistor level power optimization of MAC unit by using
Gate-diffusion input (GDI) technique.
Higher order bits MAC unit development and its FPGA
implementation.

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Parallel Multiplier - Accumulator Based on Vedic Mathematics

Introduction

Objectives

Vedic Multiplier

Compressors

Parallel MAC unit

Future plans

References
Young-Ho Seo, Member, IEEE, and Dong-Wook Kim, Member, IEEE, A
New VLSI Architecture of Parallel MultiplierAccumulator Based on
Radix-2 Modified Booth Algorithm, IEEE Transactions on very large scale
integration(VLSI) systems, Vol 18, No.2 February 2010.
Tiwari, Honey Durga, Ganzorig Gankhuyag, Chan Mo Kim, and Yong
Beom Cho.Multiplier design based on ancient Indian Vedic
Mathematics. In SoC Design Conference, 2008. ISOCC08.
International, vol. 2, pp. II-65. IEEE, 2008.
Sushma R. Huddar ,Sudhir Rao Rupanagudi, Kalpana M and Surabhi
Mohan,Novel High Speed Vedic Mathematics Multiplier using
Compressors. 2013 IEEE.
Devika Jaina, Kabiraj Sethi and Rutuparna Panda, Vedic Mathematics
Based Multiply Accumulate Unit .2011 International Conference on
Computational Intelligence and Communication Systems.
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Parallel Multiplier - Accumulator Based on Vedic Mathematics