LABORATORY EXPERIMENT # 4

"AN INTRODUCTION TO THE 555 INTEGRATED CIRCUIT TIMER"

Discussion: The 555 timer is an integrated circuit used in a multitude of precise timing and waveform
generation applications. In this lab, we will consider the 555 configured as an "astable multivibrator" and
as a "monostable multivibrator" or "one shot." Essentially, the "astable multivibrator" is a circuit that
outputs a quasi-rectangular waveform whose frequency and duty cycle are established by choice of
external resistors and capacitor (see Figure 1a). In comparison, the "one shot" receives an appropriate
trigger signal and outputs a single pulse whose duration is set by the selection of an external resistor and
capacitor (see Figure 1b). As with the 741 op-amp, the 555 timer requires a power supply and external
circuitry to achieve the desired operating characteristics. As illustrated in Figure 2, the chip has eight pins
that are identified in the following table.

out A

out A

cc!

cc

' Tpulse

0V-

0V
trigger time

Figure 1. (a) Astable Output

Figure 1. (b) Monostable Output

2
34 H

8
7
h

Figure 2. 555 Pin-Out

TABLE I: 555 Timer Pin Description

The supply voltage for the chip (pin 8) has the flexibility of being anywhere between +5V and +18V. The
output voltage (pin 3) can take on two states: a "high" state (~ 0.5V below the supply voltage) and a "low"
state (~ 0.1V). The ground pin (pin 1) will be tied to the common ground point used for the rest of your
circuit. Pin 4 (reset) will be tied to pin 8 during this lab; in other applications, it can be grounded to force
the 555 output to its "low" state. Pin 5 (control voltage) will be connected to ground through a 0.01uF
capacitor for this lab. The remaining pins 2 (Trigger), 6 (Threshold), and 7 (Discharge) constitute the
"heart" of the 555 timer and wil

require a closer inspection of the innards of the chip to understand how they will be merged with the
external circuitry.
A functional circuit diagram of the 555 timer is provided in Figure 3. Note that it consists of 3
high-precision equal-valued resistors, 2 comparators, an RS flip-flop, and a transistor connected to the
discharge pin. The non-inverting (+) and inverting (-) terminals of the comparators may both be viewed as
"infinite input resistance," implying that no current is allowed to flow in. As a consequence, the power
supply voltage (Vcc) and three 5k resistors are isolated, the voltage across each resistor necessarily being
Vcc/3. The voltage at the inverting terminal of the top comparator must then be 2V cc/3, and the voltage at
the non-inverting terminal of the bottom comparator is Vcc/3 (as shown in Figures 4 and 5). Recall that the
comparator output is a logical "high" when the non-inverting terminal voltage exceeds the inverting
terminal voltage (e.g., R=1) and is a logical "low" when the inverting terminal voltage is greater than the
non-inverting terminal voltage (e.g., R=0).
To next consider how the comparator outputs drive the RS flip-flop to then create the chip output,

Threshold

The comparators:
The first note about the 555 timer is the comparator segments. A comparator circuit is an opanip circuit that is
designed to compare an input with a fixed threshold voltage. The output will be high if the input voltage is
higher, or lower depending on the comparator's design, than the threshold voltage. In the 555 EC, if the
threshold pin input (pin 6) is higher than 2/3 Vcc. the output of CP1 i u p\ueon:pai;"itor> goes hiszh When the
triage: phi in put h love: than 1 .^Vce. then the output of pro (lower comparator) is high.

(pin 6)

The RS FUp-Flop( Control F/T):

The second segment of the 555 TC to analyze is the RS flip-flop When the output of CP2 is high, and thus the
output of CP1 is low. then the flip-flop has inputs, R=0 and S=l. This cause; the output of the RS flip-flop to be
high, or logic 1. Thus, the inverted output of the flip-flop will be logic 0, or low. When the output of CP1 is
high, and thus the output of CP2 is low. then the flip-flop has the inputs, R=l and S=0. This causes the output of
the RS flip-flop to be logic 0 and the inverted output of the flip-flop to be logic 1. The last input pin is CI (pin
'1), or reset. The reset feature of the RS flip-flop is active low. Thus, when the input to the reset pin is low, the
flip-flop's output will be logic 0 and the inverted output will be logic 1. To disable the reset feature, the CI input
of the flip-flop, and thus the reset pin of the 555 IC, should be tied high.

Trigger
(pin 2)

The Discharge Transistor^ Tl):

The last aspect of the 555 TC to be analyzed is the discharge transistor. When the output of the flip-flop is high,
and thus the inverted output is low, the transistor is off. Since, the transistor is connected to the inverted output
of the flip-flop, when the inverted output is low the transistor is off because mere is no current flowing in to the
base of the transistor. When the output of the flip-flop is low, and thus the inverted output of die flip-flop is
high, the discharge transistor turns on and thus current flows in through the discharge pin (pin 7) and to ground
through the discharge transistor.

Discharge
(pin 7)

Figure 3. Functional Diagram of 555 Timer

first we will assume that pin 2 (Trigger) and pin 6 (Threshold) are connected together and we will refer to
that voltage as Vtrig. Three comparator output possibilities exist: if V trig < Vcc/3, then the lower comparator
output is high (S=1) and the upper comparator output is low (R=0); if 2V cc/3 > Vtrig > Vcc/3, then both
comparator outputs are low (R=0 and S=0); and if V trig > 2Vcc/3, then the upper comparator output is high
(R=1) and the lower comparator output is low (S=0). Note, there is no way for both R and S to be high
since this would simultaneously require V trig to be greater than 2Vcc/3 AND less than Vcc/3. The RS flipflop is a "register" whose output is a function of the R and S inputs with the functional relationship
illustrated by the following truth table:

TABLE II: Flip-Flop Truth Table

The variable Qn+1 refers to the next state or output of the flip-flop given the indicated inputs. Thus, when
S=1 and R=0, the output is a logical one (the "set" condition). When R=1 and S=0, the output is a logical
zero (the "reset" condition). Finally, when R=0 and S=0, the output remains in the state that it was
previously in (the "memory" condition). Thus, if we had V trig < Vcc/3 so that the output was a logical one
and then we transition to a situation where 2V cc/3 > Vtrig > Vcc/3, the output would stay at logical one.
Similarly, if Vtrig > 2Vcc/3 so that the output is at logical zero, then a transition to a situation where 2V cc/3
> Vtrig > Vcc/3 would result in the output remaining at a logical zero.
Figure 4. Monostable Multivibrator Functional Circuit Monostable
Multivibrator
Operation
Monostable (meaning,
explained by referring

one stable state) is best

R

LED

to Figure 4. Here we

see that the discharge

terminal

connected

(pin

7)

is

to

the

Threshold pin. To
terminal, consider that

understand the discharge

there are two outputs of

the RS flip-flop, Q and

logical
complement

Q. The signal Q is the

(opposite) of Q. Thus, if Q

is a logical one, then Q

logical zero, the base of

is a logical zero. If Q is a
the transistor is grounded

and the transistor is off

- the discharge terminal
appears as an open circuit. However, if Q is a logical zero and Q is a logical one, then the transistor is
pushed into saturation and the discharge terminal appears as a low impedance path to ground. As Figure 4
illustrates with the capacitor tied to the discharge pin, this would enable us to rapidly dump the charge
from the capacitor CT .
Let's next explain how the circuit achieves a programmed timing interval. As the name implies,
the monostable has one stable state - the output being low. Thus initially with the trigger terminal held at
Vcc, S=0 and R must also be zero. To see that this is so consider that R=1
initially, the output would be low (the "reset" condition) and Q would be high. The transistor
2
would be "on," and the capacitor voltage would discharge, forcing Vthresh below VC = 3Vcc.
Therefore, R=0 and we would enter the memory state - Q would remain low and Q would stay high (the
transistor being "on" would maintain the capacitor voltage at zero). Now by shorting the Trigger terminal
to ground, we then force S=1 so that Q=1 (the "set" condition) and Q goes low. Thus, the discharge
transistor turns "off" and Vcc is allowed to charge the capacitor. By
immediately removing the Trigger terminal short, both R=0 and S=0 and the timer stays in the memory
state with Q=1. The output state does not change until the capacitor voltage charges up 2
to 3Vcc at which point R=1 and the output toggles back to the monostable state (the "reset"
condition): Q=0 and Q=1. The discharge capacitor is turned "on" and the capacitor charge is dumped to
ground. Both R=0 and S=0 and we then remain in the memory state with Q=0. The
2

time that the capacitor takes to charge from 0V up to 3Vcc is dictated by the time constant of the external
RC network. The charging of this capacitor is governed by:

f
V

C=VCC

10

-t \

1 e

TT

R C

2
Thus, if we set VC = 3Vcc and solve for the time, we get the following:

pulse = RTCT ln

1^

V3/

12

1.0986RTCT

Clearly, we can choose a combination of RT and CT to give us the required time delay. Finally, consider the
output of the circuit pictured in Figure 4. With the output normally low, the LED is "off." When the output
is high and the capacitor is charging, the LED is "on." Thus, we should anticipate that the LED will be
"on" for Tpuilse once we momentarily short the trigger input to ground.
Astable Multivibrator Operation
The "astable multivibrator" is configured by using the internal connection of the complement of the 555
output and the transistor connected to the discharge pin (pin 7) as shown in Figure 5. Note, when the 555
timer output is high (Q = 1), its complement (logical inversion) must be low
( Q = 0 ). With Q = 0, the internal transistor is "off" and pin 7 appears as an open circuit. When

the 555 timer output is low (Q = 0), its complement must be high (Q = 1). With Q = 1, the internal
transistor is "on" and pin 7 appears as a very low impedance path to ground (essentially a short circuit).
As shown in Figure 5, resistors RA and RB and capacitor CT are external components connected to pins 2
(Trig), 6 (Thresh), and 7 (Discharge) of the 555 timer. Once again, the two internal comparators of the
555 draw no current from the external circuit and simply appear as open circuits. The discharge pin will
appear as either an open or a short depending on the status of the RS flip-flop.

Green

Discharge

Figure 5. Astable Multivibrator Functional Circuit

With the power supply "off," the capacitor voltage is initially zero and thus R=0, S=1, Q=1, and Q = 0.
Therefore, the transistor is "off" and pin 7 appears as an open circuit. With the power supply "on," the
external circuit then simply consists of a charge path from the power supply, through R A and RB, into CT
(see Figure 6a). The capacitor voltage (which is also V trig) builds up exponentially. When it exceeds
Vcc/3, the flip-flop enters the memory state and the 555 output remains at Q=1. Once Vtrig builds up past
2Vcc/3, the previous truth table indicates that R=1, S=0,
Q=0, and thus Q = 1 . The internal transistor is "on" and the external circuitry is modified to the schematic
detailed in Figure 6b. Note, now the capacitor is disconnected from V cc and will discharge through R B to
ground (through pin 7). As Vtrig decays back below 2Vcc/3, the RS flip-flop transitions back to the memory
state and the 555 output remains at Q=0. Once Vtrig falls
below Vcc/3, the truth table indicates that R=0, S=1, Q=1, and Q = 0. The transistor is turned "off" and we
return to the original "charging" circuit (as pin 7 now appears as an open circuit). The circuit will continue
to oscillate between the "charging mode" when V trig builds from Vcc/3 to 2Vcc/3 and the "discharging
mode" when Vtrig decays from 2Vcc/3 and Vcc/3 (see Figure 7). During the "charge mode" the trigger
voltage is governed by:

V
trig

= V -2 V P
cc
3 cc

( A +Rb )t

Setting this equal to the "trip voltage" of 2Vcc/3 allows us to solve for the amount of time that the output is
in the logical one state:
TH = 0.693 (R A + RB )CT

RB

+
V

trig ^CT

16

trig

(a)

(b)

Figure 6. Astable Circuit During (a) Charge and (b) Discharge

trig TVcc 3
cc

18

out

V cc

t
Figure 7. Astable Capacitor and Output Voltage Waveforms During
the "discharge mode" the trigger voltage is governed by:

20

V g = 3 V cC e
n

BCT

Setting this equal to the "trip voltage" of V cc/3 allows us to solve for the amount of time that the output is
in the logical zero state:
TL = 0.693RBCT
By combining TH and TL, we can determine the period of the cyclic waveform produced
T = TH + TL = 0.693 (R A + 2RB ) CT The
reciprocal of the period is the frequency in Hertz

1.44

rri

The duty cycle of the output waveform is given by the ratio of the output high time to the output
period or
D

T (RA + 2RB )

Clearly, when RA=0 D=0.5 and when R =oo D=1. Thus, as currently configured, our astable multivibrator
can only produce duty cycles ranging between 0.5 and 1. Consider the output network of Figure 5. When
Q=1 and Vout = VCC , there is zero volts across the red LED (it's "off)
and
15V - 2.3V = 27mA flows through the green LED (it's "on"). When Q=0 and V^t = 0V,
A

470Q
there is zero volts across the green LED (it's "off) and
red LED (it's "on").

22

15V - 2.3V
= 27mA flows through the
470Q

INDUSTRIAL ELECTRONICS
LABORATORY EXPERIMENT # 4
"AN INTRODUCTION TO THE 555 INTEGRATED CIRCUIT TIMER"
BSEE V-1
MEMBERS:
CORLETO, RAND PAUL V.
MARTOS, LOUWILL DAIVE G.
MASCARINAS, MORIS I.
RAMOS, DARL JOSHUA L.

Section A. Building and Evaluating a Monostable Multivibrator

23

1. When the output of the 555 is "high", the voltage is approximately 15V. A conducting LED will
have a voltage drop of about 2.3V. If we desire to have 25mA of current flowing through the
conducting LED, what is the required value for RLED? Choose the closest 5% value for this
resistor and record the value here.

Rled =

2. If CT=22|iF electrolytic capacitor, find the theoretical resistance R to provide a 6 sec, 15 sec, and
30 sec delay.

3. Choose the nearest standard 5% resistor. Measure and record the value of the resistor in the
following chart. Also, record the anticipated time delay.

4. Build the circuit shown in Figure 8 (this is Figure 4 with the 555 chip pin-out inserted) and
complete the following chart. Note, the jumper needs only to be touched to ground to activate the
timing cycle. You should immediately take it out of ground so that the circuit can correctly cycle
into the memory state. The stop-watch should be used to measure the achieved delay. Use the
measured time delay to then estimate the actual capacitance. Repeat the 30 sec measurement 3
times. Have the instructor verify your circuit operation following the 6sec measurement.

Time Delay Theoretical

Resistance

Closest
Standard 5%
Value

Actual
Measured
Value

Anticipated
Time Delay

Measured
Time Delay

Calculated
Capacitor

6 sec
15 sec
30 sec
30 sec
30 sec

5. Comment in your postlab as to why we would prefer to rely on the 30-sec measurement more
heavily for the calculated capacitor value.

6. De-energize the proto-board.

Section B. Building and Investigating an Astable Multivibrator

24

1. Given D=2/3, f=0.167Hz and CT=22|iF electrolytic, solve for R A and RB (where RA must be
>100kQ). Make sure to show your work in the postlab. Build the astable multivibrator circuit
illustrated in Figure 9 (this is Figure 5 with the 555 chip pin-out inserted). Choose the closest
5% resistor values and measure and record the actual values.

25

2. Energize the circuit and complete the following chart. Have the instructor verify your circuit and
results.
Measured RA Measured RB Theoretical Period
Measured Period Theoretical Duty
Measured Duty

3. De-energize the proto-board and disassemble the circuit. Return all resistors, capacitors and timer
chips to the appropriate bin drawers. Return all proto-boards, proto-wire kits, and stopwatches to
the lab cabinets.

26