About COEP & E&TC Department

College of Engineering, Pune (COEP) is one

of the prestigious engineering colleges in
India. Established in 1854, it is the third oldest
engineering college in Asia. It is located in
Pune, Maharashtra. In 2004, the Institute was
granted complete autonomy by the State
Government & declared as Center for
Excellence in Technical Education. The
Institute now is an autonomous engineering
school with permanent affiliation to the
University of Pune.
The Department of Electronics and
Telecommunication Engineering (E&TC) has
been playing a vital role in producing
engineers & technologists of highest caliber
ever since it was established in the year 1948.
The department offers UG programme with 60
intake, two PG programmes with four
specializations (Digital Systems, VLSI &
Embedded Systems, Wired & Wireless
Communication, and Signal Processing) and
Research programmes.
About the Speaker
Mr. Pramod Sabnis obtained Bachelor of
Engineering (1988) from Walchand Institute
of Technology, Solapur and M. Tech (1991)
from Karnataka Regional Engineering
College, Suratkal.
Mr. Sabnis has Total industry experience of 23
years in Industrial Drives and Automation,
Chip Design, Training and Development.
He has 15+ years of experience in ASIC/ SoC
Physical Design.
Currently Mr. Sabnis holds the position of
Director ASIC/ SOC implementation at
Graphene Semiconductor. In this role, his
responsibility is to execute projects, mentor
the team in execution aspects of Chip design,

acquire exposure to newer areas and build the

competency.
Mr. Sabnis has been successful in building
teams from scratch at Qualcore, Sasken and
Infosys.
He has been involved in design, methodology
development, design-automation and project
management and was extensively involved in
Training and Development in VLSI Design.
Scope of the course
This FDP focuses on ASIC Physical Design.
Physical Design is the process of translating a
design from a logical/ behavioral domain to
physical domain. The physical design
engineer has to think terms of real wires and
real physical effects. This process starts with
estimation and analysis of the design. There
are a number of inputs that a physical design
engineer has to deal with for this analysis. The
analysis phase is followed by Implementation
phase where the design is actually taken
through the complex physical design flow.
This flow is run with strict PPA (power,
performance and area) goals. These goals are
sacro sanct and these have to be met in teh
stipulated time to market. The Implementation
phase is followed by Verification phase where
the PPA metrics are measured and design is
closed.
The above three phases make up the ASIC/
SoC physical design process.
The FDP intends to familiarize the participants
with the above process through theory and
labs. The FDP will also cover the different
inputs that a physical design engineer has to
deal with, their analysis and inferences.This
FDP will also include a session on TCL
scripting which is a MUST have skill in VLSI
field.

Objectives

One of the major challenges faced by the

teachers is in bridging the concepts to the
application and to bring out the practical
perspective for an effective teaching
learning interaction. This FDP is designed
1. To enable teachers to bridge this gap
through a series of handson illustrative
teachinglearning
activities/experiments
that will help connecting the theoretical
concepts to the industry relevant application
perspective as well as practices.
2. To provide an overview of the topics with
emphasis on opportunities for getting ready to
handle industrial application requirement.
3. To provide Hands-on experience in
Cadence tool.
Broad Topics to be covered
This FDP will deal with complete Place and
Route flow of a design
This will involve theory and labs on:
a) Floor planning
b) IO planning
c) Power planning
d) Standard Cells Placement
e) Different clock structures and CT Synthesis
f) Routing
g) TCL Scripting
Resource person
Mr. Pramod Sabnis
Director, ASIC/SOC Implementation,
Graphene Semiconductor Services
Pvt.Ltd, Bangalore

Registration form
1. Name: ____________________________
2. Category: Academic / Industry
3. Organization: ______________________
4. Address__________________________
_________________________________
_________________________________
5. Professional Experience
Teaching/Industry__________________
6. Research interest
________________________________
________________________________
7. Email Id: _______________________
8. Mobile Number: __________________
9. DD No. & Bank: __________________
(DD should be drawn in favor of DIRECTOR,
COEP, payable at Pune)

Declaration by the candidate

The given information is true to the best of my
knowledge.
I agree to abide by the rules and regulations
governing the programme. If selected, I shall
attend the course for the entire duration.
Date:
Place:
Signature:
Important Dates to Remember:
Last date for registration:
Intimation date:

18/01/2016
20/01/2016

The brochure, application form & technical

details can also be downloaded from college
website: www.coep.org.in

Details of Registration
Faculty Rs 10,000/Industry personnel - Rs 15,000/Research scholar- Rs 5000/The registration fee includes cost towards
course material, lunch, and refreshment.

TEQIP II sponsored
One week
Faculty Development Program
on

VLSI CAD using Cadence tool

(Jan 22-26, 2016)

Registration
Registration for the FDP can be made by
sending the duly filled application form along
with Demand Draft payable at Pune.
Eligibility:
1. Faculty working in Engineering Colleges/
Polytechnic colleges
2. Engineers from R&D Organizations
/Industries.
3. Research Scholars
Note:
1. Only 20 participants will be selected on first
come first served basis.
2. Intimation of selection /confirmation will be
only through Email till 20 Jan 2016.
3. If you are selected, the fee paid will not be
refunded under any circumstances.
4. If required, ACCOMMODATION for the
participants will be suggested.
5. No TA/DA will be provided to any participant

The duly filled application form along with

DD is to be sent to:
Ms. Vanita Agarwal
Department of E&TC Engineering
College of Engineering, Pune (COEP)
Wellesley Road, Shivajinagar, Pune-411005
Phone: 020-2550 7616, 09665366195
Fax: 020-2550 7299
Website: www.coep.org.in
Email: vsa.extc@coep.ac.in

Organized by

Department of Electronics &

Telecommunication Engineering,
College of Engineering, Pune (COEP)
(An Autonomous Institute of the
Government of Maharashtra)

Course Coordinators
Ms Vaishali V Ingale (8149477127)
Associate Prof., E & TC, COEP
Ms. Vanita Agarwal (9665366195)
Assistant Prof., E & TC, COEP