You are on page 1of 5

Analysis of Static Noise Margin of 6T SRAM

in 65nm CMOS technology


Kunwar Tarun
Under guidance of

Mohammad Hashmi, Assistant Professor(ECE),IIITD


Abstract This paper examines the factors that

affect the Static Noise Margin (SNM) of a 6T


Static Random Access Memory (SRAM) cell
designed in 65-nm CMOS. In this paper, the read
and write operation of SRAM cell is performed
and noise margins are obtained while varying
several parameters that affect SRAM operations.
These parameters are temperature, cell ratio,
supply voltage.

I.

INTRODUCTION

Continuous Scaling of CMOS technology leads to


incorporation of small size modules under a small single area
and leads to the growth of System on Chip (SoCs). Due to this
small area constraint, noise originating in one section of power
line or any other section will severely affect the other parts of
on chip design. One example of such system where noise
effects are of great concern is the SRAM because it is made up
of large number of minimum sized devices which are sensitive
to noise. Stability of 6T SRAM is major concern that is
evaluated by analyzing Static noise margin (SNM) of SRAM.
For analysis of 6T SRAM noise margin, noise voltage is
introduced between cross coupled inverter to flip the output of
cell.
The inverter arranged in cross-coupled maintains bistable
state and output of the bit-cell retain their data. When the
noise voltage introduced between these inverters increases,
stability of 6T SRAM degrades, and leads to the fluctuations
at the output of bit-cell. The SNM quantifies the allowed
levels of these noise voltages and thus the ability of these
inverters to retain their state in the presence of noise. Basic 6T
SRAM cell is shown in FIG 1.
The goal of this paper is examine the read and write operation
of 6T SRAM designed in 90nm technology and analyze the
Read Margin, Write Margin, Static current noise margin
(SINM) and Write current noise margin(WINM) in presence
of varying circuit parameters such as temperature, power
supply , cell ratio.
II.

bit lines. The stability of Read operation depends upon the cell
ratio, which should be sufficiently large to obtain the read
stability. Cell ratio is the ratio of size of the pull-down
transistor to the size of access transistor.
.

READ OPERATION

In the read operation, both the bit line and bit line bar is pre
charged to VDD and then the word line is enabled. The bit line
and bit line bar will get the voltages of out and out bar of bit
cell. In this read operation, stability of 6T SRAM is major
concern, as the output of bit cell should not flip and must hold
their original values, while transferring their node voltages to

FIG 1. Basic 6T SRAM


Read margin
The cell is most vulnerable when accessed during a read
operation because it must retain its state in the presence of the
bit line pre-charge voltage. If the cell is not designed properly,
it may change its state during a read cycle which results in
either a wrong data being read or a destructive read where the
cell changes state. Thus, the worst noise margin is obtained
during read access . At the start of read access, the bit lines are
pre-charged to VDD and then the word lines are activated to
access the cell. The node having the 0 data pulls one of the
bit lines to GND causing a voltage swing which is read by
sensing circuits as shown in FIG 2.

voltage sweep is applied at one of the nodes and the current


supplied by the source is measured. The positive peak current
is the SINM or the static current noise margin which is defined
as the maximum current that can be injected in the cell to
change its state. The negative peak current is the WINM or the
write current noise margin defines the amount of current
needed to write to the cell with both bit lines charged to VDD.

FIG 2.

Equivalent SRAM circuit during read Operation


III.

WRITE OPERATION

In write mode, value to be written in the cell is stored in bit


line and bit line bar. Then the word line is activated. Due to
this, data is written in SRAM cell. For write stability, size of
the access transistor must be greater than the pull up transistor.

FIG 4. N-Curve circuit and N-curve


FIG 3. Equivalent SRAM circuit during write operation
V.
Write Margin
The write noise margin is defined as the minimum bit line
voltage needed to flip the state of cell. During a write
operation, the input data are sent to the bit lines, then the word
lines are activated to access the cell. The bit line that is
charged to 0 pulls the node of the cell storing 1 to 0
causing the cell to flip state. The circuit is the same as in the
measurement of read margin. It shows the inverter with 1 at
its output and its bit line is connected to GND to simulate a
write 0 to that node as shown in FIG 3.
IV.

N-CURVE METHOD

This is the method to measure the noise margin of the SRAM


cell is using the N-Curve. It is measured by clamping both
word lines and bit lines to VDD like in a read operation. A

SIMULATION OF STATIC NOISE


MARGIN

A. Effect of Cell Ratio


Read operation of a 6T SRAM cell is affected by the cell ratio.
Thus, the SNM is also affected by this ratio. The cell ratio is
defined as ratio between the sizes of the NMOS transistors of
the inverters and the NMOS access transistor. This ratio
affects the read operation of SRAM. The cell ratio is
W2/W4(from FIG 1) where W2 is the size of the pull down
transistor which determines the strength of the node 0 to pull
the pre charged bit line to GND and W4 is the size of the
access transistor. The larger the cell ratio, the larger the pull
down network which means that the node storing 0 is more
robust from noise introduced by the bit line pre charged
voltage during read. The node voltage retains its value because
of the strong pull down network. The N-Curve measurements

also show an increase in the read noise current as the cell ratio
is increased which means that the current required to change
the state of the cell also increases.
CONCLUSION
As the cell ratio increases, the stability of 6T SRAM improves
and both read and write margin increases. In this paper, cell
ratio varies from 0.5 to 2.5 in 0.5 increments and both read
and write margin improves.
B. Effect of Supply Voltage
In order to decrease power consumption of digital circuits,
supply voltage scaling is commonly employed. The noise
Margin of SRAM cell is also a function of the supply voltage.
Although the leakage current increases, but the supply
required to withstand will overpower noise variations to give
stable output. Due to this voltage scaling will be limited to
levels such that noise margin is still greater than the expected
noise in the circuit.
CONCLUSION
As the power supply increases, the write margin and read
margin increases. This result is expected since as the supply
voltage decreases, the effect of noise present becomes more
significant thus the circuit is less stable. The supply voltage
also defines the voltage swing limits at the output nodes of the
inverters. Due to this voltage scaling will be limited to levels
such that noise margin is still greater than the expected noise
in the circuit.

FIG 5. READ OPERATION


As the word line is activated after pre-charging bit lines to
VDD ,the bit line and bit line bar reads the value of bit cell
output nodes as shown in FIG 5.

C. Effect of temperature variations


The effect of temperature on the noise margin is almost
insignificant it is shown by using temperatures -40C, 27C,
100C and 125C. As the temperature increases, the static
current noise margin decreases thus the current required to flip
the state of the cell is decreased. This means that the cell
becomes less stable as the operating temperature is increased.
CONCLUSION
As the temperature increases, there is slight decrease in read
and write margin in 6T SRAM cell.
VI.

SIMULATION RESULTS

FIG 6. WRITE OPERATION


As the word line is activated after providing the data to bit and
bit line bar i.e. 0 and VDD , the output node of SRAM cell
flips and data is written to 6T SRAM cell as shown in FIG 6.

FIG 8. Effect of cell ratio variations


As the cell ratio increases, the stability of 6T SRAM improves
and both read and write margin increases. In this paper,
cell ratio varies from 0.5 to 2.5 in 0.5 increments and both
read and write margin improves as shown in FIG 8.

FIG 7. N-CURVE
The N-curve shown in FIG 7. is obtained for VDD = 1.2V ,
temperature =27C and cell ratio = 2 . The value of different
noise margins obtained from N-curve are shown in below
table
STATIC CURRENT
NOISE MARGIN
(SINM)

304.63uA

WRITE CURRENT
NOISE MARGIN
(WINM)

34.72Ua

READ MARGIN

494.179mV

WRITE MARGIN

552.268mV

The supply voltage also defines the voltage


swing limits at the output nodes of the inverters. Due to this
voltage scaling will be limited to levels such that noise margin
is still greater than the expected noise in the circuit
REEFRENCES
[1] Christiensen D.C. Arandilla, Anastacia B. Alvarez, and
Christian Raymund K. Roque ,"Static Noise Margin of 6T
SRAM Cell in 90-nm CMOS",2011 UKSim 13th International
Conference on Modelling and Simulation.
[2] Sangeeta Singh, Vikky Lakhmani, "Read and Write
Stability of 6T SRAM", International Journal of Advanced
Research in Electronics and Communication Engineering
(IJARECE)
Volume 3, Issue 5, May 2014.
[3] Abhishek Agal, Pardeep, Bal Krishan, "6T SRAM Cell:
Design And Analysis", Int. Journal of Engineering Research
and Applications www.ijera.com ISSN : 2248-9622, Vol. 4,
Issue 3( Version 1), March 2014, pp.574-577.
[4] Rajni Sharma 1, Sanjay Chopade, "Stability Analysis of 6T
SRAM at 32 Nm Technology", International Journal of
Innovative Research in Science, Engineering and Technology
(An ISO 3297: 2007 Certified Organization) Vol. 3, Issue 5,
May2014

FIG 9. Effect of power supply variations


As the power supply increases, the write margin and read margin increases. This result is expected since as the supply voltage
decreases, the effect of noise present becomes more significant thus the circuit is less stable. The supply voltage also defines the
voltage swing limits at the output nodes of the inverters. Due to this voltage scaling will be limited to levels such that noise
margin is still greater than the expected noise in the circuit.

You might also like