UNIT I

1) Do the required conversions for the following numbers:

a) (BF8)16=(__)10
b) (1000)10=(__)8
c) (377)8=(__)16
2) What are different ways of representing signed binary numbers? Explain with
examples.
3) Solve the following equation using K map minimization technique. Draw the
diagram for the output:
Z=f(A,B,C,D)=4 root 12 M(0,1,6,7,8,9)
4) Perform the following operations:
a) (FFFF)16 (10000)10=(__)10
b) (756)8+(365)8=(__)16
c) (658)16+(975)16=(__)16
d) (1011.101)2=(__)10
5) Solve the following equation using corresponding minimization technique.
Draw the diagram for the output:
Z=f(A,B,C,D)= summation m(2,4,6,11,12,14)+d(3,10)
6) What are the advantages of Quine McClusky minimization technique over K
map?
7) Do the required conversions for the following numbers:
a) (1FFF)16=(__)10
b) (1024)10=(__)16
d) (36)8=(__)16
8) Which gates are known as Universal Gates? Justify using examples.
9) Solve the following equation using K map minimization technique. Draw the
MSI design for the output:
Z=f(A,B,C,D)=summation m(1,3,6,7,12,13)+d(0,2,8,9)
10)
Perform the following operations:
a) (8085)16 (1000)10=(__)10
b) (777)8+(77)8=(__)16
c) (888)16+(999)16=(__)16
d) (1001.10)2=(__)10
11)
Solve the following equation using corresponding minimization
technique. Draw the MSI design for the output:
Z=f(A,B,C,D)= pi M(1,3,5,6,7,10,11)+d(2,4)
12)
State and prove any two theorems of Boolean Algebra.
13)
What will be the Excess3 code of any given 4bit grey code number?
Show the truth table.
14)
Express the following numbers in binary. Show your step by step
equation and calculation:
a) (1010.11)10
b) (428.10)10
15)
Perform the following Hexadecimal subtraction and show your answer
in Hexadecimal only:
a) (387)16-(2AC)16
b) (587)16-(4EB)16

16)
What is the max. equivalent decimal number represented by its max.
equivalent 4digit Hex number? Also convert the following Hex number to get
its equivalent octal and decimal:
a) (ABC)16
b) (DEF)16
17)
What is De Morgans theorem? Solve the following using minimization
technique:
a) Z=f(A,B,C,D)= summation (0,2,4,7,11,13,15)
b) Z=f(A,B,C,D)=pi(1,2,3,6,8,10,12,14)
18)
Convert the following octal numbers into equivalent decimal and hex:
a) (555)8
b) (777)8
c) Solve the following equation using corresponding minimization technique.
Draw the MSI design for the output:
Z=f(A,B,C,D)=pi(2,7,8,10,11,13,15)
Z=f(A,B,C,D)=summation(0,3,4,9,10,12,14)
19)
Express the following numbers in binary. Show your step by step
equation and calculation:
a) (110.110)10
b) (234.234)10
20)
Convert 4-bit grey code into corresponding BCD code. Show truth table
and MSI circuit.
21)
Design and explain in detail 4-bit input grey code to7-segment BCD
code conversion technique. For this design use K map reduction MSI circuit
for each segment of display.
22)
Enlist various code conversion methods.
23)
Express the following numbers in binary. Show your step by step
equation and calculation:
a) (7762)8
b) (432A)16
c) (2946)10
d) (1101.11)10
24)
What will max 4-digit equivalent Hex number for 4-digit max. decimal
number? Also perform the following subtraction:
(7048)10-(07A8)16
25) For a max 3-digit octal number obtain equivalent hex, binary, decimal
number.
26) Perform the following operations and show answers in hexadecimal,
decimal and octal format:
a) (7FF)16-(777)8
b) (2078)16-(3FF)16
c) (1111)10-(1111)2
d) (3258)8+(FFF)16

e) (1110)2+(1110)10
27) Design and explain in detail 4-bit gray code to 5-bit BCD code conversion.
For this design use K
map reduction and MSI circuit using basic gates.
28) Explain rule for any sequence binary to grey code conversion.

UNIT II
1) Define the following terms related to logic families. Mention typical values for
standard TTL family:
a) Propagation delay
b) Fan-out
c) VIL, VIH, VOH
d) Fan-in
e) Power dissipation
f) Noise margin
2) Draw the structure of two input CMOS NAND gate. Explain its working.
3) List differences between CMOS and TTL.
4) Explain the working of two input TTL NAND gate with open collector output.
Consider various input, output states for explanation.
5) Which specification of logic families are significant in CMOS TTL interfacing?
Explain the same when CMOS drives TTL.
6) Draw the structure of CMOS inverter gate. Explain its working.
7) List differences between open drain and wired logic CMOS.
8) Explain the working of two input TTL NAND gate with active pull up. Consider
various input, output states for explanation.
9) Which parameters are significant while interfacing TTL and CMOS? Draw and
explain TTL driving CMOS gate.
10)
With the help of Quine McClusky technique determine the PI for the
following equation:
Z=f(A,B,C,D)= summation(0,1,3,4,6,8,10,12,14)
11)
Explain standard TTL characteristics in brief.
12)
Draw 2-i/p standard TTL NAND gate circuit and explain operation of
transistor with suitable conditions and truth table.
13)
Compare TTL and CMOS logic family. Also draw CMOS-NOR gate.
14)
With the help of Quine McClusky technique determine the PI for the
following equation:
Z=f(A,B,C,D)= summation(0,3,8,9,10,12,15)
15)
Draw 2-i/p standard TTL NAND gate with totem pole. Explain operation
of transistor with suitable conditions and truth table.
16)
What is logic family? Explain types of logic families in detail.
17)
Explain for IC 74LSXX various characteristics in brief.
18)
Draw and explain the design of 3-i/p standard TTL NAND gate circuit.
Also explain various input, output states with transistor ON/OFF condition.
19)
Explain working of 2-i/p CMOS NOR gate.
20)
Explain working of 2-i/p CMOS OR gate.

UNIT III
1) How is BCD addition different from binary addition? What is the use of 7483
chip? Draw and explain nines complementer used in BCD subtractor using
7483.
2) Design 16:1 multiplexer using only one 8:1 multiplexer and required discreet
logic gate for the following function:
F(A,B,C,D)= summation m(0,4,6,9,12,13)
3) What do you mean by parity? How does IC74180 work? Design 9 bit even
generator using the same.
4) Implement two bit comparator using 1:16 demultiplexer (active low output).
Draw the truth table of two bit comparator and explain the design in steps.
5) Design 4-bit binary to gray code converter. State the applications of gray
code.
6) Explain the working of magnitude comparator 7485. Discuss the truth table
for the same.
7) Design 8:1 multiplexer using only one 4:1 multiplexer. Explain with the help of
the truth table. Implement the function:
F(A,B,C,D)= summation m(1,3,7)
8) Describe the working of BCD adder using 7483 with the help of diagram.
9) Draw and explain 4-bit BCD subtracter using IC 7483. Explain subtraction for
(9-5)BCD and (4-7)BCD
10)
Design 12:1 multiplexer using only one 4:1 multiplexer. Explain the
truth table of the circuit.
11)
Explain Demux(1:8) as a full adder and full subtractor. Show your
design.
12)
Draw and explain 4-bit BCD adder using IC 7483. Explain any two BCD
operations.
13)
Explain the working of cascaded mode magnitude comparator using IC
7485.
14)
Design 14:1 multiplexer using only one 4:1 multiplexer. Explain the
truth table of the circuit.
15)
Draw and explain 4-bit BCD adder using IC 7483. Explain subtraction
for (9+5)BCD and (7+2)BCD.
16)
Explain decoder (1:8) as full adder and full subtractor. Show your
design.
17)
Design 28:1 multiplexer using 8:1 multiplexer. Explain the truth table of
the circuit.

UNIT IV
1) Design binary sequence generator to generate binary sequence 11010,
1101011 using MS JK flip flop. How to avoid lockout condition in designed
sequence generator?

2) Assume 16 MHz clock in a system. How will you divide this frequency by a
factor 4? Explain your logic with suitable circuit diagram.
3) Draw basic internal architecture of IC 7490. Design a divide-by-20
counter using same. Design MOD 7 and MOD 98 and MOD 27 and MOD
17 and MOD 24 using IC 7490.
4) Draw and explain 4 bit bidirectional shift register.
5) What is SR flip flop? Convert the basic SR flip flop into:
a) JK-FF
b) T-FF
c) D-FF
6) What is the difference between synchronous counter and asynchronous
counter? Design 3 bit synchronous up-counter using MS JK FF.
7) Design sequence detector using D FF to detect the following sequence
based on Mealy machine: 1101
8) explain the difference between combinational and sequential circuit.
9) Explain Johnson counter with design for initial state 0110. From initial
state explain and draw all possible states.
10)
Explain with neat diagram working of parallel in serial out 4 bit shift
registers.
11)
Applications of shift registers. Also explain 4 bit Johnsons counter.
12)
Explain ring counter with design having initial state 01011 and 10110
from initial state explain all possible states in that ring.
13)
Draw 4 bit asynchronous counter.+
UNIT V
1) Draw an ASM chart, state table and state diagram for synchronous circuit
having the following description: The circuit has a control input X, clock and
outputs A and B. if X=1 on every clock rising edge the code BA changes from
00-01-10-11-00 and repeats. If X=0 circuit holds the present state.
2) What is difference between signal and variable in VHDL? Explain with
example.
3) Write VHDL description of full subtractor using dataflow and structural
modeling.
4) State and explain basic components of ASM chart.
5) Explain ASM technique of designing the sequential circuits in detail. How does
it differ from conventional flow chart?
6) Describe different modeling styles of VHDL with suitable examples.
7) Give the features of ASM. Draw the ASM chart for 2 bit binary up-counter with
an enable signal e such that: for e=0 disable counting
e=1 enable counting.
8) With the help of suitable example, explain the data objects: constant,
variable, signal and file.
9) A sequential ring counter with present state 0001. The circuit also have an
input X. if X=0 then circuit will show next output else for x=1 it will show
initial state 0001. Draw an ASM chart and state table for this circuit to
generate the output using mux controller method.

10)
With the help of an ASM chart design a modulo-6-up date counter.
11)
Write VHDL code for 4 bit full adder.
12)
Write VHDL code for 4:1 mux.
13)
Explain entity architecture declaration for 2 bit NOR and AND gate and
NAND gate.
14)
Design ASN chart for 3 bit octal number sequence with up-down
conditions.

UNIT VI
1) Explain steps for designing circuits using CPLD.
2) Write a note on FPGA.
3) Explain operations performed in various phases of instruction execution in
microprocessor based system.
4) Differentiate between FPGA and CPLD.
5) Define PLD and mention different types of PLD. Implement the following
functions using PAL: F(A,B,C,D)= summation m(0,1,3,15)
6) Draw and explain architectural diagram of 8085 microprocessor.
7) What do you mean by FPGA? Explain the details of internal architecture of
FPGA.
8) Draw the block diagram of simple microprocessor based system and explain
the functions of each block.
9) Explain the design of FPGA.
10)
Explain in brief working of ALU, program counter, instruction register
Address bus, Data bus and Control bus assuming a basic operation.
11)
Design using PLD a 3:8 decoder.
12)
Using PLD design a 4 bit gray code counter.
13)
Explain interfacing of memory with microprocessor.
14)
Explain execution of a sample program.