Capacitive Interpolated Flash ADC Design Technique

He Tang, Hui Zhao, Xin Wang, Lin Lin, Qiang Fang,

Jian Liu and Albert Wang*

Siqiang Fan and Bin Zhao

Fairchild Semiconductor, Inc., Irvine, CA, USA
Zitao Shi and Yuhua Cheng
Peking University, Beijing, China

Dept. of EE, University of California, Riverside, USA,

aw@ee.ucr.edu
AbstractAnalog-to-digital converter (ADC) is a key component
electronic system. Flash ADC is widely used in high-speed
systems. However, practical flash ADC design is very challenging
where experience plays a significant role. ADC design involves in
many factors at different levels including architecture, circuit,
device and technology. This paper reports a quantitative design
methodology for capacitive interpolated flash ADCs, which
establishes a design matrix that links ADC chip performance
with architecture, block circuit, devices and process parameters.
Complex relationship among critical ADC specs, such as,
sampling speed, interpolation factors, number of stages, preamplifier bandwidth and transistor parasitic effects, etc, are
described. An accurate dynamic power analysis technique is
depicted. This flash ADC design method was validated using
several designs in 90nm and 130nm CMOS technologies.

very complicated for capacitive interpolated ADC due to the

capacitor charging and discharging effects that consume
varying, yet some kind of large dynamic power if the sampling
speed and resolution bit increase. However, most ADC power
analysis techniques reported focus on static power only [5, 6].
In this paper, we present a new quantitative design matrix
technique for capacitive-interpolated flash ADC design, which
provides a quick, accurate and practical bottom-up flash ADC
design procedure that addresses general ADC performance
specs including the dynamic power analysis. The paper is
organized as following: Section II discusses details of the new
design methodology; Section III focuses on dynamic power
analysis; Section IV presents design verification results,
followed by conclusions.

Keywords-flash ADC; capacitive interpolation; CMOS.

I.

INTRODUCTION

Nowadays, ADC has become a basic and indispensable

building block for most electronics systems. Among all kinds
of ADCs, flash ADC features low to medium resolution and
very high sampling speed (sampling rate over Gsps in CMOS)
has found widely spread applications in UWB systems, disk
drivers and optical communications, etc [1]. In principle, an
m-bit flash ADC consists of 2m-1 comparators and a resistor
ladder with 2m equal segments. However, due to the massive
parallelism or lack of front-end sampling, the number of
comparators in flash ADCs will grow exponentially with the
resolution bits that result in huge chip size, high power
consumption and large input capacitance, etc [2]. Hence,
interpolation technique has been widely used to resolve these
problems for flash ADCs.
In practical flash ADC designs, it is very important to fully
understand the influences of various design factors, e.g.,
interpolation, on the performance of the whole flash ADC
chips. This means a quantitative design matrix and direct
mapping between the ADC chip performance specs (e.g.,
resolution, sampling speed, size and power dissipation) and
the lower level factors, such as, process parameters, device
parameters, block circuit schematics and parameters, as well
as ADC architectures, are required. However, such a
quantitative flash ADC design methodology does not exist yet,
although some discussions on design trade-offs were reported
[3, 4]. Consequently, practical flash ADC design is still an
experience-based and time-consuming task, which can neither
be easily evaluated nor be readily optimized for the best
overall chip performance. In addition, power consumption of
flash ADC increases dramatically against sampling speed.
Unfortunately, since high-speed ADC power estimation is

978-1-4244-8631-1/10/$26.00 2010 IEEE

INTERPOLATED FLASH ADC DESIGN MATRIX

II.

A. Cascaded Multi-Stage Bandwidth Reduction

For a multi-stage (i.e., n stages) cascaded amplifier network,
assuming all stage are identical to each other, the overall
network frequency response is expressed as,
n

H Z 

Let

> H  Z @

H1 Z   H n Z 

H Z 

AV

1  j Z Z1, L

AV


1  j Z Z1, L

1
2

AV

, one obtains the

overall n-stage network bandwidth as,

1

Z 3 dB , total

Z1, L 2 n  1

Z1, 3 dB 2 n  1

(2)

Eq. (2) readily shows that the overall bandwidth of a multistage cascaded amplifier network shrinks monolithically.
B. Bandwidth Analysis for Interpolated Flash ADCs
Consider an interpolated flash ADC consisting of preamplifier stages and the comparator stage, the number of preamplifier stages varies upon ADC resolution bits and its
interpolation factors. Normally, higher resolution results in
more stages; while a larger interpolation factor reduces the
stage numbers. Detailed structure for a practical 4bits
capacitive interpolated flash ADC is given in Figs. 1&2. Fig. 1
depicts pre-amplifier influences on the flash ADC, which
consists of edge pre-amplifiers and interpolated pre-amplifiers.

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interpolation multi-stage pre-amplifier chain with largest load

in the middle section has the slowest signal path and hence
determines the flash ADC sampling speed, as illustrated in Fig.
2. Note that the last stage comparators have little impact on
ADC speed, because these comparators are normally dynamic
latches, which serve to compare signals at very high speed and
are much faster than the pre-amplifiers. Therefore, ADC speed
bottleneck is with interpolation pre-amplifiers.
Fig. 3 shows the equivalent loading circuit for an example
interpolated pre-amplifier loaded by three sampling capacitors
and three succeeding pre-amplifiers. Rout and Cp are output
resistance and parasitic capacitance of the interpolated preamplifier, respectively, where Cp includes parasitic Cdg, Cds, Cdd
and Cdb. Cs is sampling capacitance. Cm is Miller capacitance
and Cgs is gate-source capacitance of the succeeding preamplifier. All pre-amplifiers are identical. The load resistance
is obviously Rout and the load capacitance is calculated by,

Fig. 1 ADC interpolation has different paths including interpolation

amplifiers in middle and pre-amplifiers at edge.

Fig. 3 Equivalent loading circuit of an interpolated pre-amplifier.

CL,central

C p  3 Cs //  Cm  Cgs ,in 
C p  3 Cs // 1  AV  Cgd ,in  Cgs ,in



The bandwidth of the interpolated pre-amplifier is obtained

as Z-3dB, central 1  Rout CL , central  . Apply it into Eq. (2), one can
get overall frequency bandwidth for the capacitive interpolated
flash ADC as,

Fig. 2 Middle path is the slowest channel due to large load.

As discussed, the cascaded pre-amplifier network, used for

interpolation, will reduce the overall ADC bandwidth due to
increase of stage number. On the other hand, it is realized that
pre-amplifiers at different locations have different loading
effects of capacitance and resistance. Obviously, each
interpolated pre-amplifier is loaded by three succeeding preamps (in practical design, a sampling capacitor is applied to the
pre-amplifier); while each edge pre-amplifier has a lighter load
coming from two succeeding pre-amplifiers. Thus, it is easy to
understand that the middle interpolation pre-amplifiers will
definitely have larger time constants and hence narrower
bandwidth. Therefore, considering the two factors together, the

Z3 dB , ADC

>

2n 1

Rout C p  3 Cs //  Cm  C gs ,in 



From Eq. (4), it is obvious that the overall bandwidth for a

capacitive interpolated flash ADC can be substantially reduced
by both multi-stage interpolation and the relatively heavier load
of the interpolation pre-amplifiers, which leads to reduced
ADC sampling rate. The previous analysis provides a clear
illustration for the impacts of capacitive interpolation on the
flash ADC bandwidth, both qualitatively and quantitatively.

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C. Sampling Speed Analysis for Interpolated Flash ADC

Flash ADC sampling rate analysis is provided below. For a
single one-pole amplifier, from previous frequency response
analysis, it comes that,

vo  t 

AV vin 1  e

t

analysis, the overall sampling speed for a flash ADC can be

derived in Eq. (9),
1

f speed , ADC



where  is time constant given by W

RL CL , AV is low
frequency amplifier gain, RL and CL are load resistance and
capacitance of the amplifier, respectively. It is understood that
the time required to amplify input signals to a certain output
magnitude depends strongly on the difference of the input
signals. For an ADC chip, the worst case is when the
difference between the input and one of the reference is 1/2
LSB, which makes both the two adjacent pre-amplifiers take
longer time to amplify signals. On the other hand, the output
of a pre-amplifier will be sent to a latched comparator, which
requires the output signal to be large enough in order to be
sensed by the latched comparator for accurate signal
comparison. Thus, the following can be obtained,
t


W
AV LSB 1  e 'vL
n 1
2
2

comparator,

LSB

is

 Full Scale 

constant. 1 2

n 1

number

2 , W
n

of

pre-amplifier

III.

stages,

1 Z -3dB is pre-amplifier time

is the smallest gain that amplifies the

input signal, because each interpolated signal from the second

stage is only amplified by 1 AV . Therefore, the slowest
2
response time becomes,

ts

1
1

W ln
W

ln
n
n
n
'vL 2

'v L 2 2


1
1
An LSB

n
AV FS



Ts 2 1 2 f s holds, where ts is response

time of whole cascaded pre-amplifier chain, Ts is clock period
and fs is generally defined as sampling speed for the ADC.
Thus, sampling rate for a flash ADC is given as,
In addition, t s

fs

1
2 ts

S f  3 dB

1
ln
n
n
1 'vL 2 2


n
AV FS

2 n  1 f 3 dB , central

1
ln
n
n
1  'vL 2 2
n

AV FS

(9)

where fspeed,ADC is overall ADC sampling speed, n is number of

stages and f-3dB,central is bandwidth of the individual interpolation
pre-amplifier block circuit. Eq. (9) depicts that the sampling
speed for a capacitive interpolated flash ADC is quantitatively
related to its interpolation pre-amplifier bandwidth,
interpolation factor, resolution bit number and the number of
stages selected. The new quantitative matrix obtained provides
useful design guidelines for IC designers to rapidly and
accurately design capacitive interpolated flash ADC for proper
design trade-offs and achieving whole-chip ADC performance
optimization.



where 'vL is minimum voltage signal required by a latched

DYNAMIC POWER ANALYSIS OF CAPACITIVE

INTERPOLATED ADC

Power consumption is very critical for ADCs especially for

high speed ADCs. Increase of speed always results in higher
power consumption because of large number of pre-amplifiers,
even when interpolation technique is applied. However, for
capacitive interpolated flash ADC, it could be worse since the
capacitors used for interpolation constantly charges and
discharges, which generate transient current that flows through
and hence cause substantial dynamic power dissipation. For
low speed ADCs, the dynamic power dissipation can be
neglected. But for very high speed (>Gsps) and relatively high
resolution ADCs, the dynamic power dissipation may play a
significant role, which is analyzed in this section.
A. Power of a Single Switched-Capacitor Pre-amplifier
Consider a switched-capacitor amplifier shown in Fig. 4. It
is obvious that the input capacitors (Cin and Cip) are charging
and discharging when the switches are turned on and off. Same
happens to output capacitors (Con and Cop). Thus, charging and
discharging of capacitors consume dynamic power. Simulation



where f-3dB is overall frequency bandwidth (Hz) of the

cascaded interpolation pre-amplifier chain. From previous

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Fig. 4 A switched-capacitor amplifier.

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shows that the current flowing from the capacitor to ground has
periodic spikes when capacitors charge and discharge. Note
that the input and output capacitors are used for interpolation in
ADC design, hence, parasitic capacitances should be
considered when calculating dynamic power. The dynamic
power dissipation can be expressed as,

PD ,total

Pin  PL

D Cin 'Vin2 fin  D CL 'Vout2 f out

(10)

where  is switching probability, C is capacitance including the

parasitic one, 'V is voltage change and f is frequency. For a
practical switched-capacitor amplifier design used in our ADC
operating at 2GHz, the maximum dynamic power dissipation is
estimated as (=0.5 for simplicity),

PD ,total

0.5 u 100f u 0.32 u 2G  100f u 0.62 u 2G  u 2

(11)

90PW
Compare the dynamic power with the static power, which
is about 2.28mW, the dynamic power is still relatively small
for a single amplifier. However, for the whole ADC core, the
overall dynamic power could be relatively large. The
capacitive interpolation makes whole chip power estimation
complicated, because the edge pre-amplifiers and interpolated
pre-amplifiers have different input and loading capacitors. For
our 4-bit ADC designed, the dynamic power is roughly
(including 19 edge pre-amps and 15 interpolated pre-amps),
PD ,overall

new ADC design matrix technique. Fig. 2 shows the 4bits flash
ADC designed in 90nm CMOS in this work. The individual
interpolation pre-amplifier bandwidth is obtained as about
3.3GHz. Apply it into Eq. (9), the overall ADC sampling speed
can be calculated as,

19 u 90 PW 
0.5 u  4 u 100f u 0.32  2 u 150f u 0.6 2  u 2G u 15 (12)
3.87 mW

The overall static power consumption is calculated as

77.52mW. Hence, dynamic power is about 5% of the static
power. Although still relatively small, the dynamic power does
increase faster than static power because of interpolation,
which makes some pre-amplifiers have more input capacitors
and heavily loaded, resulting in much more dynamic power
dissipation. As sampling speed increases and bit resolution gets
higher, the dynamic power can no longer be ignored. For
example, at a 10GHz speed, rough calculation shows that the
dynamic power dissipation could easily reach to at least 50mW,
which becomes non-negligible. The static power dissipation
increases too, reaching to several hundreds of mW. On the
other hand, if the resolution bit increases, more stages and
more interpolation are needed, which result in more
interpolation pre-amplifiers, hence, higher dynamic power too.
Generally speaking, for a capacitive interpolated flash ADC,
the dynamic power consumption may be neglected if it works
at relatively lower speeds. However, as ADC sampling speed
increases, e.g., >4GHz, the dynamic power could reach to tens
of mW and become ~10% of the static power. Therefore,
accurate power estimation for flash ADC must include
dynamic power analysis using the above technique.

f speed , ADC

S 2 4  1 u 3.3

1
ln
4
4
1  20mV 2 2

24 400mV

2.8GSps




The theoretical maximum speed calculated for this ADC is
about 2.8GSps, which is reasonably close to the actual ADC
sampling rate of about 2.3GSps obtained. Another practical
design in 130nm CMOS technology simulated a maximum
speed of 1GSps while theoretical calculation is 1.22GSps.
These examples confirm that our new design matrix works
reasonably well in practical designs. It can also be used to
directly map whole-chip ADC performance specs with key
design factors at different levels, i.e., ADC architecture, block
circuit, device and process parameters, hence, provides useful
quantitative design guidelines for flash ADC designs.
V.

CONCLUSION

This paper provides a practical design matrix analysis

technique for designing capacitive interpolated flash ADCs,
which allows quantitative analysis of influences of technology,
device, circuit and structural parameters on whole-chip ADC
performance. The quantitative mapping between ADC
performance specs and design parameters, such as,
interpolation factor, number of stages, pre-amplifier bandwidth,
loading effects, transistor size, technology parameters, etc., will
enable IC designers to conduct quick and rational flash ADC
design with optimum design balance and whole chip
performance. We also developed a new accurate dynamic
power analysis technique, which allows more accurate power
estimation for ADC including the non-negligible dynamic
power dissipation at high sampling speeds. The design
technique was validated by actual design of 4bits flash ADCs
in commercial 90nm and 130nm CMOS technology.
REFERENCES
[1]
[2]
[3]

[4]
[5]

IV. DESIGN VERIFICATION

Actual capacitive interpolated flash ADCs designed in
foundry 90nm and 130nm CMOS were used to validate the

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M. Gustavsson, J. Jacob Wikner and N. Tan, CMOS Data Converters for

Communications, Kluwer Academic Publishers, 2000.
D. Hoeschele, Analog-to-Digital and Digital-to-Analog Techniques,
Wiley & Sons, 1994.
A. Ismail and M. Elmasry, Analysis of the flash ADC bandwidthaccuracy trade-off in deep-submicron CMOS technologies, IEEE Trans.
Circuit and Systems-II, pp. 1001-1005, 2008.
J. Vandenbussche, et al., Systematic design of a 200 MS/s 8-bit
interpolating A/D converter, Proc. IEEE DATE, pp. 357-361, 2002.
K. Uyttenhove and M. Steyaert, Speed-power-accuracy trade-off in
high-speed ADCs: what about nano-electronics?, Proc. IEEE Custom
Integrated Circuits Conf., pp. 341-344, 2001.
W.-T. Lee, et al., A new low power flash ADC using mutiple-selection
method, Proc. IEEE EDSSC, pp. 341-344, 2007.

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