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DEPARTMENT OF ELECTRONICS &


COMMUNICATION ENGINEERING
NIT CALICUT

LAB MANUAL
EC 2028: ELECTRONIC CIRCUITS LABORATORY I

Syllabus

1. BJT and JFET Biasing schemes and Bias Stability comparison


2. Emitter follower frequency and phase response
3. Single stage BJT amplifier Frequency Response
4. Single stage JFET amplifier Frequency Response
5. Power amplifier Class A and Class AB
6. Two stage RC coupled amplier Frequency Response
7. Cascode Amplifier Frequency Response
8. Feedback amplifiers
9. Phase Shift Oscillator
10. Colpitts/Hartley Oscillators
11. Astable, Monostable and Bistable Multivibrator with BJT
. Reference:
1. A S Sedra & K C Smith : `Microelectronic Circuits, Oxford University Press.1998
2. Jacob Millman & Herbert Taub: Pulse, Digital & Switching Waveforms, TMGH
1995
3. Donald A. Neamen, Electronic Circuit Analysis and Design, 2nd Edition, MCGraw
Hill 2003
4. Millman & Halkias : `Integrated Electronics, MGH. 1996
5. D L Schilling & C Belove : `Electronic Circuits, Third Ed; MGH. 2002
6. Robert Boylestad & Louis Nashelsky : `Electronic Devices & Circuit Theory,
PHI.1995
7. William H Hayt Jr : `Electronic Circuit Analysis & Design.1994
8. Theodore F Bogart : `Electronic Devices & Circuits.2003
9. Mark N Horenstein : `Microelectronic Circuits & Devices, PHI.2002
10. Millman & Grabel : Microelectronics : MGH 1989
11. Richard C. Jaeger : Microelectronic circuit design, MGH 2007

Course Outcomes:
CO1: Develop the ability to Design and implement discrete analog
amplifiers to meet the given specifications.

CO2: Understand the effects of parasitic of circuit components on the


performance of the circuits and learn how to minimize those effects.
CO3: Design and implement BJT/FET based harmonic and relaxation
oscillators.
CO4: Learn to alter power level of the signals to feed the available
loads.
CO5: Develop the ability to design and implement analog subsystems
based on discrete component design
CO6: Develop the ability to give both oral presentation and technical
report on basic discrete analog circuits.

TABLE OF CONTENTS

SL
NO.

EXPERIMENT NAME

1.

STUDY OF BIASING CIRCUITS

2.

TRANSISTOR AS SWITCH

3.

COMMON EMITTER AMPLIFIER

4.

MULTIVIBRATORS

5.

EMITTER FOLLOWER

6.

PHASE SHIFT OSCILLATOR

7.

FEED BACK AMPLIFIER

8.

POWER AMPLIFIER

Experiment: 1

STUDY OF BIASING
CIRCUITS
OBJECTIVE: To understand different transistor
biasing circuits and to
appreciate the advantage of one above the
other.
AIM
To design, set up and study the performance of transistor biasing
circuits (fixed biasing and voltage divider biasing).

COMPONENTS REQUIRED
1.
2.
3.
4.
5.
6.
7.
8.

Power supply
CRO
Breadboard
Multimeter
Resistors
BC547
SL100
Capacitors

Figure 1
GRAPH

: LOAD LINE

Figure 2 : (a) Fixed Bias Configuration (b) Voltage Divider Bias of NPN
Transistor

Figure 3 : Voltage Divider Bias with Capacitors

THEORY& DESIGN
INTRODUCTION

In order to design any amplifier circuit, various factors like


gain, current etc. have to be fixed according to the
requirements of the circuit. To achieve this, the transistor
has to be DC biased to the required specification or
operating point. Hence, various DC biasing circuits are used
to drive transistors into different operating modes based on
the available parameters and our requirements.
LOAD LINE ANALYSIS
Operating Point:
For transistor amplifiers the resulting dc current and voltage
establishes an operating point on the characteristics that
define the region that will be employed for amplification of
the applied signal. Since the operating point is a fixed point
on the characteristics, it is also called the quiescent point.
As seen from the figure1, Point A is the most suitable point
for amplification purposes.
Load Line:
Consider a plot between VCE and IC, now superimpose a line
joining VCC and VCC/RC over it. This line is called the load line
since its defined by the load resistor RC. The load line is
described by the equation VCE = VCC ICRC. This equation is
obtained by considering KVL from VCC to ground as shown in
figure2 (a). Once the two graphs are superimposed, its
observed that for different values of I B the two graphs
intersect at different points. Hence from the required
application and from the required value of I B, we can obtain the
Q point.

VOLTAGE DIVIDER BIAS


In this configuration, we fix the base voltage V B using the
two resistors R1 and R2. This effectively provides a constant
base voltage and helps to make the circuit almost
independent of . This ensures the stability of the circuit, as
by choosing the proper circuit parameters we can keep I C
and VCE almost independent of .
Also the addition of an emitter resistor, stabilizes the circuit
against temperature variation on . This configuration is

hence preferred over fixed bias as the operating point is


almost independent of hence the circuit gives the same
output even if a different transistor were to be used.
Design
As per the output requirements, IC can be fixed. Now it is
assumes that 10% of VCC drops across RE.
So RC and RE can be designed as given by the equation; (IC
IE);

This fixes our output current requirements. Now to bias the


circuit resistors, R1 and R2 have to be designed.
We assume that the current flowing through these resistors
due to VCC is 10% of IE. Also we know that,
VR1 = VBE + VE = 0.7V + 1V = 1.7V

R1 = VR1 /(0.1 x IC)

FIXED BIAS
This is one of the simplest transistor biasing configurations
where we reach the operating point by making use of a
single DC supply, an input signal and two resistors. In this
biasing circuit, we fix the base current IB to the transistor.
This is achieved by taking the VCC to the base via the resistor
RB to provide the constant current. The collector current I C
can be fixed as per requirement by using a suitable resistor
RC.
Although, simple and easy to build, this design faces a lot of
stability issues such as the variation of with temperature
or IC. Hence, the circuit parameters depend on and any
changes in (e.g. If the transistor is changed) can affect the
output of the circuit.
Design

The collector current can be fixed to a required value as


needed. Using this information and VCC value, RC can be
designed as

Now RB can be designed to get the corresponding IB (= IC /);

PROCEDURE
1. Different breakdown voltages, (Min, Typ and Max)
and maximum collector current of BC547B and SL100
were noted down from their data sheet.
2. Design and assemble the Fixed Biasing circuit for the
BC547B transistor to operate it at points A, B and C in
the given load line.
3. Measure the values of collector voltage (V C), Emitter
voltage (VE) and Base voltage (VB) of the transistor,
verify the operating points and VBE value in each case.
is calculated by measuring IC and IB.
4. Repeat steps (2) and (3) for Voltage divider biasing
circuit.
5. Apply a sine wave of amplitude (20mVpp, 1kHz) in the
voltage divider circuit through a 10F capacitor. Vary
the amplitude of the input waveform and observe
output waveform at collector of the transistor through
another 10 F capacitor.
6. The maximum amplitude of input signal that can be
given to the circuit is noted so that the output is
undistorted.
7. Replace BC547B with SL100 in both the biasing circuits.
Step (3) is repeated.
8. Compare the bias stability of the two biasing circuits
based on the results

10

SAMPLE NETLIST IN NGSPICE


Biasing circuits
VCC 1 0 DC 10
rc 1 2 2.5k
rb 1 3 1600k
q1 2 3 0 bc548c
.MODEL bc548c NPN (
+ AF= 1.00E+00 BF=543 BR= 2.42E+00 CJC= 5.17E-12
+ CJE= 1.33E-11 CJS= 0.00E+00 EG= 1.11E+00 FC= 9.00E-01
+ IKF= 1.80E-01 IKR= 1.00E+00 IRB= 1.00E+01 IS= 1.95E-14
+ ISC= 1.00E-13 ISE= 1.31E-15 ITF= 1.03E+00 KF= 0.00E+00
+ MJC= 3.19E-01 MJE= 3.26E-01 MJS= 3.30E-01 NC= 2.00E+00
+ NE= 1.32E+00 NF= 9.93E-01 NR= 1.20E+00 PTF= 0.00E+00
+ RB= 2.65E+01 RBM= 1.00E+01 RC= 1.73E+00 RE= 1.00E+00
+ TF= 6.52E-10 TR= 0.00E+00 VAF=33.3v VAR= 2.47E+01
+ VJC= 3.39E-01 VJE= 6.32E-01 VJS= 7.50E-01 VTF= 1.65E+00
+ XCJC= 1.00E+00 XTB= 0.00E+00 XTF= 1.00E+02 XTI=
3.00E+00)
.end

EXPECTED OBSERVATIONS AND RESULT

Voltage divider biasing is more stable than fixed bias


due to the influence of the emitter resistor.
Voltage divider biasing is not affected much by the
change in .

Maximum swing is obtained when the Q-point is


located at approximately the middle of the load line.

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PRE REQUISITES
For BC547B, from datasheet, the following values were
observed:
IC MAX = 100 mA
Breakdown Voltages: VCBO = 50 V

VCEO = 45 V

values: min = 200, typical = 300, max=450


For SL100, from datasheet, the following values were
observed:
IC MAX = 500mA
Breakdown Voltages: VCBO = 60 V

VCEO = 50 V

values: min = 40, typ = 170, max=300


.

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Experiment: 2

TRANSISTOR AS
SWITCH
OBJECTIVE: To familiarize different
transistor switching configurations so as
to choose a suitable one for practical
realizations
AIM
To design, set up and study the performance of
transistor switching circuits.
COMPONENTS
1. Resistors
2. Capacitors
3. Transistor BC547B
4. Transistor SL500
5. DC power source
6. Multimeter
7. Connecting wires
8. Breadboard
CIRCUIT DIAGRAMS

Figure. 1

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Figure. 2

Figure. 3
Figure. 4

THEORY

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Transistor as a switch.
Solid state switches are one of the main applications for the use
of transistors, and transistor switches can be used for controlling
high power devices such as motors, solenoids or lamps. The
areas of operation for a Transistor switch are known as the
saturation region and the Cut-off Region.
1. Cut - off region
The operating conditions of the transistor are zero input
base current (IB), zero output collector current(I C) and
maximum collector voltage (VCE) which results in a large
depletion layer and no current flowing through the device.
Therefore the transistor is switched Fully OFF. The cutoff region or OFF mode when using a bipolar transistor
as a switch can thus be defined as both junctions reverse
biased,VB <0.7v and Ic=0.For a PNP transistor, the Emitter
potential must be negative with respect to the base.
2. Saturation Region
The transistor will be biased so that the maximum amount
of base current is applied , resulting in maximum collector
current resulting in the minimum collector emitter voltage
drop which results in the depletion layer being as small as
possible and maximum current flowing
through the
transistor. So the transistor is switched Fully-ON. Both
junctions are forward biased, VB > 0.7v and for a PNP
transistor, the emitter potential must be positive with
respect to the base.
For transistor switching action, we exploit the cut off and
saturation regions of the transistor. A zero input voltage ensures
the transistor to be in the cut off region providing a high output
voltage of VCC.For obtaining a low output a saturation current I C is
required to flow through the transistor .In order to ensure
saturation a Base Current which is greater than that
corresponding to saturation current. The collector current is fixed
as required at the output using the collector resistance R C.A base
current that ensures saturation is obtained by fixing the base
resistance RC.

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Rise and Fall Times


As soon as the input voltage goes high, the transistor is forced
into the saturation region. But it takes some time for the
transistor to transform from cut-off to saturation through the
active region. The time for collector current to rise from zero to
ten percent of the maximum is termed as the delay time. From
there, the time it takes to reach ninety percent is termed as the
rise time. The delay time and fall time together forms the t ON.
After the transistor switches on, the base region gets filled with
charge carriers during saturation. When the input voltage falls
forcing the transistor to switch off, both the junctions become
reverse biased trapping the charge carriers in the base region.
Now, the base charge diffuses as the reverse saturation current
and thus it takes a long time to go into the cut-off. The time for
collector current to fall from maximum to ninety percent of the
maximum is termed as the storage time. Therefore, storage time
is the maximum. From there, the time it takes to reach ten
percent is termed as the fall time. When we observe output
voltage (collector voltage), the rise in collector current is
reflected as the fall in output voltage and vice-versa. So, the fall
time of output voltage will be very small relative to the rise time
Capacitors
Capacitors play an important role in transistor switching circuits
because of their abilities to filter out the dc component from a
signal and that to introduce a delay in rise and fall of voltage
levels in the circuit. The series capacitor at the input is placed so
as to filter the input signal to provide the desired alternating
signal of a particular frequency. The capacitor at the output is
placed such that the delay introduced by the capacitor relative to
the input frequency helps us to maintain an output high, less
than the usual high output (3V in our experiment). The capacitor
value is taken such that by the time it charges to the desired
output high during the transistor on state, the transistor turns
off.
VC = Vf + (Vini- Vf)

Relay
Relays are components which allow a low-power circuit to switch
a relatively high current on and off, or to control signals that
must be electrically isolated from the controlling circuit itself. In
our experiment, we make use of the transistor switching circuit

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to switch on or off the relay which in turn controls another circuit


with different voltage and current ratings. Furthermore, this
switching action of the transistor is done by a very small base
current supplied by a small input pulse. The various parameters
of the transistor switching circuit are determined by the ratings
of the relay. Collector current is fixed by the voltage requirement
and resistance of the relay. Base resistor is used to set the base
current for the transistor, so that the transistor is driven into
saturation (fully turned on) when the relay is to be energized.
That way, the transistor will have minimal voltage drop, and
hence dissipate very little power and at the same time, deliver
most of the supply voltage to the relay coil.
The relay consists of five terminals two lines for supply and
three for controlling the outer circuit. The two supply lines are
connected in the path of supply voltage to the transistor, in
accordance with the polarity. The other three lines comprises of a
common, a normally closed and a normally open terminals.
Normally, there will be electrical continuity between the common
and the normally closed lines while the normally open line will be
disconnected. As the relay is turned on, the continuity shifts from
the normally closed line to the normally open line, thus acting as
a switch.
A power diode is connected across the relay coil, to protect the
transistor from damage due to the back-EMF pulse generated in
the relay coils inductance when the transistor turns off.
DESIGN
Let VBEsat = 0.7V, VCEsat = 0.2V, = 200

FIGURE 1

FIGURE 2

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VC (

)=3V

FIGURE 3

VC = Vf + (Vini- Vf)
Vf =

Vini=

C=

FIGURE 4

PROCEDURE
1. The circuit was designed as in fig. 1 for I Csat = 2mA and VCC
= 10V.
2. Apply an input Vi as a pulse waveform of 0-5V and observe
the output for voltage levels, rise time and fall time when
the input frequency is (a) 1 kHz, (b) 5 kHz, (c) 500 kHz.
3. Design the circuit in fig. 2 for I Csat = 2mA and VCC = 10V
under the assumption that voltage drop across the LED
when it is ON is VLED = 1.5V.
4. Apply input voltage (Vi) as a square wave of amplitude 0-5V
and note the behavior of the LED by varying the input
frequency.
5. Design the circuit as in fig. 3 for a collector current of 2mA
and VCC = 10V such that the output V o reaches 3V at the
end of the OFF state of the transistor for a 1 kHz square
wave input of 0-5V.
6. Observe and plot the output wave form of this circuit.
Repeat this for half and double the calculated capacitor
values and note the changes.
7. Design the circuit as in fig. 4 after identifying the terminals
of the relay. A normal diode may be placed across the relay.
8. Connect the bulb and 12V source between the C and N/C
terminals and observe the behavior of the bulb for high (V i
= 5V) and low (Vi = 0V) inputs.
9. Observe the behavior of the bulb when the bulb and the
12V supply are connected across the C and N/C terminal of
the relay.

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EXPECTED OBSERVATIONS
Rise time is greater than the fall time for BC547B.
Rise time is of the order of 10s and fall time is lower than
5s.
The rise time and fall time, both are independent of input
frequency as long as its within the operating frequency of
the specified transistor.
At higher frequency (500KHZ), it was observed that the
transistor remains on. This happens because the transistor
is not getting enough time to switch between saturation
and cut-off. Time period of input pulse is 2s (1/500), the
rise time of transistor is around 10s. From these
observations its clear that the transistor remains on.
From the second part of the experiment it was observed
that the LED blinks at low frequency. But at a slightly higher
frequency of about 50HZ, the blinking visually stops.
After adding a capacitor (0.33F) between the collector and
emitter of the transistor as shown in the third part of the
experiment, it was observed that the output voltage rises to
a maximum of 3V.
If we decrease the capacitance value, it takes smaller time
for the capacitor to charge. So the output voltage rises to a
larger value.
If we increase the capacitance value, output voltage rises
to a smaller value.
It was also observed that at lower capacitance value, the
curve becomes visually more exponential in nature.
When the relay is not energized (no current is flowing
through the relay), at the output side, there is a connection
between the N/C and C terminal.
When the relay is energized, there is a connection between
the N/O and C terminals. The N/C terminal is left open.
The diode connected in parallel to the relay protects the
transistor from the back EMF by providing a path for the
energy stored in the relay to dissipate.

Relay switching Bulb behaviour


Connected
Terminal

VIN

Light

N/C

0V

ON

5V

OFF

Normally Closed

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N/O
Normally Open

0V

OFF

5V

ON

Switch with LED


At lower frequencies : Blinking of LED w.r.t input
signal is visible clearly
At higher frequencies ( >50Hz) : Blinking cannot
be distinguished and the LED seems to remain
always on

EXPECTED WAVEFORMS FOR THE RC RAMP


GENERATOR
Vc (V)

t (ms)

C =0.33F Calculated value

Vc (V)

t (ms)
Vc (V)

CC =2*0.33F
=0.5*0.33F
2 xCalculated
Calculatedvalue
value/ 2

t (ms)

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SAMPLE NETLIST IN NGSPICE


RC BOOTSTARP
q1 5 3 0 ttn
q2 1 5 6 ttn
rb 1 3 150k
r1 2 5 3.9k
re 6 7 1k
c1 5 0 .47uf
c2 3 4 33nf
c3 2 6 47uf
vcc 1 0 10v
vee 0 7 10v
d1 1 2 dd1
VIN 4 0 PULSE(0 -5 2NS 2NS2NS 1ms 2ms)
.MODEL ttn NPN (
+ AF= 1.00E+00 BF=420 BR= 2.42E+00 CJC= 5.17E-12
+ CJE= 1.33E-11 CJS= 0.00E+00 EG= 1.11E+00 FC= 9.00E-01
+ IKF= 1.80E-01 IKR= 1.00E+00 IRB= 1.00E+01 IS= 1.95E-14
+ ISC= 1.00E-13 ISE= 1.31E-15 ITF= 1.03E+00 KF= 0.00E+00
+ MJC= 3.19E-01 MJE= 3.26E-01 MJS= 3.30E-01 NC= 2.00E+00
+ NE= 1.32E+00 NF= 9.93E-01 NR= 1.20E+00 PTF= 0.00E+00
+ RB= 2.65E+01 RBM= 1.00E+01 RC= 1.73E+00 RE= 1.00E+00
+ TF= 6.52E-10 TR= 0.00E+00 VAF= 9.17E+01 VAR= 2.47E+01
+ VJC= 3.39E-01 VJE= 6.32E-01 VJS= 7.50E-01 VTF= 1.65E+00
+ XCJC= 1.00E+00 XTB= 0.00E+00 XTF= 1.00E+02 XTI= 3.00E+00)
.MODEL dd1 d
+IS=7.02767e-09 RS=0.0341512 N=1.80803 EG=1.05743
+XTI=5 BV=1000 IBV=5e-08 CJO=1e-11
+VJ=0.7 M=0.5 FC=0.5 TT=1e-07
+KF=0 AF=1
.end

21

EXPERIMENT: 3

COMMON EMITTER
AMPLIFIER
OBJECTIVE: To understand and appreciate the
importance of Common Emitter amplifier
AIM:
1. To design and set up a Common Emitter (CE) amplifier with
the following specifications
(i) Voltagegain >100
(ii) Minimum input frequency=500Hz
With the transistor operating at the Q point I c=2mA using a 12V
power supply, for a resistive load 50k.
2. To test the performance of the amplifier by measuring
transient and frequency responses.
COMPONENTS REQUIRED:
1.
2.
3.
4.
5.
6.
7.
8.

Transistor BC547B
Resistors
Capacitors
Breadboard
Multimeter
CRO
DC power supply
Potentiometer

CIRCUIT DIAGRAMS:

22

Figure 1

Figure 2: To measure the input


resistance

Figure 3: To measure the output resistance


THEORY:
Amplifier

23

Amplification is a fundamental signal processing function used in


almost every electronic system. Amplifier is functional block that
accomplishes this task and it also increases the power of a
signal. It does this by taking energy from a power supply and
controlling the output to match the input signal shape but with a
larger amplitude.
Depending on the signal to be amplified (voltage or current) and
on the desired form of output signal (voltage or current) there
are four basic types of electronic amplifiers namely voltage
amplifiers, current amplifiers, trans conductance amplifiers and
trans resistance amplifiers.

CE Amplifier
There are three basic configurations for connecting the BJT as an
amplifier. Each of these configurations is obtained by connecting
one of the three BJT terminals to ground. Thus the grounded
terminal is common to both the input and output ports. In
common-emitter configuration, the emitter terminal is connected
to ground, the input voltage signal is vi applied between the base
and ground.
The upper cut-off frequency FH is defined as the frequency
beyond which there is an attenuation of more than 3dB. The
lower cut-off frequency FL is defined as the frequency below
which the attenuation is greater than 3dB. Bandwidth of the
transistor is the difference between FH and FL. Maximum gain is
available at frequencies within the bandwidth of the transistor.

The lower cut-off frequency can be calculated from the graph


which plots the collector voltage and time by using the following
equation,

Where FL is the lower cut-off frequency. V and V have been


marked on their respective graphs.

Also the upper cut-off frequency can be obtained from the figure,
by using the equation

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Where BW is the bandwidth of the transistor, F L is neglected


compared to FH. tr is obtained from the graph .

DESIGN:

To calculate the collector resistance R C: The gain of the


amplifier as well as the collector current and load resistance
is known. Therefore from the equation of voltage gain, we
can calculate RC.

The voltage drop across RE is assumed to be 10% of VCC and


its value is designed from the following relation because
of BC547 is sufficiently large.

Using KVL, we can determine the value of VCE to be

Hence the operating point of the transistor can be defined by (I C,


VCE).

Base current of the transistor is calculated from the relation

Voltage drop across VR2 =VBE +VRE.


The current through R1 (IR1) is assumed to be 20 times IB.
From these two relations, we can calculate R1 and R2.
While assuming IR2, we also need to ensure that
R1||R2 < 0.1(+1)RE (for bias stability).

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We need to calculate CC1, CC2, and CE such that at an


operating frequency of 500HZ , the magnitude of
impedance due to the respective capacitors satisfy the
following conditions.
Where Rin = R1||R2||hie
Where RL = 50K

PROCEDURE
1. Design and set up the circuit as shown in the figure1.
2. Observe the values of IC; VCE; VRE; VR1 (without applying input
signal) and ensure that requiredQ point is obtained. If not,
find out the reason for shift in Q point and adjust the bias to
get the required Q point.
3. Apply a 10mV (or less) sinusoidal signal of frequency in
mid-band region and measure the output signal amplitude.
Then, calculate mid band voltage gain.
4.

Measure the frequency response (magnitude) of the


voltage gain (from 50Hz to 3MHz, almost the full frequency
range available with the function generator).

5. Find

the

lower

cut-off

frequency

and

upper

cut-off

frequency at which the voltage gain falls to ofthe mid band


gain value.
6. Find the input signal amplitude at which output starts
getting clipped (for an input frequency in the mid-band
region).
7. Measure the input resistance and the output resistance of
the circuit.
a) To measure input resistance, connect a potentiometer (010k) to the CE amplifier in series with the input clipping

26

capacitor(figure2). Apply a mid band frequency


sinusoidal signal of small amplitude. Vary the
potentiometer until the amplitude of the signal voltage
Vx becomes half of that of input signal V i. Remove the
potentiometer and measure its resistance value to get
the input resistance of the circuit. (Make sure that output
voltage is undistorted throughout the measurement).
b) To measure output resistance (without the effect of load
resistor)(figure3).
Apply a mid band frequency sinusoidal signal of small
amplitude (to ensure transistor operates in active region)
at the input. Measure the open circuit output signal
amplitude Voc. Now connect a potentiometer (0-5k) as
load. Vary the potentiometer until the output signal
amplitude Vo becomes half of that of open circuit output
signal. Remove the potentiometer and measure its
resistance value to get the output resistance of the
circuit.
8. Apply square waves of 20mV peak to peak amplitude at a
frequency in
a. low frequency band,
b. mid-band
c. high frequency band
in the frequency response, to the input of the same CE
amplifier.
9. Observe and note down the output waveform in each case.
From the waveforms, calculate the upperand lower cut-off
frequencies and hence the bandwidth of the amplifier.
10.
Remove the capacitor Cand repeat steps 3-9. For
input resistance measurement, use 0-50kpotentiometer.
Find out the mid-band gain bandwidth product in both
cases.
EXPECTED OBSERVATIONS AND RESULT:

The gain of the amplifier remains constant throughout the


mid band frequency.
Current gain bandwidth product remains same for both the
cases, with and without capacitor and hence the transistor
can be operated in a larger frequency range on removing
the capacitor.
Removing the capacitor increases the input impedance
(while output impedance remains almost same) as the
capacitor acts a low impedance path for the signal as per

27

the design. This also increases the max input voltage


threshold before the output is clipped due to the reduced
voltage gain.
At low frequencies the CE amplifier acts as a differentiator
as the input capacitor has a very high impedance at lower
frequencies and this distorts the output waveform. At
higher frequencies the transistor junction capacitances
provide very low impedance to the signal and acts as an
integrator which also distorts the input wave. Hence the
transistor CE amplifier works best in the mid band region.

EXPECTED GRAPHS

28

EXPECTED GRAPHS OF VCE


WITH CAPACITOR

Low Frequency (100Hz)


V (V)
t (ms)

Mid Band Frequency (10kHz)

29

High Frequency (2MHz)

V (V)
t (us)

WITHOUT CAPACITOR CE

Low Frequency (100Hz)

30

V (mV)
t (ms)

V (mV)
t (ms)
V

Mid band Frequency (10kHz)

V (mV)

t (ms)

NOTE:

31

While performing the experiment it is important to use


attenuation probes instead of ordinary probes. This is done to
remove the capacitance of the CRO by the principle of
compensated attenuators (R1C1 = R2C2). However, use of this
device will cause an attenuation to the output signal hence to get
the exact output value, the measured output needs to be
multiplied with the inverse of attenuation factor.

32

SAMPLE NETLIST IN NGSPICE


.ce amplifier
q1 5 2 3 bc548c
rc 4 1 2.7k
re 3 0 470
r1 4 2 150k
r2 2 0 27k
rl 6 0 50k
rp 7 8 0
c1 8 2 6.8uf
c2 1 6 1uf
ce 3 0 100uf
vin 7 0 ac 1 sin(0 10m 10k)
*VIN 7 0 PULSE(-10m 10m 2NS 2NS2NS 2ms 4ms)
v 1 5 0v
vcc 4 0 12v
.MODEL bc548c NPN (
+ AF= 1.00E+00 BF=600 BR= 2.42E+00 CJC= 5.17E-12
+ CJE= 1.33E-11 CJS= 0.00E+00 EG= 1.11E+00 FC= 9.00E-01
+ IKF= 1.80E-01 IKR= 1.00E+00 IRB= 1.00E+01 IS= 1.95E-14
+ ISC= 1.00E-13 ISE= 1.31E-15 ITF= 1.03E+00 KF= 0.00E+00
+ MJC= 3.19E-01 MJE= 3.26E-01 MJS= 3.30E-01 NC= 2.00E+00
+ NE= 1.32E+00 NF= 9.93E-01 NR= 1.20E+00 PTF= 0.00E+00
+ RB= 2.65E+01 RBM= 1.00E+01 RC= 1.73E+00 RE= 1.00E+00
+ TF= 6.52E-10 TR= 0.00E+00 VAF=33.3v VAR= 2.47E+01
+ VJC= 3.39E-01 VJE= 6.32E-01 VJS= 7.50E-01 VTF= 1.65E+00
+ XCJC= 1.00E+00 XTB= 0.00E+00 XTF= 1.00E+02 XTI= 3.00E+00)
.end

33

Experiment: 4

MULTIVIBRATORS
OBJECTIVE: To study and realize basic multivibrator
circuits used practically for many timing operations
AIM
1. To design, set up and test an astablemultivibrator with BJT s
to generate a square voltage signal of 1 KHz for an output
load current of 50A (The supply voltage is 5V).
2. To design, set up and test a monostablemultivibrator with
BJTs to generate a pulse signal of width 750s with collector
currents of 5mA (The supply voltage is 5V).
COMPONENTS REQUIRED
1.
2.
3.
4.
5.
6.
7.
8.

Transistor BC547B
Resistors
Capacitors
Breadboard
Supply wires
Multimeter
DC power source
CRO

CIRCUIT DIAGRAMS

AstableMultivibrator

MonostableMultivibrator

34

THEORY& DESIGN
MULTIVIBRATORS:
A multivibrators an electronic circuit used to implement a variety
of simple two-state systems such as oscillators, timers and flipflops. It is characterized by two amplifying devices cross coupled
by resistors and capacitors. There are three types of
multivibrators circuits depending on the circuit operation:
Astablemultivibrator,
Monostablemultivibrator and
Bistablemultivibrator
These circuits find application in a variety of systems where
square waves or timed intervals are required.

ASTABLE MULTIVIBRATORS
An astablemultivibrator consists of two amplifying stages
connected in a positive feedback loop by two capacitive-resistive
coupling networks. This is generally used as square wave
generator. The circuit has two unstable states and hence oscillate
back and forth between these states.
The BJT astablemultivibrator (as in the fig) has two transistor (Q1
and Q2) switches which are cross couples together through
resistors and capacitors (R1-C1 and R2-C2) which decide the
duration of each unstable state. The output may be obtained at
either VC1 or VC2 with a phase shift of 180o.

Working:
Based on the load and current requirements (I C) the resistors
Rccan be fixed.

RB (RB1 = RB2)can be calculate by the relation


In any of the states one of the transistors will be ON and the
other will be OFF. Assuming that Q1 is ON and Q2 is OFF. Now C1

35

is fully charged and its negative plate is connected to Q2 base


which ensures that Q2 remains OFF. At the same time C1
discharges through RB1 and the saturated transistor Q1. As soon
as the base voltage of Q2 (VB2) reaches above ground level Q2
switches ON (VB2 0.7V). This change the collector voltage V C2
gets coupled to the base of Q1 via the capacitor C2 producing a
negative voltage at the base of Q1 and hence effectively
switching it off. Now C2 discharges via Q2 and R B2 till it switches
again. This process repeats causing the output voltage to
oscillate between VCC and VCEsatproducing a square wave.
If the output is taken as VC1, Q1 remains ON (VC1 = VCEsat) for the
duration as decides by charging of C1 through RB1,

Similarly,
And Duty cycle for this wave is

and frequency =

MONOSTABLE MULTIVIBRATORS
A monostablemultivibrator as the name indicates has one stable
state and one unstable state. This operates such that a trigger
applied to the circuit causes it to move to its unstable state for a
short amount of time and then return back to the stable state. It
is used when a time interval based application is necessary and
also as a frequency divider.
This circuit is achieved by replacing one of the capacitiveresistive network of an astablemultivibrator with resistive
network (as in the fig).
Working:
The output is taken as VC1=Vo. Hence resistors Rccan be fixed so
as to receive the required output current.
And

, similar to the astablemultivibrator.

Initially we assume the circuit to be in the stable state with Q1


ON and Q2 OFF, making Vo =VCesat. This condition is ensured by

36

the resistor R2 which ensures the base voltage of Q2 is well below


the cutoff voltage
The trigger is given as a negative spike at collector of Q2 which
brings VC2 down. This change gets coupled on the capacitor C
whose negative terminal is connected to the base of Q1 which in
turn causes Q1 to turn OFF. The capacitor the begins to charge
through RB and Q2 (till its voltage or VB1 reaches ground level) for
the duration given by

After this duration the capacitor voltage reaches V BEsat at the base
of Q1 and Q1 switches ON causing the output voltage to reduce
and hence going back to its stable state till another trigger is
applied.
The value of the resistor R1 and R2 can be calculated such that
whenQ2 is on R2 has a drop of VBEsatacross it and also provides the
necessary base current (IB = IC/) required. Also it is assumed
that IR1 is 1/10th of the collector current.
Triggering:
The trigger pulse is generated using a differentiator circuit
connected to the collector terminal of Q2. This is set up such that
, where t is time period of the square wave
which is to be differentiated. A diode (in reverse bias) is used to
remove the positive spikes from the differentiator output.
Speed-up Capacitor:
A speed up capacitor C1 placed parallel to R1 is used to speed up
the transitions of Q2. Any capacitor can be used for this purpose
which meets the constrains,
and
Where tontime taken for voltage to rise from 0 to 90%
of its value and toff the duration for which the output
VC1 is low before the next trigger.

PROCEDURE
1. AstableMultivibrator:
1. Design and set up the circuit.Check the proper working
of each capacitively coupled inverter.
2. Note down the voltage waveforms at the nodes V c1, Vc2,
Vb1, Vb2.

37

3. Check whether the results obtained are consistent with


the expected ones.
4. Repeat steps 2-3 after connecting load resistances of
100K with respect to ground at both the output nodes.
5. Modify the circuit to get a 75% duty cycle square wave of
1kHz.Repeat the steps 2-3.
6. Redesign the circuit for an output frequency (50% duty
cycle square wave) of 100kHz.Observe the output.
2. MonostableMultivibrator:
1. Design and set up the circuit.
Check separately the proper working of each inverter.
2. Apply a 0-5V square wave voltage signal of 500Hz as
Vtrig.
3. Note down the voltage waveforms at the nodes V c1, Vc2,
Vb1,and Vb2.
4. Check whether the results obtained are consistent with
the expected ones.
5. Remove C1 and repeat step 3.
6. Apply a 0-5V square wave voltage signal of 2 kHz as V trig
and observe Vc1.
EXPECTED OBSERVATIONS
The astablemultivibrator circuit can be used produce square
waves of the required frequency and duty cycle by using
the corresponding resistive capacitive networks.
Introducing the speed up capacitor to the monostable
circuit improves the output waveform making it sharper
during transitions. The output falls more rapidly than
before. (This also causes downward spikes in the base
voltage of Q2).
A monostablemultivibrator can be used a frequency divider
to divide the input frequency of the trigger wave. In the
experiment a 2kHz wave given as the input gave an output
wave of 1kHz with a different duty cycle (depending on the
monostable time period).

38

EXPECTED WAVEFORMS

ASTABLE MULTIVIBRATOR
Without Load

39

With Load

40

MONOSTABLE MULTIVIBRATOR
Without speed-up Capacitor

41

With speed-up Capacitor

SIMULATION RESULTS
To redesign the astablemultivibrator circuit for an output
frequency (50% duty cycle square wave) of 100 kHz.
Observe the output

42

Simulated graphs at various nodes


Redesigning C1 = C2 as 41.7pF
VC1 (V

43

VC2 (V)

44

SAMPLE NETLIST IN NGSPICE


monostablemultivibrator
q1 2 1 0 bc548c
q2 4 3 0 bc548c
rc1 7 2 1k
rc2 7 4 1k
rb 1 7 330k
r1 2 3 10k
r2 3 0 2.2k
rd 5 7 .6k
c 1 4 3.3nf
*c1 2 3 4.7nf
cd 5 6 15nf
d1 4 5 dmod
vcc 7 0 5v
vtrig 6 0 ac 1 dc 0 PULSE(0 5 0 0 0 .25ms .5ms )
.model dmod D ( bf =50 is =1e-13 vbf =50)
.MODEL bc548c NPN (
+ AF= 1.00E+00 BF=543 BR= 2.42E+00 CJC= 5.17E-12
+ CJE= 1.33E-11 CJS= 0.00E+00 EG= 1.11E+00 FC= 9.00E-01
+ IKF= 1.80E-01 IKR= 1.00E+00 IRB= 1.00E+01 IS= 1.95E-14
+ ISC= 1.00E-13 ISE= 1.31E-15 ITF= 1.03E+00 KF= 0.00E+00
+ MJC= 3.19E-01 MJE= 3.26E-01 MJS= 3.30E-01 NC= 2.00E+00
+ NE= 1.32E+00 NF= 9.93E-01 NR= 1.20E+00 PTF= 0.00E+00
+ RB= 2.65E+01 RBM= 1.00E+01 RC= 1.73E+00 RE= 1.00E+00
+ TF= 6.52E-10 TR= 0.00E+00 VAF=33.3v VAR= 2.47E+01
+ VJC= 3.39E-01 VJE= 6.32E-01 VJS= 7.50E-01 VTF= 1.65E+00
+ XCJC= 1.00E+00 XTB= 0.00E+00 XTF= 1.00E+02 XTI= 3.00E+00)
.END

45

EXPERIMENT 5:

EMITTER FOLLOWER
OBJECTIVE: To comment upon the importance of
emitter follower circuit as a buffer
AIM:
1. To design and set up an Emitter Follower circuit with the
following specifications (i) input resistance > 100k (ii)
Minimum
input
frequency=500Hz
(iii)
maximum
symmetrical swing at the output using a 10V power supply.
2. To test the performance of the amplifier by measuring
transient and frequency responses.

COMPONENTS REQUIRED:
1.
2.
3.
4.
5.
6.
7.
8.

Resistors
Capacitors
Transistor BC547B
Multimeter
Breadboard
DC Power supply
Function Generator
CRO

CIRCUIT DIAGRAM:

Figure: Emitter
Follower

THEORY:
The common-collector (CC) circuit is a very important circuit that
finds frequent application in the design of both small-signal and
large-signal amplifiers and even in digital circuits. The circuit is
more commonly known as emitter follower.

46

In an emitter follower, since the collector is to be at signal


ground, collector resistanceRc has been eliminated. The input
signal is capacitively coupled to the base, and the output signal
is capacitively coupled from the emitter to a load resistance RL.
Unlike the CE and CB circuits, the emitter-follower circuit is not
unilateral, that is, the input resistance depends on RL, and the
output resistance depends onRsig. The BJT has an output
resistance (r0 II RL) in series withthe emitter resistance

. Thus

application of the resistance reflection rule results in the


equation of input resistance. The input resistance at the base,
Ribis Rib = (+l) [RE + (r0||RL)]from which we see that the emitter
follower acts to raise the resistance level of
RL || ro by the factor ( + 1) and presents to the source the
increased resistance.
The total input resistance of the follower is Rin = RB || Rib from
which we see that to realize the full effect of the increased Rib,
we have to choose aslarge a value for the bias resistance RB as is
practical. Also, whenever possible, we should dispense with RB
altogether and connect the signal sourcedirectly to the base. To
find the overall voltage gainGv, we first apply Thevenin theorem
at the input side of
the circuit and we see that Vo can be found by utilizing the
voltage divider rule; thus,
=
We observe that the voltage gain is less than unity; however, for
RB>Rsigand

, it becomes very close

to unity. Thus the voltage at the emitterVofollows very closely the


voltage at the input, which gives the circuit the name emitter
follower.
Rather than reflecting the emitter resistance network into the
base side, we can do the converse: Reflect the base resistance
network into the emitter side. To keep the voltages unchanged,
we divide all the base-side resistances by ( + 1). This is the dual
of the resistance reflection rule. Applying the same procedures
again produces the same equation for G V with both numerator
and denominator divided by
.
While biasing, the q-point is fixed such that the emitter voltage
VE is half of the total biasing voltage so that maximum swing of

47

input sinusoid is allowed. The desired input impedence places


restriction on the resistors RB and RE which in turn fix IE.
Also, the capacitances are chosen such that their loading is
minimal compared to that by the resistors.
In summary, the emitter follower exhibits a high input resistance,
a low output resistance, a voltage gain that is smaller than but
close to unity, and a relatively large current gain. It is therefore
ideally suited for applications in which a high-resistance source is
to be connected to a low-resistance loadnamely, as the last
stage or output stage in a multistage amplifier, where its purpose
would be not to supply additional voltage gain but rather to give
the cascade amplifier a low output resistance.

DESIGN:
Express REinterms of IE as:

where,VE=VCC/2 (for maximum symmetrical swing)


Express RBinterms of IE using the relationship
VCC =

Input resistance
>> 100k (approximate formula).
Using this expression an upper limit for IE will be obtained.Fix
the value of IE which is less than this limit and calculate RE
and RB.
Calculate the expected input resistance with the values and verify that it is
greater than 100k.
Calculate CC1 such that at an operating frequency of 500Hz , the magnitude
of impedance due to CC1 is XCC1<Rin/10.
Take CC2=CC1 (as load resistance is not mentioned)

PROCEDURE
1. Design and set up the circuit in the figure.
2. Note down the values of I C, VCE, VRE,VBE(without applying input
signal) and ensure that required Q point is obtained. If not
find out the reason for shift in Q point and adjust the bias to
get the required Q point.

48

3. Apply a 0.5V (or less) sinusoidal signal of frequency in midband region and measure the output signal amplitude. Hence
calculate mid band voltage gain.
4. Measure the frequency response (magnitude) of the voltage
gain (from 50Hz to 3MHz, almost the full frequency range
available with the function generator). Find the lower cut off
frequency and upper cut off frequency.
5. Find the input signal amplitude at which output starts getting
clipped (for an input frequency in the mid band region).
6. Measure the input resistance and the output resistance of
the circuit. (For an input frequency in the mid band
region).Use
appropriate
potentiometers
for
the
measurements.
7. Connect a load resistance RLof 1k and find the input
resistance.
8. Connect a series resistance Rs of 4.7k between the signal
source and Cc1and find the output resistance.
9. Connect a variable load resistance RLof 0 5k at the output
and find the gain for different values of R L(5k, 1k, 500,
200, 100, 50, 20). Plot the load characteristics (Gain
V/S RL).
10.
(Simulation experiment only) With a series resistance R s
of 4.7k between the signal source and Cc1, connect a
capacitor of 10nF as load of emitter follower and find the
upper cut off frequency. Repeat the same by avoiding emitter
follower in between.

EXPECTED OBSERVATIONS AND RESULT:


The gain of the circuit is close to unity meaning that it
provides a path where the signal at the input of the side of
the circuit is almost entirely passed as such to the load.
The frequency response of the circuit has a lower cut off in
the range of a few hertz and upper cut off in the megahertz
range. The initial fall off of gain at lower frequencies is due
to the input coupling capacitor which provides high
impedance at lower frequencies. At higher frequencies the
internal junction capacitances of the transistor cause the
gain to decrease (by providing a low impedance).
The input impedance of the circuit is high and the output
impedance is low. Introducing a series resistance further
decreases the output impedance. On connecting a load
resistance the input impedance decreases as the load being
in parallel with emitter resistance causes the effective

49

resistance at the emitter to decrease and hence the input


impedance also reduces.
The gain of the circuit varies with load resistance. Lower
values of resistance result in a lower value of gain. Gain
increases with load resistance and tend to saturate at a
value (less than) near 1 at higher values of RL
A capacitive load in the circuit cause the frequency
response to vary in shape as the capacitor being frequency
dependent provides different load impedances at different
frequencies.

EXPECTED WAVEFORMS

50

SIMULATION RESULTS (SAMPLE WAVEFORMS)


With a series resistance Rs of 4.7k between the signal source and
Cc1, connect a capacitor of 10nF as load of emitter follower and find
the upper cut off frequency. Repeat the same by avoiding emitter
follower in between.

FREQUENCY RESPONSE (WITH EMITTER FOLLOWER)

10

100

1K

10K

100K

1M

51

WITHOUT EMITTER FOLLOWER


SAMPLE NETLIST IN NGSPICE
Emitter follower
*.tran 1us 1ms
rb 3 2 270k
re 1 0 560
rs 4 6 4.7k
cin 2 6 22n
cout 1 5 22n
c1 1 5 22n
c2 1 5 22n
cl 5 0 10n
q1 3 2 1 TT
vd 3 0 10v
VIN 4 0 ac 1 SIN ( 0 1 10k 0.0 0.0 )
.model TT npn bf=600 vaf=90
.ac dec 10 .01 10MEG
10

*plot v(1)
.end

Experiment:

PHASE SHIFT OSCILLATOR


AIM
1. To design, set up and test a BJT based phase shift oscillator to
generate a sinusoidal signal of 10 kHz, using a supply voltage of
10V.

COMPONENTS REQUIRED
1. BC547B
2. Resistors

100K
10K
1K
100

52

3.
4.
5.
6.
7.
8.

Capacitor
Multimeter
Breadboard
Supply wire
DC power supply
CRO

CIRCUIT DIAGRAMS

THEORY& DESIGN
Basic operation of an Oscillator
An amplifier with positive feedback results in oscillations if the
following conditions are satisfied:
o
The loop gain (product of the gain of the amplifier and the
gain of the feedback network) is unity
o
The total phase shift in the loop is 0o
If the output signal is sinusoidal, such a circuit is referred to as
sinusoidaloscillator.
When the switch at the amplifier input is open, there are no
oscillations. Imagine that a voltage V i is fed to the circuit and the
switch is closed. This results in Vo= Av Vi and Vf = Vo is fed back to
the circuit. If we make Vf= Vi, then even if we remove the
inputvoltage to the circuit, the output continues to exist.

53

Vo = A v V i
Vf = Vo
Vf = A v V i
If Vf has to be same as Vi, then from the above equation, it is clear
that, A=1.
Thus, by closing the switch and removing the input, we areable to
get the oscillations at the output if A=1, where A is called the
Loop gain.
Positive feedback refers to the fact that the fed back signal is in
phase with the inputsignal. This means that the signal experiences
0ophase shift while traveling in the loop.
The above condition along with the unity loop gain needs to be
satisfied to get thesustained oscillations. These conditions are
referred to as Barkhausen criterion.
Another way of seeing how the feedback circuit provides operation
as an oscillator is obtained by noting the denominator in the basic
equation
= A / (1-A)
.
When A = 1 or magnitude 1 at a phase angle of 0 o, the
denominator becomes 0 andthe gain with feedback A fbecomes
infinite. Thus, an infinitesimal signal ( noise voltage) can provide a
measurable output voltage, and the circuit acts as an oscillator even
withoutan input signal.

RC Phase shift Oscillator Using BJT


The basic RC Oscillator which is also known as a Phase-shift
Oscillator, produces a sine wave output signal using regenerative
feedback obtained from the resistor-capacitor combination. This
regenerative feedback from the RC network is due to the ability of
the capacitor to store an electric charge, (similar to the LC tank
circuit).
This resistor-capacitor feedback network can be connected to
produce a leading phase shift (phase advance network) or
interchanged to produce a lagging phase shift (phase retard

54

network) the outcome is still the same as the sine wave oscillations
only occur at the frequency at which the overall phase-shift is 360 o.
By varying one or more of the resistors or capacitors in the phaseshift network, the frequency can be varied.
If all the resistors, R and the capacitors, C in the phase shift network
are equal in value, then the frequency of oscillations produced by
the RC oscillator is given as:
fr =
Where:

r is the Output Frequency in Hertz


R is the Resistance in Ohms

C is the Capacitance in Farads

N is the number of RC stages. (N = 3)

Since the resistor-capacitor combination in the RC Oscillator circuit


also acts as an attenuator producing an attenuation which can be
used to obtain a total gain of unity.
The loading effect of the amplifier on the feedback network has an
effect on the frequency of oscillations and can cause the oscillator
frequency to change. Then the feedback network should be driven
from a high impedance output source and fed into a low impedance
load such as a common emitter transistor amplifier but better still is
to use an Operational Amplifier as it satisfies these conditions
perfectly. Also, the last resistor in the rc circuit can be connected in
series to the transistor input and manipulated such that the total
resistance including the input resistance can be made as per the
design.
From Barkhausen criterion (A= 1 <0o),
We obtain

frequency of oscillation, f=

Transistor Gain, = 23+29

55

Where

R=resistance in the RC circuit


RC=collector resistance of the amplifier

But due to non linearity factors, the gain is taken above one so that
the oscillations build up and get sustained at unit gain.
> 23+29

PROCEDURE
1. Assemble the three RC sections in cascade (with equal R-C
values ) as a third order high pass filter ( with Rs connected to
ground).
2. Apply a 10V sinusoidal signal of 10kHz and observe the
magnitude and phase of the voltage gain of this network.
Output is measured as the voltage across the third R.
3. Design and set up CE amplifier portion of the circuit.
4. Note down the values of IC , VCE , VRE ,VR1 ( without applying input
signal) and ensure that required Q point is obtained. Find out
the reason for shift in Q point and adjust the bias to get the
required Q point if it is not obtained.
5. Apply a 10 mV sinusoidal signal of frequency in mid-band region
through a capacitance CC1 = 1F and measure the output signal
amplitude. Observe the mid band voltage gain. Check whether
the measured gain closely matches with the required gain.
6. Measure the input resistance Rin.
7. Change the third R in the RC section with R = R Rin and
combine it with CE amplifier to the oscillator.
8. Change the value of R and vary it to get the sinusoidal
oscillation.
9. Measure the amplitude and frequency of oscillation.

EXPECTED OBSERVATIONS AND RESULT


The amplifier stage is accomplished using a CE amplifier which
is designed to produce a large enough small signal gain (A
125) required for the oscillator.

56

The RC network acts as a third order filter (HPF) with each RC


network providing a phase totaling to 180 o at a particular
frequency. The circuit may not provide an exact 180 phase
shift at the designed frequency as RC values tend to vary from
the calculated values. But the shift will tend to 180 o at some
frequency near the required value.
Although A is found to be greater than 1, this is required so
as to build up the output to a suitable amplitude after which
non linearities in the circuit cause the gain to drop to 1 and
hence sustain the output at a particular voltage.
Use of the potentiometer for R allows us to tune the circuit so
as to get the required output frequency. It also provides a
certain amount to manual tunability to the circuit wherein
varying R can slightly change the output frequency and its
amplitude.

EXPECTED GRAPHS
Output Wave

RC Network

57

EXPERIMENT: 7

SAMPLE NETLIST IN NGSPICE

Phase shift oscillator


.tran 1us 1ms
q1 3 2 1 bc548c
r1 2 5 37.7k
r2 2 0 8k
re 1 0 180
ra 6 0 6.2k
rb 7 0 6.2k
rc 3 5 820
rx 8 2 3.8k
c1 3 6 1n
c2 6 7 1n
c3 7 8 1n
ce 1 0 22u
cc 3 9 1u
rl 9 0 5000k
vcc 5 0 10v
.MODEL bc548c NPN (
+ AF= 1.00E+00 BF=543.1 BR= 2.42E+00 CJC= 5.17E-12
+ CJE= 1.33E-11 CJS= 0.00E+00 EG= 1.11E+00 FC= 9.00E-01
+ IKF= 1.80E-01 IKR= 1.00E+00 IRB= 1.00E+01 IS= 1.95E-14
+ ISC= 1.00E-13 ISE= 1.31E-15 ITF= 1.03E+00 KF= 0.00E+00
+ MJC= 3.19E-01 MJE= 3.26E-01 MJS= 3.30E-01 NC= 2.00E+00
+ NE= 1.32E+00 NF= 9.93E-01 NR= 1.20E+00 PTF= 0.00E+00
+ RB= 2.65E+01 RBM= 1.00E+01 RC= 1.73E+00 RE= 1.00E+00
+ TF= 6.52E-10 TR= 0.00E+00 VAF= 9.17E+01 VAR= 2.47E+01
+ VJC= 3.39E-01 VJE= 6.32E-01 VJS= 7.50E-01 VTF= 1.65E+00
+ XCJC= 1.00E+00 XTB= 0.00E+00 XTF= 1.00E+02 XTI= 3.00E+00)
*.ac dec 10 50 3MEG
.end

58

FEEDBACK AMPLIFIER
OBJECTIVE: To understand the advantages of feedback
in an amplifier configuration
AIM:
1. To design and set up a series-shunt feedback amplifier with a
Voltage gain of 10 using a 20 V power supply.
2. To test the performance of the amplifier by measuring transient
and frequency responses.

COMPONENTS REQUIRED:
1.
2.
3.
4.
5.
6.
7.
8.

JFET(BFW10)
BC547
Resistors
Capacitors
Breadboard
Multimeter
CRO
CRO Probe

CIRCUIT DIAGRAM

59

fig.1 Feedback Amplifier

JFET

Amplifier

CE Amplifier

THEORY:
A negative
feedback
amplifier (or feedback
amplifier)
is
an electronic amplifier that subtracts a fraction of its output from its
input, so that negative feedback opposes the original signal. The
applied negative feedback improves performance (gain stability,
linearity, frequency response, step response) and reduces sensitivity
to parameter variations due to manufacturing or environment.

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Because of these advantages, many amplifiers and control systems


use negative feedback.
Such an amplifier consists of two sections:
An amplifier block A which provides a large enough gain A.
A feedback network which samples a part of the output and
mixes it with the input with a gain .
Here a series shunt feedback configuration is used where the output
voltage is sampled and in the input side a fraction of this is mixed
with the input (in series with the input loop).

A Block

The amplifier section here consists of two amplifier sections


consisting of a JFET amplifier with a gain 2 and a CE amplifier
section with a large small signal gain of around 400. The two
sections are cascaded to get a large net gain. Let this gain be A.
The JFET amplifier itself has a feedback incorporated in it due to the
resistor RS providing a net gain of

. Here Rc actually

represents the net output resistance as seen by the signal and can
vary due to loading of the next section.
The CE amplifier is made so as to provide a gain of around 400 = A 2.
Its gain is given by the expression
The net gain can be taken as A = A 1A2 800 if we were to neglect
loading effects but in practice loading significantly reduces the gain,
but it remains large enough to be incorporated in the feedback
amplifier.

Block
The network is constituted by a network of resistors which act as
an attenuator sampling the output voltage and taking a part of it to
the input. Here is in terms of voltage gain and is found to be less

61

than 1. This is accomplished by the two resistors R f and RS which act


as a voltage divider giving,
The network is to be an ideal network with gain but it does
provide some loading effect at the input and output of the network
which is given as:
R11= Rf || RS, which is kept in series with the input loop, and
R22= Rf + RS, which is placed parallel to the output.
With these effects incorporated in the A block, the network can be
taken as an ideal attenuator.

Closed loop gain


On connecting the feedback loop the net gain reduces to a value
given as;

Although the gain is found to decrease the stability of the circuit


increases as the circuit gains becomes more and more independent
of any variations in A. As A tends to large values the net gain
becomes, Af= 1/.
In this circuit the expressions can be found to be Af= 1+ (Rf/RS) 10.

DESIGN:
JFET amplifier:
Take IDSS = 10mA and VP = -3V. ID=2mA.
Calculate VGS required using the relation

Calculate RS using the relation VGS=-ID RS.


Calculate gm of the JFET.
Design RD such that voltage gain of JFET amplifier is -3. (

Calculate VDS=VCC-ID(RD+RS). Operating point (ID,VDS).

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Take RG=1M(for high input resistance of the amplifier).


Take CC1 and CC2 as 1F(such that they act short for operating
frequencies in kHz range.

CE amplifier:
Same as that in experiment 3.
To find RF:
Overall gain of the feedback amplifier is 10.
Avf (for large AV).

PROCEDURE
1. Design and set up the JFET amplifier circuit.
2. Note down the values of ID, VDS.
3. Apply a 10mV (or less) sinusoidal signal of frequency in midband region (10kHz) and measure the output signal amplitude.
Hence calculate mid band voltage gain. Make sure that |Voltage
gain|>2.
4. Measure the frequency response of the voltage gain. Find the
lower cut off frequency and upper cut off frequency.
5. Design and set up the CE amplifier circuit in fig. 3
6. Note down the values of IC, VCE, VRE, VR1 and ensure that
required Q point is obtained.
7. Apply a 10 mV sinusoidal signal of frequency in mid-band
region (10 kHz)and measure the output signal amplitude.
Hence calculate mid band voltage gain .Make sure that |Voltage
gain|>250.
8. Cascade the circuits in fig.2 and fig.3
9. Apply a 10mV sinusoidal signal of frequency in mid-band region
(10 kHz) and measure the output signal amplitude. Hence
calculate mid band Voltage gain.
10.Connect the resistor RF and capacitor CC4 to get the seriesshunt feedback amplifier.

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11.Apply a 10mV sinusoidal signal of frequency in mid-band


region (10 kHz) and measure the output signal amplitude and
calculate mid band voltage gain.
12.Measure the input resistance and the output resistance of the
series-shunt feedback amplifier.

EXPECTED OBSERVATIONS AND RESULT:


The amplifiers individually provides gains as calculated,
cascading them together results in a decrease of individual
gain of JFET due to loading effects of the CE amplifier at the
output of the JFET amplifier.
The net gain of the feedback become independent of the
device parameters and equal to the inverse of the feedback
factor. (An approximation of the feedback gain when amplifier
gains become very high).
Due to the feedback mechanism, the gain reduces, bandwidth
extends (observed in simulation), input resistance increases
and output resistance decreases creating an almost ideal
voltage controlled voltage device.

EXPEXTED GRAPHS
JFET output

CE Amplifier Output

64

Feedback Amplifier Output

SIMULATION

65

CE Amplifier

66

JFET Amplifier

67

Cascaded Amplifier

68

Feedback Amplifier

69

SAMPLE NETLIST IN NGSPICE


cascade
j1 1 2 3 jj
rd 4 1 2.2k
rg 2 0 1meg
rs 3 0 470
cc1 6 2 1u
cc2 1 5 1u
q1 7 5 8 tt
rb1 4 5 259k
rb2 5 0 42.9k
rc 4 7 4.7k
re 8 0 1k
rl 9 0 50MEG
cc3 7 9 1u
ce 8 0 22u
vcc 4 0 20
vi 6 0 dc 0 ac sin(0 .01 10k 0 0)
.model jjnjf(vt0=-3 beta=3.65m)
.model ttnpn (bf=600 vaf=90)
.end

EXPERIMENT: 8

CLASSAB PUSH PULL


POWER AMPLIFIER

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OBJECTIVE: To understand the importance of


power amplifier in output stage realizations

AIM:
1. To design and set up a class AB Push Pull Power Amplifier to
deliver a maximum ac power of 1W to a load of 10.
2. To test the performance of the amplifier by appropriate
measurements.
COMPONENTS REQUIRED:
1.
2.
3.
4.
5.
6.
7.

BC547B
Resistors
Capacitors
Breadboard
CRO
Multimeter
Diode-1N4

CIRCUIT DIAGRAMS:
THEORY:

Power amplifier
Small signal amplifiers are mainly used for signal processing and
other purposes. Now after signal processing, we need power at the
output stage of the system. So all electronic systems actually, the

71

initial stages are the small signal amplifiers, which are used for data
processing and signal processing, and the output stage is a power
amplifier.
Power amplifiers deliver required power to the output device for
example, power is required to run a motor at the end or a printer. In
power amplifiers, we talk of powers in the range of half watt to
several tens or several hundred watts and even more. While in a
small signal amplifiers, these are quite small less than 500 milli
watts in general. Conversion efficiency is basically with what
efficiency, the amplifier converts dc into the useful ac signal. Power
transistor should have larger surface area as compared to a small
signal transistors, so that it can deliver and it can handle large
powers. When the device is dealing with large powers then heating
will be created. These are broadly the three types of power
amplifiers; class A power amplifier, class B power amplifier, class C
power amplifier.

Class B Power Amplifier


Class B amplifier is obtained by biasing it at 0 DC current. Therefore,
each of the transistor conducts for only half the input wave cycle. Its
conduction angle is 180 degrees. In the circuit given, class B
amplifier is obtained by shorting the two diodes shown in figure. One
of the most widely used amplifiers today is the class B push-pull
power amplifier. It is clear from the circuit that we have used
complementary transistors, one is npn and the other is a pnp
transistor. The emitter of both transistors are connected together
and a load is connected to this common terminal.
When the input voltage is between 0.5V and -0.5V, both the
transistors remain off so there is no output. As a result there is a
distortion of the input signal at the output, this distortion is called
cross-over distortion. When the input voltage reaches 0.5V, the first
transistor just turns on and as its further increased, so does the
output voltage. When the input voltage drops below -0.5V, the lower
transistor turns on and it continues to conduct. In both cases, one of
the transistor is conducting while the other remains off.

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Class AB Power amplifier


It is biased at non zero DC current that is much smaller than
amplitude of signal current. As a result, it is slightly less efficient
than a class B power amplifier. The diodes shown in the circuit
ensure that there is a voltage drop of 1.4V across the BE junction of
both the transistors thereby helping to avoid the cross over
distortion. Current through the biasing network is taken to be 2mA to
ensure that both the transistors are turned on.

DESIGN:
The VCC can be designed from the equation

Current is taken to be 2mA and the drop across both the diodes
is approximately 0.7V also current through the transistors is
assumed to be approximately 0. Therefore writing the KVL
equation, we get

CC1 and CC2 are chosen such that at the operating frequency,
their impedance is negligible.
In the second circuit, Q3 is designed as an inverting amplifier
of gain 5. The remaining portion of the circuit is same as given
above. VRE was assumed to be 10% of VCC and we know that IC
is 2mA from these values, we can calculate the value of R E

We know that VR2 is 1.7V so by ohms law, we can calculate the


value of R2. R1 is calculated by assuming a current of 20I B
flowing through it. Our next assumption is that the voltage
drop across VCE is half of VCC this is to ensure maximum swing.
Next by applying KVL, we can calculate the value of RC

The value of the capacitors are chosen such that at the operating
frequency, their impedance is negligible.

73

PROCEDURE:
1. Design and set up the circuit in the figure 1 without diodes to
get class B circuit.
2. Apply a 2V peak sinusoidal signal of frequency 5 kHz and
observe the cross over distortion in the output signal.
3. Find the signal amplitude at which the output gets clipped.
4. Design and set up the class AB circuit in the figure 1.
5. Apply a 2V peak sinusoidal signal of frequency 5 kHz and
6.
7.
8.
9.

observe the output signal.


Measure the maximum ac output power.
Calculate the conversion efficiency .
Connect a variable load and plot output power VsRL.
Connect a resistance of 2k (RS) series with signal source and

measure the output power delivered to 10 load resistor.


10.
Design and set up the circuit in the figure 2. Adjust C E for
the required voltage gain.
11.
Do the power output measurement without output
clipping (step 9).
12.
Connect a 8 speaker to the signal source directly and
hear the audio output.
13.
Remove RL and connect the 8 speaker as the load of
amplifier and hear the audio output and feel the effect of
power amplifier.

EXPECTED OBSERVATIONS AND RESULT:


1. In class B amplifiers due to the absence of a DC bias a
crossover distortion is observed in the output due to the
BE voltage of the transistor.
2. The efficiency of an AB amplifier is lower than a class B
amplifier as the AB amplifier has a small DC bias and
hence a current ( when VO = 0)
3. Use of a driver stage in the AB amplifier design can
increase power gain and also reduce the effect of source
resistances (loading effects) on the final output.

74

4. The output power is maximum at a load value and is seen


to fall off on either sides. This happens as the load
resistance is matched with the output impedance of the
AB amplifier so as to deliver max power.
5. The effect of power amplification can be felt on connecting
a speaker at the input and output. The output produces a
much louder sound. The lack of any sensible distortion in
the output sound indicates the class AB does not distort
the signal.

EXPECTED WAVEFORMS

75

Load Resistance v Power

Input Signal

Class B Output

76

Class AB Output

Class AB Amplifier with RS

77

Class AB With CE Amplifier Driver stage :


Input signal

Output without RS

78

Output with RS

SIMULATION

79

Input Wave

Class B output

80

Class AB Output

Class AB with RS

With CE Driver Stage input

81

Output

SAMPLE NETLIST IN NGSPICE

power
q1 1 3 5 ttn
q2 0 4 5 ttp
r1 1 3 1.8k
r2 4 0 1.8k
rl 6 0 10
c1 2 3 10uf
d1 3 7 dd1
d2 7 4 dd1
*r3 3 4 0
c2 2 4 10uf
c3 5 6 100uf
Vi 8 0 SIN(0 5 5k 0 0 )
rs 8 2 2k
vcc 1 0 9v
.MODEL ttn NPN ( IS=290.83E-15 BF=113.55 VAF=100 IKF=1.9905 ISE=1.3946E12 NE=1.4763 BR=.1001 VAR=100 IKR=10.010E-3 ISC=320.65E-12 NC=1.8994
NK=.58929
+ RB=.71129 CJE=348.44E-12 VJE=.78228 MJE=.42865 CJC=184.26E-12
VJC=.47897 MJC=.40458 TF=36.381E-9 XTF=100.32 VTF=21.563 ITF=28.791
TR=10.000E-9 )
.MODEL ttp PNP (IS=442f NF=1.00 BF=137 VAF=180
+ IKF=1.21 ISE=377p NE=2.00 BR=4.00 NR=1.00
+ VAR=20.0 IKR=3.00 RE=53.6m RB=0.214 RC=21.4m
+ XTB=1.5 CJE=336p VJE=0.600 MJE=0.300 CJC=122p VJC=0.220
+ MJC=0.200 TF=26.5n TR=4.64u EG=1.12 )
.MODEL dd1 d
+IS=7.02767e-09 RS=0.0341512 N=1.80803 EG=1.05743
+XTI=5 BV=1000 IBV=5e-08 CJO=1e-11
+VJ=0.7 M=0.5 FC=0.5 TT=1e-07
+KF=0 AF=1

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84

85

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