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LAB MANUAL
EC 2028: ELECTRONIC CIRCUITS LABORATORY I
Syllabus
Course Outcomes:
CO1: Develop the ability to Design and implement discrete analog
amplifiers to meet the given specifications.
TABLE OF CONTENTS
SL
NO.
EXPERIMENT NAME
1.
2.
TRANSISTOR AS SWITCH
3.
4.
MULTIVIBRATORS
5.
EMITTER FOLLOWER
6.
7.
8.
POWER AMPLIFIER
Experiment: 1
STUDY OF BIASING
CIRCUITS
OBJECTIVE: To understand different transistor
biasing circuits and to
appreciate the advantage of one above the
other.
AIM
To design, set up and study the performance of transistor biasing
circuits (fixed biasing and voltage divider biasing).
COMPONENTS REQUIRED
1.
2.
3.
4.
5.
6.
7.
8.
Power supply
CRO
Breadboard
Multimeter
Resistors
BC547
SL100
Capacitors
Figure 1
GRAPH
: LOAD LINE
Figure 2 : (a) Fixed Bias Configuration (b) Voltage Divider Bias of NPN
Transistor
THEORY& DESIGN
INTRODUCTION
FIXED BIAS
This is one of the simplest transistor biasing configurations
where we reach the operating point by making use of a
single DC supply, an input signal and two resistors. In this
biasing circuit, we fix the base current IB to the transistor.
This is achieved by taking the VCC to the base via the resistor
RB to provide the constant current. The collector current I C
can be fixed as per requirement by using a suitable resistor
RC.
Although, simple and easy to build, this design faces a lot of
stability issues such as the variation of with temperature
or IC. Hence, the circuit parameters depend on and any
changes in (e.g. If the transistor is changed) can affect the
output of the circuit.
Design
PROCEDURE
1. Different breakdown voltages, (Min, Typ and Max)
and maximum collector current of BC547B and SL100
were noted down from their data sheet.
2. Design and assemble the Fixed Biasing circuit for the
BC547B transistor to operate it at points A, B and C in
the given load line.
3. Measure the values of collector voltage (V C), Emitter
voltage (VE) and Base voltage (VB) of the transistor,
verify the operating points and VBE value in each case.
is calculated by measuring IC and IB.
4. Repeat steps (2) and (3) for Voltage divider biasing
circuit.
5. Apply a sine wave of amplitude (20mVpp, 1kHz) in the
voltage divider circuit through a 10F capacitor. Vary
the amplitude of the input waveform and observe
output waveform at collector of the transistor through
another 10 F capacitor.
6. The maximum amplitude of input signal that can be
given to the circuit is noted so that the output is
undistorted.
7. Replace BC547B with SL100 in both the biasing circuits.
Step (3) is repeated.
8. Compare the bias stability of the two biasing circuits
based on the results
10
11
PRE REQUISITES
For BC547B, from datasheet, the following values were
observed:
IC MAX = 100 mA
Breakdown Voltages: VCBO = 50 V
VCEO = 45 V
VCEO = 50 V
12
Experiment: 2
TRANSISTOR AS
SWITCH
OBJECTIVE: To familiarize different
transistor switching configurations so as
to choose a suitable one for practical
realizations
AIM
To design, set up and study the performance of
transistor switching circuits.
COMPONENTS
1. Resistors
2. Capacitors
3. Transistor BC547B
4. Transistor SL500
5. DC power source
6. Multimeter
7. Connecting wires
8. Breadboard
CIRCUIT DIAGRAMS
Figure. 1
13
Figure. 2
Figure. 3
Figure. 4
THEORY
14
Transistor as a switch.
Solid state switches are one of the main applications for the use
of transistors, and transistor switches can be used for controlling
high power devices such as motors, solenoids or lamps. The
areas of operation for a Transistor switch are known as the
saturation region and the Cut-off Region.
1. Cut - off region
The operating conditions of the transistor are zero input
base current (IB), zero output collector current(I C) and
maximum collector voltage (VCE) which results in a large
depletion layer and no current flowing through the device.
Therefore the transistor is switched Fully OFF. The cutoff region or OFF mode when using a bipolar transistor
as a switch can thus be defined as both junctions reverse
biased,VB <0.7v and Ic=0.For a PNP transistor, the Emitter
potential must be negative with respect to the base.
2. Saturation Region
The transistor will be biased so that the maximum amount
of base current is applied , resulting in maximum collector
current resulting in the minimum collector emitter voltage
drop which results in the depletion layer being as small as
possible and maximum current flowing
through the
transistor. So the transistor is switched Fully-ON. Both
junctions are forward biased, VB > 0.7v and for a PNP
transistor, the emitter potential must be positive with
respect to the base.
For transistor switching action, we exploit the cut off and
saturation regions of the transistor. A zero input voltage ensures
the transistor to be in the cut off region providing a high output
voltage of VCC.For obtaining a low output a saturation current I C is
required to flow through the transistor .In order to ensure
saturation a Base Current which is greater than that
corresponding to saturation current. The collector current is fixed
as required at the output using the collector resistance R C.A base
current that ensures saturation is obtained by fixing the base
resistance RC.
15
Relay
Relays are components which allow a low-power circuit to switch
a relatively high current on and off, or to control signals that
must be electrically isolated from the controlling circuit itself. In
our experiment, we make use of the transistor switching circuit
16
FIGURE 1
FIGURE 2
17
VC (
)=3V
FIGURE 3
VC = Vf + (Vini- Vf)
Vf =
Vini=
C=
FIGURE 4
PROCEDURE
1. The circuit was designed as in fig. 1 for I Csat = 2mA and VCC
= 10V.
2. Apply an input Vi as a pulse waveform of 0-5V and observe
the output for voltage levels, rise time and fall time when
the input frequency is (a) 1 kHz, (b) 5 kHz, (c) 500 kHz.
3. Design the circuit in fig. 2 for I Csat = 2mA and VCC = 10V
under the assumption that voltage drop across the LED
when it is ON is VLED = 1.5V.
4. Apply input voltage (Vi) as a square wave of amplitude 0-5V
and note the behavior of the LED by varying the input
frequency.
5. Design the circuit as in fig. 3 for a collector current of 2mA
and VCC = 10V such that the output V o reaches 3V at the
end of the OFF state of the transistor for a 1 kHz square
wave input of 0-5V.
6. Observe and plot the output wave form of this circuit.
Repeat this for half and double the calculated capacitor
values and note the changes.
7. Design the circuit as in fig. 4 after identifying the terminals
of the relay. A normal diode may be placed across the relay.
8. Connect the bulb and 12V source between the C and N/C
terminals and observe the behavior of the bulb for high (V i
= 5V) and low (Vi = 0V) inputs.
9. Observe the behavior of the bulb when the bulb and the
12V supply are connected across the C and N/C terminal of
the relay.
18
EXPECTED OBSERVATIONS
Rise time is greater than the fall time for BC547B.
Rise time is of the order of 10s and fall time is lower than
5s.
The rise time and fall time, both are independent of input
frequency as long as its within the operating frequency of
the specified transistor.
At higher frequency (500KHZ), it was observed that the
transistor remains on. This happens because the transistor
is not getting enough time to switch between saturation
and cut-off. Time period of input pulse is 2s (1/500), the
rise time of transistor is around 10s. From these
observations its clear that the transistor remains on.
From the second part of the experiment it was observed
that the LED blinks at low frequency. But at a slightly higher
frequency of about 50HZ, the blinking visually stops.
After adding a capacitor (0.33F) between the collector and
emitter of the transistor as shown in the third part of the
experiment, it was observed that the output voltage rises to
a maximum of 3V.
If we decrease the capacitance value, it takes smaller time
for the capacitor to charge. So the output voltage rises to a
larger value.
If we increase the capacitance value, output voltage rises
to a smaller value.
It was also observed that at lower capacitance value, the
curve becomes visually more exponential in nature.
When the relay is not energized (no current is flowing
through the relay), at the output side, there is a connection
between the N/C and C terminal.
When the relay is energized, there is a connection between
the N/O and C terminals. The N/C terminal is left open.
The diode connected in parallel to the relay protects the
transistor from the back EMF by providing a path for the
energy stored in the relay to dissipate.
VIN
Light
N/C
0V
ON
5V
OFF
Normally Closed
19
N/O
Normally Open
0V
OFF
5V
ON
t (ms)
Vc (V)
t (ms)
Vc (V)
CC =2*0.33F
=0.5*0.33F
2 xCalculated
Calculatedvalue
value/ 2
t (ms)
20
21
EXPERIMENT: 3
COMMON EMITTER
AMPLIFIER
OBJECTIVE: To understand and appreciate the
importance of Common Emitter amplifier
AIM:
1. To design and set up a Common Emitter (CE) amplifier with
the following specifications
(i) Voltagegain >100
(ii) Minimum input frequency=500Hz
With the transistor operating at the Q point I c=2mA using a 12V
power supply, for a resistive load 50k.
2. To test the performance of the amplifier by measuring
transient and frequency responses.
COMPONENTS REQUIRED:
1.
2.
3.
4.
5.
6.
7.
8.
Transistor BC547B
Resistors
Capacitors
Breadboard
Multimeter
CRO
DC power supply
Potentiometer
CIRCUIT DIAGRAMS:
22
Figure 1
23
CE Amplifier
There are three basic configurations for connecting the BJT as an
amplifier. Each of these configurations is obtained by connecting
one of the three BJT terminals to ground. Thus the grounded
terminal is common to both the input and output ports. In
common-emitter configuration, the emitter terminal is connected
to ground, the input voltage signal is vi applied between the base
and ground.
The upper cut-off frequency FH is defined as the frequency
beyond which there is an attenuation of more than 3dB. The
lower cut-off frequency FL is defined as the frequency below
which the attenuation is greater than 3dB. Bandwidth of the
transistor is the difference between FH and FL. Maximum gain is
available at frequencies within the bandwidth of the transistor.
Also the upper cut-off frequency can be obtained from the figure,
by using the equation
24
DESIGN:
25
PROCEDURE
1. Design and set up the circuit as shown in the figure1.
2. Observe the values of IC; VCE; VRE; VR1 (without applying input
signal) and ensure that requiredQ point is obtained. If not,
find out the reason for shift in Q point and adjust the bias to
get the required Q point.
3. Apply a 10mV (or less) sinusoidal signal of frequency in
mid-band region and measure the output signal amplitude.
Then, calculate mid band voltage gain.
4.
5. Find
the
lower
cut-off
frequency
and
upper
cut-off
26
27
EXPECTED GRAPHS
28
29
V (V)
t (us)
WITHOUT CAPACITOR CE
30
V (mV)
t (ms)
V (mV)
t (ms)
V
V (mV)
t (ms)
NOTE:
31
32
33
Experiment: 4
MULTIVIBRATORS
OBJECTIVE: To study and realize basic multivibrator
circuits used practically for many timing operations
AIM
1. To design, set up and test an astablemultivibrator with BJT s
to generate a square voltage signal of 1 KHz for an output
load current of 50A (The supply voltage is 5V).
2. To design, set up and test a monostablemultivibrator with
BJTs to generate a pulse signal of width 750s with collector
currents of 5mA (The supply voltage is 5V).
COMPONENTS REQUIRED
1.
2.
3.
4.
5.
6.
7.
8.
Transistor BC547B
Resistors
Capacitors
Breadboard
Supply wires
Multimeter
DC power source
CRO
CIRCUIT DIAGRAMS
AstableMultivibrator
MonostableMultivibrator
34
THEORY& DESIGN
MULTIVIBRATORS:
A multivibrators an electronic circuit used to implement a variety
of simple two-state systems such as oscillators, timers and flipflops. It is characterized by two amplifying devices cross coupled
by resistors and capacitors. There are three types of
multivibrators circuits depending on the circuit operation:
Astablemultivibrator,
Monostablemultivibrator and
Bistablemultivibrator
These circuits find application in a variety of systems where
square waves or timed intervals are required.
ASTABLE MULTIVIBRATORS
An astablemultivibrator consists of two amplifying stages
connected in a positive feedback loop by two capacitive-resistive
coupling networks. This is generally used as square wave
generator. The circuit has two unstable states and hence oscillate
back and forth between these states.
The BJT astablemultivibrator (as in the fig) has two transistor (Q1
and Q2) switches which are cross couples together through
resistors and capacitors (R1-C1 and R2-C2) which decide the
duration of each unstable state. The output may be obtained at
either VC1 or VC2 with a phase shift of 180o.
Working:
Based on the load and current requirements (I C) the resistors
Rccan be fixed.
35
Similarly,
And Duty cycle for this wave is
and frequency =
MONOSTABLE MULTIVIBRATORS
A monostablemultivibrator as the name indicates has one stable
state and one unstable state. This operates such that a trigger
applied to the circuit causes it to move to its unstable state for a
short amount of time and then return back to the stable state. It
is used when a time interval based application is necessary and
also as a frequency divider.
This circuit is achieved by replacing one of the capacitiveresistive network of an astablemultivibrator with resistive
network (as in the fig).
Working:
The output is taken as VC1=Vo. Hence resistors Rccan be fixed so
as to receive the required output current.
And
36
After this duration the capacitor voltage reaches V BEsat at the base
of Q1 and Q1 switches ON causing the output voltage to reduce
and hence going back to its stable state till another trigger is
applied.
The value of the resistor R1 and R2 can be calculated such that
whenQ2 is on R2 has a drop of VBEsatacross it and also provides the
necessary base current (IB = IC/) required. Also it is assumed
that IR1 is 1/10th of the collector current.
Triggering:
The trigger pulse is generated using a differentiator circuit
connected to the collector terminal of Q2. This is set up such that
, where t is time period of the square wave
which is to be differentiated. A diode (in reverse bias) is used to
remove the positive spikes from the differentiator output.
Speed-up Capacitor:
A speed up capacitor C1 placed parallel to R1 is used to speed up
the transitions of Q2. Any capacitor can be used for this purpose
which meets the constrains,
and
Where tontime taken for voltage to rise from 0 to 90%
of its value and toff the duration for which the output
VC1 is low before the next trigger.
PROCEDURE
1. AstableMultivibrator:
1. Design and set up the circuit.Check the proper working
of each capacitively coupled inverter.
2. Note down the voltage waveforms at the nodes V c1, Vc2,
Vb1, Vb2.
37
38
EXPECTED WAVEFORMS
ASTABLE MULTIVIBRATOR
Without Load
39
With Load
40
MONOSTABLE MULTIVIBRATOR
Without speed-up Capacitor
41
SIMULATION RESULTS
To redesign the astablemultivibrator circuit for an output
frequency (50% duty cycle square wave) of 100 kHz.
Observe the output
42
43
VC2 (V)
44
45
EXPERIMENT 5:
EMITTER FOLLOWER
OBJECTIVE: To comment upon the importance of
emitter follower circuit as a buffer
AIM:
1. To design and set up an Emitter Follower circuit with the
following specifications (i) input resistance > 100k (ii)
Minimum
input
frequency=500Hz
(iii)
maximum
symmetrical swing at the output using a 10V power supply.
2. To test the performance of the amplifier by measuring
transient and frequency responses.
COMPONENTS REQUIRED:
1.
2.
3.
4.
5.
6.
7.
8.
Resistors
Capacitors
Transistor BC547B
Multimeter
Breadboard
DC Power supply
Function Generator
CRO
CIRCUIT DIAGRAM:
Figure: Emitter
Follower
THEORY:
The common-collector (CC) circuit is a very important circuit that
finds frequent application in the design of both small-signal and
large-signal amplifiers and even in digital circuits. The circuit is
more commonly known as emitter follower.
46
. Thus
47
DESIGN:
Express REinterms of IE as:
Input resistance
>> 100k (approximate formula).
Using this expression an upper limit for IE will be obtained.Fix
the value of IE which is less than this limit and calculate RE
and RB.
Calculate the expected input resistance with the values and verify that it is
greater than 100k.
Calculate CC1 such that at an operating frequency of 500Hz , the magnitude
of impedance due to CC1 is XCC1<Rin/10.
Take CC2=CC1 (as load resistance is not mentioned)
PROCEDURE
1. Design and set up the circuit in the figure.
2. Note down the values of I C, VCE, VRE,VBE(without applying input
signal) and ensure that required Q point is obtained. If not
find out the reason for shift in Q point and adjust the bias to
get the required Q point.
48
3. Apply a 0.5V (or less) sinusoidal signal of frequency in midband region and measure the output signal amplitude. Hence
calculate mid band voltage gain.
4. Measure the frequency response (magnitude) of the voltage
gain (from 50Hz to 3MHz, almost the full frequency range
available with the function generator). Find the lower cut off
frequency and upper cut off frequency.
5. Find the input signal amplitude at which output starts getting
clipped (for an input frequency in the mid band region).
6. Measure the input resistance and the output resistance of
the circuit. (For an input frequency in the mid band
region).Use
appropriate
potentiometers
for
the
measurements.
7. Connect a load resistance RLof 1k and find the input
resistance.
8. Connect a series resistance Rs of 4.7k between the signal
source and Cc1and find the output resistance.
9. Connect a variable load resistance RLof 0 5k at the output
and find the gain for different values of R L(5k, 1k, 500,
200, 100, 50, 20). Plot the load characteristics (Gain
V/S RL).
10.
(Simulation experiment only) With a series resistance R s
of 4.7k between the signal source and Cc1, connect a
capacitor of 10nF as load of emitter follower and find the
upper cut off frequency. Repeat the same by avoiding emitter
follower in between.
49
EXPECTED WAVEFORMS
50
10
100
1K
10K
100K
1M
51
*plot v(1)
.end
Experiment:
COMPONENTS REQUIRED
1. BC547B
2. Resistors
100K
10K
1K
100
52
3.
4.
5.
6.
7.
8.
Capacitor
Multimeter
Breadboard
Supply wire
DC power supply
CRO
CIRCUIT DIAGRAMS
THEORY& DESIGN
Basic operation of an Oscillator
An amplifier with positive feedback results in oscillations if the
following conditions are satisfied:
o
The loop gain (product of the gain of the amplifier and the
gain of the feedback network) is unity
o
The total phase shift in the loop is 0o
If the output signal is sinusoidal, such a circuit is referred to as
sinusoidaloscillator.
When the switch at the amplifier input is open, there are no
oscillations. Imagine that a voltage V i is fed to the circuit and the
switch is closed. This results in Vo= Av Vi and Vf = Vo is fed back to
the circuit. If we make Vf= Vi, then even if we remove the
inputvoltage to the circuit, the output continues to exist.
53
Vo = A v V i
Vf = Vo
Vf = A v V i
If Vf has to be same as Vi, then from the above equation, it is clear
that, A=1.
Thus, by closing the switch and removing the input, we areable to
get the oscillations at the output if A=1, where A is called the
Loop gain.
Positive feedback refers to the fact that the fed back signal is in
phase with the inputsignal. This means that the signal experiences
0ophase shift while traveling in the loop.
The above condition along with the unity loop gain needs to be
satisfied to get thesustained oscillations. These conditions are
referred to as Barkhausen criterion.
Another way of seeing how the feedback circuit provides operation
as an oscillator is obtained by noting the denominator in the basic
equation
= A / (1-A)
.
When A = 1 or magnitude 1 at a phase angle of 0 o, the
denominator becomes 0 andthe gain with feedback A fbecomes
infinite. Thus, an infinitesimal signal ( noise voltage) can provide a
measurable output voltage, and the circuit acts as an oscillator even
withoutan input signal.
54
network) the outcome is still the same as the sine wave oscillations
only occur at the frequency at which the overall phase-shift is 360 o.
By varying one or more of the resistors or capacitors in the phaseshift network, the frequency can be varied.
If all the resistors, R and the capacitors, C in the phase shift network
are equal in value, then the frequency of oscillations produced by
the RC oscillator is given as:
fr =
Where:
frequency of oscillation, f=
55
Where
But due to non linearity factors, the gain is taken above one so that
the oscillations build up and get sustained at unit gain.
> 23+29
PROCEDURE
1. Assemble the three RC sections in cascade (with equal R-C
values ) as a third order high pass filter ( with Rs connected to
ground).
2. Apply a 10V sinusoidal signal of 10kHz and observe the
magnitude and phase of the voltage gain of this network.
Output is measured as the voltage across the third R.
3. Design and set up CE amplifier portion of the circuit.
4. Note down the values of IC , VCE , VRE ,VR1 ( without applying input
signal) and ensure that required Q point is obtained. Find out
the reason for shift in Q point and adjust the bias to get the
required Q point if it is not obtained.
5. Apply a 10 mV sinusoidal signal of frequency in mid-band region
through a capacitance CC1 = 1F and measure the output signal
amplitude. Observe the mid band voltage gain. Check whether
the measured gain closely matches with the required gain.
6. Measure the input resistance Rin.
7. Change the third R in the RC section with R = R Rin and
combine it with CE amplifier to the oscillator.
8. Change the value of R and vary it to get the sinusoidal
oscillation.
9. Measure the amplitude and frequency of oscillation.
56
EXPECTED GRAPHS
Output Wave
RC Network
57
EXPERIMENT: 7
58
FEEDBACK AMPLIFIER
OBJECTIVE: To understand the advantages of feedback
in an amplifier configuration
AIM:
1. To design and set up a series-shunt feedback amplifier with a
Voltage gain of 10 using a 20 V power supply.
2. To test the performance of the amplifier by measuring transient
and frequency responses.
COMPONENTS REQUIRED:
1.
2.
3.
4.
5.
6.
7.
8.
JFET(BFW10)
BC547
Resistors
Capacitors
Breadboard
Multimeter
CRO
CRO Probe
CIRCUIT DIAGRAM
59
JFET
Amplifier
CE Amplifier
THEORY:
A negative
feedback
amplifier (or feedback
amplifier)
is
an electronic amplifier that subtracts a fraction of its output from its
input, so that negative feedback opposes the original signal. The
applied negative feedback improves performance (gain stability,
linearity, frequency response, step response) and reduces sensitivity
to parameter variations due to manufacturing or environment.
60
A Block
. Here Rc actually
represents the net output resistance as seen by the signal and can
vary due to loading of the next section.
The CE amplifier is made so as to provide a gain of around 400 = A 2.
Its gain is given by the expression
The net gain can be taken as A = A 1A2 800 if we were to neglect
loading effects but in practice loading significantly reduces the gain,
but it remains large enough to be incorporated in the feedback
amplifier.
Block
The network is constituted by a network of resistors which act as
an attenuator sampling the output voltage and taking a part of it to
the input. Here is in terms of voltage gain and is found to be less
61
DESIGN:
JFET amplifier:
Take IDSS = 10mA and VP = -3V. ID=2mA.
Calculate VGS required using the relation
62
CE amplifier:
Same as that in experiment 3.
To find RF:
Overall gain of the feedback amplifier is 10.
Avf (for large AV).
PROCEDURE
1. Design and set up the JFET amplifier circuit.
2. Note down the values of ID, VDS.
3. Apply a 10mV (or less) sinusoidal signal of frequency in midband region (10kHz) and measure the output signal amplitude.
Hence calculate mid band voltage gain. Make sure that |Voltage
gain|>2.
4. Measure the frequency response of the voltage gain. Find the
lower cut off frequency and upper cut off frequency.
5. Design and set up the CE amplifier circuit in fig. 3
6. Note down the values of IC, VCE, VRE, VR1 and ensure that
required Q point is obtained.
7. Apply a 10 mV sinusoidal signal of frequency in mid-band
region (10 kHz)and measure the output signal amplitude.
Hence calculate mid band voltage gain .Make sure that |Voltage
gain|>250.
8. Cascade the circuits in fig.2 and fig.3
9. Apply a 10mV sinusoidal signal of frequency in mid-band region
(10 kHz) and measure the output signal amplitude. Hence
calculate mid band Voltage gain.
10.Connect the resistor RF and capacitor CC4 to get the seriesshunt feedback amplifier.
63
EXPEXTED GRAPHS
JFET output
CE Amplifier Output
64
SIMULATION
65
CE Amplifier
66
JFET Amplifier
67
Cascaded Amplifier
68
Feedback Amplifier
69
EXPERIMENT: 8
70
AIM:
1. To design and set up a class AB Push Pull Power Amplifier to
deliver a maximum ac power of 1W to a load of 10.
2. To test the performance of the amplifier by appropriate
measurements.
COMPONENTS REQUIRED:
1.
2.
3.
4.
5.
6.
7.
BC547B
Resistors
Capacitors
Breadboard
CRO
Multimeter
Diode-1N4
CIRCUIT DIAGRAMS:
THEORY:
Power amplifier
Small signal amplifiers are mainly used for signal processing and
other purposes. Now after signal processing, we need power at the
output stage of the system. So all electronic systems actually, the
71
initial stages are the small signal amplifiers, which are used for data
processing and signal processing, and the output stage is a power
amplifier.
Power amplifiers deliver required power to the output device for
example, power is required to run a motor at the end or a printer. In
power amplifiers, we talk of powers in the range of half watt to
several tens or several hundred watts and even more. While in a
small signal amplifiers, these are quite small less than 500 milli
watts in general. Conversion efficiency is basically with what
efficiency, the amplifier converts dc into the useful ac signal. Power
transistor should have larger surface area as compared to a small
signal transistors, so that it can deliver and it can handle large
powers. When the device is dealing with large powers then heating
will be created. These are broadly the three types of power
amplifiers; class A power amplifier, class B power amplifier, class C
power amplifier.
72
DESIGN:
The VCC can be designed from the equation
Current is taken to be 2mA and the drop across both the diodes
is approximately 0.7V also current through the transistors is
assumed to be approximately 0. Therefore writing the KVL
equation, we get
CC1 and CC2 are chosen such that at the operating frequency,
their impedance is negligible.
In the second circuit, Q3 is designed as an inverting amplifier
of gain 5. The remaining portion of the circuit is same as given
above. VRE was assumed to be 10% of VCC and we know that IC
is 2mA from these values, we can calculate the value of R E
The value of the capacitors are chosen such that at the operating
frequency, their impedance is negligible.
73
PROCEDURE:
1. Design and set up the circuit in the figure 1 without diodes to
get class B circuit.
2. Apply a 2V peak sinusoidal signal of frequency 5 kHz and
observe the cross over distortion in the output signal.
3. Find the signal amplitude at which the output gets clipped.
4. Design and set up the class AB circuit in the figure 1.
5. Apply a 2V peak sinusoidal signal of frequency 5 kHz and
6.
7.
8.
9.
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EXPECTED WAVEFORMS
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Input Signal
Class B Output
76
Class AB Output
77
Output without RS
78
Output with RS
SIMULATION
79
Input Wave
Class B output
80
Class AB Output
Class AB with RS
81
Output
power
q1 1 3 5 ttn
q2 0 4 5 ttp
r1 1 3 1.8k
r2 4 0 1.8k
rl 6 0 10
c1 2 3 10uf
d1 3 7 dd1
d2 7 4 dd1
*r3 3 4 0
c2 2 4 10uf
c3 5 6 100uf
Vi 8 0 SIN(0 5 5k 0 0 )
rs 8 2 2k
vcc 1 0 9v
.MODEL ttn NPN ( IS=290.83E-15 BF=113.55 VAF=100 IKF=1.9905 ISE=1.3946E12 NE=1.4763 BR=.1001 VAR=100 IKR=10.010E-3 ISC=320.65E-12 NC=1.8994
NK=.58929
+ RB=.71129 CJE=348.44E-12 VJE=.78228 MJE=.42865 CJC=184.26E-12
VJC=.47897 MJC=.40458 TF=36.381E-9 XTF=100.32 VTF=21.563 ITF=28.791
TR=10.000E-9 )
.MODEL ttp PNP (IS=442f NF=1.00 BF=137 VAF=180
+ IKF=1.21 ISE=377p NE=2.00 BR=4.00 NR=1.00
+ VAR=20.0 IKR=3.00 RE=53.6m RB=0.214 RC=21.4m
+ XTB=1.5 CJE=336p VJE=0.600 MJE=0.300 CJC=122p VJC=0.220
+ MJC=0.200 TF=26.5n TR=4.64u EG=1.12 )
.MODEL dd1 d
+IS=7.02767e-09 RS=0.0341512 N=1.80803 EG=1.05743
+XTI=5 BV=1000 IBV=5e-08 CJO=1e-11
+VJ=0.7 M=0.5 FC=0.5 TT=1e-07
+KF=0 AF=1
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