QUESTION BANK

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

YEAR/SEM

: III/VI

NAME OF THE SUBJECT

: MEDICAL ELECTRONICS

NAME OF THE FACULTY: Mr. T SENTHIL KUMAR

UNIT -I
SINGLE STAGE AMPLIFIERS
(X)** Common source stage, Source follower, Common gate stage, Cascode stage.
(Y)** Single ended and differential operation, Basic differential pair, Differential pair
with MOS loads

PART A
Define a)Resting Potential

b) Action Potential May/June 2009, Nov/Dec 2008

Define Conduction VelocityApr/May 2008, Nov/Dec 2008, May/June 2007

Write down the Nernst equation of action potential.
What is meant by sodium pump?
State all or none law in respect of cell bio potential. Apr/May 2008
List the types of bioelectric potentials.
Define electrode and list its types.
What are perfectly polarized and perfectly non polarized electrodes?
What are the types of electrodes used in bipolar measurement? May/June- 2012
Name the electrodes used for recording EMG and ECG.
11. State the importance of biological amplifiers.

Nov/Dec-2012

Apr/May 2010

What are the requirements for bio-amplifiers?

What are the basic components of biomedical systems?
List the lead systems used in ECG recording.

Apr/May 2010

What is evoked potential?

What is PCG?
Compare the signal characteristics of ECG and PCG.

Nov/Dec-2011

State the importance of PCG signals. May/June 2009

Define latency as related to EMG.

Nov/Dec 2008

Draw typical ECG waveform.Nov/Dec 2009, May/June 2007

What are the important bands of frequencies in EEG and state their importance
What are the peak amplitude and frequency response for ECG, EEG and EMG.

PART - B
1. (i) For a CS amplifier, derive the expression for transfer function from the small signal
equivalent circuit. (6) (May/June 2014)
(ii) Analyse the operation of a differential amplifier with active load. What is the effect of
parameter mismatch on the gain of differential amplifier? (10) (May/June 2014)
2. (i) Draw the circuit of a CG amplifier with active load and determine expressions for
input resistance, output resistance and voltage gain.(8) (May/June 2014)
(ii) For the amplifier discussed above,W/L=100m/1.6m for all transistors,=kn=90A/V2,
IRef=100A,VAN=8L(m)volts, VAP=12L(m) volts. Body effect factor X=015. Determine
r01, r02, Av and Ri. (May/June 2014)
3. (i) Explain in differential pair with MOS loads in detail. (8) (May/June 2015)
(ii) Write short notes on common gate stage. (8) (May/June 2015)
4. (i) Write short note on single ended and differential signals. (8) (May/June 2015)
(ii) Derive the voltage gain of CG with active load. Plot the output current characteristics
with respect to input differential voltage. Also derive the expression for driver current as
a function ofd the differential voltage. (8) (May/June 2015)

5. aa

UNIT - II
FREQUENCY RESPONSE AND NOISE ANALYSIS
(X)** Miller effect, Association of poles with nodes, frequency response of common
source stage, Source followers, Common gate stage, Cascode stage.
(Y)** Differential pair, Statistical characteristics of noise, noise in single stage amplifiers,
noise in differential amplifiers.

PART A
1. What is the effect of high frequency supply noise in differential amplifier? (May/June
2014)
2. Compare frequency response characteristics of CS, CD and CG amplifiers. (May/June
2014)
3. What is Miller Effect? (May/June 2015)
4. List the statistical characteristics of noise. (May/June 2015)

PART - B
1. (i)Calculate the transfer function for the circuit shown in fig 1. (6) (May/June 2014)

(ii) For an nMOS differential amplifier with pMOS toad, assuming all devices operate in
saturation and circuit is symmetric, calculate input referred noise voltage. (10) (May/June
2014)
2. (i) Explain with schematic and expressions, how the input referred noise voltage in CS
stage is reduced if transistor functions as a current source. (10) (May/June 2014)
(ii) Define the various noise source associated with differential amplifier and give the
expression for thermal noise in particular in MOSFET device. (6) (May/June 2014)
3. (i) Find the maximum noise voltage that a single MOSFET can generate. (4) (May/June
2015)
(ii) Draw a high frequency model of differential pair with active current mirror and derive
its CMRR. (12) (May/June 2015)
4. (i) Write short notes on noise in single stage amplifiers. (8) (May/June 2015)
(ii) Draw a high frequency model of a cascode stage and explain in detail. (8) (May/June
2015)
5. aa

UNIT - III
OPERATIONAL AMPLIFIERS
(X)** Concept of negative feedback, Effect of loading in feedback networks, operational
amplifier performance parameters.
(Y)** One-stage Op Amps, Two-stage Op Amps, Input range limitations, Gain boosting,
slew rate, power supply rejection, noise in Op Amps.
PART A
1. Define gain boosting. (May/June 2014)
2. What are the types of noises encountered in Op Amps? (May/June 2014)
3. List some applications of feedback. (May/June 2015)
4. List some op amp design parameters. (May/June 2015)

PART - B
1. (i) Explain the effect of loading in current-voltage feedback network using z-model. (10)
(May/June 2014)
(ii) List the various factors that limit the slew rate of opamps and discuss any one method
for improving the same. (6) (May/June 2014)
2. (i) Calculate input common mode voltage range and closed loop output impedance for
cascode op amp. (6) (May/June 2014)
(ii) Compare telescopic and folded-cascode topologies of single stage opamp and discuss
the effect of gain boosting in cascode devices. (10) (May/June 2014)
3. (i) Explain PSRR with an example circuit.(8) (May/June 2015)
(ii) Write short notes on gain boosting. (8) (May/June 2015)
4. (i) Draw and explain implementation of a two stage op amp and write the expression of
AV. (6) (May/June 2015)
(ii) Draw voltage current feedback amplifier. Draw the basic amplifier without feedback
and derive open loop transfer gain and form this find the closed loop transfer gain. (10)
(May/June 2015)
5. aa

UNIT - IV
STABILITY AND FREQUENCY COMPENSATION
(X)** General
Compensation.

considerations,

Multipole

systems,

Phase

Margin,

Frequency

(Y)** Compensation of two stage Op Amps, Slewing in two stage Op Amps, and Other
compensation techniques.

PART A
1. State the importance of phase margin in Op Amp design. (May/June 2014)
2. Mention any one method for improving slew rate. (May/June 2014)

3. Write the T(s) of a multiple system. (May/June 2015)

4. An amplifier with a forward gain of Ae and two poles at 10 MHZ and 500 MHZ is placed
in a unity gain feedback loop. Calculate Ae for a phase margin of 60o. (May/June 2015)

PART - B
1. (i) Explain the need for frequency compensation in operational amplifiers. (4)
(May/June2014)
(ii) For a telescopic operational amplifier with single-ended output, identify the number
of poles and discuss the effect of device capacitance on the internal nodes. (12)
(May/June2014)
2. What are the difficulties in compensating two-stage CMOS Op Amps? Discuss the
compensation technique using common gate stage. (16) (May/June2014)
3. Explain compensation methods of two-stage op amps in detail. (16) (May/June 2015)
4. Construct the root locus for a two poles system. (16) (May/June 2015)

UNIT - V
BIASING CIRCUITS
(X)** Basic current mirrors, cascode current mirrors, active current mirrors, voltage
references.
(Y)** Supply independent biasing, temperature independent references, PTAT current
generation, Constant- Gm Biasing.

PART A
1. What is the effect of channel length modulation on the current mirror ratio? (May/June
2014)
2. State principle of PTAT current generation. (May/June 2014)

3. How current mirrors are rationed? (May/June 2015)

4. What is voltage reference? (May/June 2015)

PART - B
1. (i) Explain with schematic and relevant expressions of constant gm, biasing.
(May/June2014)
(ii) Discuss the characteristics features of BandGap Reference Circuit. Show how it
yields temperature independent biasing. (May/June2014)
2. (i) For the source degenerated current mirror calculate output resistance and minimum
voltage required to keep device in saturation. nCoxW/L = 110 A/V2 and =0.01V-1,
Vth=0.83V. Also draw the small signal equivalent circuit. (9) (May/June2014)
(ii) Design DC Current sources with current value of 10A and 20A and DC current
sinks with current values of 10A and 40A. VDS sat for both current sinks and sources
must be less than 0.5V. You are given one reference current source of 10A. V TN=1V,
VTP= -1V, NCox=50A/V2, pCox=25A/V2, n = p = 0.1V-1 at L=1m. (7)
(May/June2014)
3. (i) Draw a cascode current source and with its equivalent circuit derive for its output
resistance. (10) (May/June 2015)
(ii) Explain PTAT voltage reference with circuit. (6) (May/June 2015)
4. (i) Write a short note on supply independent biasing. (8) (May/June 2015)
(ii) Explain constant Gm biasing. (8) (May/June 2015)
5.