CASE STUDY

ASSEMBLERS FOR X85 and X86

INTRODUCTION TO ASSEMBLERS

An assembler translates a file of assembly language statements into a file of binary

machine instructions and binary data. The translation process has two major parts. The
first step is to find memory locations with labels so the relationship between symbolic
names and addresses is known when instructions are translated. The second step is to
translate each assembly statement by combining the numeric equivalents of opcodes,
register specifiers, and labels into a legal instruction. As shown, the assembler produces
an output file, called an object file, which contains the machine instructions, data, and
bookkeeping information.

An object file typically cannot be executed because it references procedures or data in

other files. A label is external (also called global) if the labeled object can be referenced
from files other than the one in which it is defined. A label is local if the object can be
used only within the file in which it is defined. In most assemblers, labels are local by
default and must be explicitly declared global. Subroutines and global variables require
external labels since they are referenced from many files in a program. Local labels hide
names that should not be visible to other modules—for example, static functions in C,
which can only be called by other functions in the same file. In addition, compiler-
generated names—for example, a name for the instruction at the beginning of a loop—
are local so the compiler need not produce unique names in every file. Since the
assembler processes each file in a program individually and in isolation, it only knows
the addresses of local labels. The assembler depends on another tool, the linker, to
combine a collection of object files and libraries into an executable file by resolving
external labels. The assembler assists the linker by providing lists of labels and
unresolved references. However, even local labels present an interesting challenge to an
assembler. Unlike names in most high-level languages, assembly labels may be used
before they are defined.

If an assembler’s speed is important, this two-step process can be done in one pass over
the assembly file with a technique known as backpatching. In its pass over the file, the
assembler builds a (possibly incomplete) binary representation of every instruction. If the
instruction references a label that has not yet been defined, the assembler records the
label and instruction in a table. When a label is defined, the assembler consults this table
to find all instructions that contain a forward reference to the label. The assembler goes
back and corrects their binary representation to incorporate the address of the label.
Backpatching speeds assembly because the assembler only reads its input once.
However, it requires an assembler to hold the entire binary representation of a program in
memory so instructions can be backpatched. This requirement can limit the size of
programs that can be assembled. The process is complicated by machines with several
types of branches that span different ranges of instructions. When the assembler first sees
an unresolved label in a branch instruction, it must either use the largest possible branch
or risk having to go back and readjust many instructions to make room for a larger
branch.

ASSEMBLY LANGUAGE

Assembly language is a programming language. Its principal difference from high-level

languages such as BASIC, Java, and C is that assembly language provides only a few,
simple types of data and control flow. Assembly language programs do not specify the
type of value held in a variable. Instead, a programmer must apply the appropriate
operations (e.g., integer or floating-point addition) to a value. In addition, in assembly
language, programs must implement all control flow with gotos. Both factors make
assembly language programming for any machine—MIPS or 80x86— more difficult and
error-prone than writing in a high-level language.
DIFFERENCE BETWEEN RISC AND CISC

RISC
Means Reduced Instruction Set Computer. A
RISC system has reduced number of
instructions and more importantly it is load
store architecture where pipelining can be
implemented easily. Ex-ATMEL AVR
CISC
Means Complex instruction set architecture.
A CISC system has complex instructions
such as direct addition between data in two
memory locations. Ex-8085

Uniform instruction format, using a single Complex instruction, more addressing

word with the opcode in the same bit mode.
positions in every instruction, demanding
less decoding.

RISC architecture is not widely used. CISC architecture is widely used At least
75% of the processor use CISC architecture.

RISC puts a greater burden on the software. CISC, software developers no need to write
Software developers need to write more lines more lines for the same tasks
for the same tasks

Mainly used for real time applications Mainly used for real time applications
Mainly used in normal PC’s, Workstations
and servers

RISC processor has a number of hardwired CISC processor executes microcode

instructions instructions

This does not provides more code flexibility This provides more code flexibility but
but increases the overall speed efficiency reduces the overall speed efficiency
DIFFERENCE BETWEEN 8085 AND 8086 ARCHITECTURE

8085 8086
The Intel 8085 is an 8 bit microprocessor The Intel 8086 is a 16 bit microprocessor
created in 1977. created in 1978.

8085 is a 8 bit processor, number of flags 8086 is a 16 bit processor, number of flags
are 5 and memory capacity is 64KB are 9 and memory capacity is 1 MB.

8085 is based on Von-Neumann
architecture in which the data and
instructions are in the same memory space
without any distinction between them.8085
is CISC (Complex Instruction Set
Computer.8085 is a 8 bit processor i.e 8 bit
data bus. Has got 16Address Lines.
Maximum Operating speed is 3MHz. 8085-
AOperates upto a maximum of 5MHz.
The 8086 was the first chip to start the X86
architecture family. 8086 is a 16 bit
processor. Has got 20 address lines.
Operates upto 5MHz8085 consists 74
instructions.8086 consists 117 instructions
in 8086 four 16 bit registers are available
and pin no 33- min/(~max) it selects
minimum mode when this pin is high
otherwise it selects maximum mode.
8085 μp

 It is manufactured with N-MOS technology.

 It has 16-bit address bus and hence can address up to 216 = 65536 bytes
(64KB) memory locations through A0-A15.
 The first 8 lines of address bus and 8 lines of data bus are multiplexed AD 0 –
AD7.
 Data bus is a group of 8 lines D0 – D7.
 It supports external interrupt request.
 A 16 bit stack pointer (SP).
 A 16 bit program counter (PC).
 Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
 It requires a signal +5V power supply and operates at 3.2 MHZ single phase
clock.
 It is enclosed with 40 pins DIP (Dual in line package).
 8086 μp

 8086 has a 20 bit address bus can access up to 220 memory locations (1 MB).
 It can support up to 64K I/O ports.
 It provides 14, 16 -bit registers.
 It has multiplexed address and data bus AD0- AD15 and A16 – A19.
 It requires single phase clock with 33% duty cycle to provide internal timing.
 8086 is designed to operate in two modes, Minimum and Maximum.
 It can prefetches upto 6 instruction bytes from memory and queues them in order to
speed up instruction execution.
 It requires +5V power supply.
 A 40 pin dual in line package.

Minimum and Maximum Modes:

 The minimum mode is selected by applying logic 1 to the MN / MX input pin. This is a
single microprocessor configuration.
 The maximum mode is selected by applying logic 0 to the MN / MXinput pin. This is a
multi micro processors configuration.
 8085 Instruction Set

Data Transfer Group:

MOV Move

MVI Move Immediate

LDA Load Accumulator Directly from Memory

STA Store Accumulator Directly in Memory

LHLD Load H & L Registers Directly from Memory

SHLD Store H & L Registers Directly in Memory

LXI Load Register Pair with Immediate data

LDAX Load Accumulator from Address in Register Pair

STAX Store Accumulator in Address in Register Pair

XCHG Exchange H & L with D & E

XTHL Exchange Top of Stack with H & L

Arithmetic Group:

ADD Add to Accumulator

ADI Add Immediate Data to Accumulator

ADC Add to Accumulator Using Carry Flag

ACI Add Immediate data to Accumulator Using Carry

SUB Subtract from Accumulator

SUI Subtract Immediate Data from Accumulator

SBB Subtract from Accumulator Using Borrow (Carry) Flag

SBI Subtract Immediate from Accumulator Using Borrow (Carry) Flag

INR Increment Specified Byte by One

DCR Decrement Specified Byte by One

INX Increment Register Pair by One

DCX Decrement Register Pair by One

DAD Double Register Add; Add Content of Register

Pair to H & L Register Pair

Logical Group:

ANA Logical AND with Accumulator

ANI Logical AND with Accumulator Using Immediate Data

ORA Logical OR with Accumulator

OR Logical OR with Accumulator Using Immediate Data

XRA Exclusive Logical OR with Accumulator

XRI Exclusive OR Using Immediate Data

CMP Compare

CPI Compare Using Immediate Data

RLC Rotate Accumulator Left

RRC Rotate Accumulator Right

RAL Rotate Left through Carry

RAR Rotate Right through Carry

CMA Complement Accumulator

CMC Complement Carry Flag

STC Set Carry Flag

Branch Group:

Jump unconditionally

JMP Jump

Jump conditionally

JC Jump on Carry CY = 1

JNC Jump on no Carry CY = 0

JP Jump on positive S = 0

JM Jump on minus S = 1

JZ Jump on zero Z = 1

JNZ Jump on no zero Z = 0

JPE Jump on parity even P = 1

JPO Jump on parity odd P = 0

Call unconditionally

CALL Call

Call conditionally

CC Call on Carry CY = 1

CNC Call on no Carry CY = 0

CP Call on positive S = 0

CM Call on minus S = 1

CZ Call on zero Z = 1

CNZ Call on no zero Z = 0

CPE Call on parity even P = 1

CPO Call on parity odd P = 0

Return conditionally

RET Return

Return unconditionally

RC Return on Carry CY = 1

RNC Return on no Carry CY = 0

RP Return on positive S = 0

RM Return on minus S = 1

RZ Return on zero Z = 1

RNZ Return on no zero Z = 0

RPE Return on parity even P = 1

RPO Return on parity odd P = 0

PCHL Move H & L to Program Counter

RST Special Restart Instruction Used with Interrupts

Stack I/O, and Machine Control Instructions:

PUSH Push Two bytes of Data onto the Stack

POP Pop Two Bytes of Data off the Stack

XTHL Exchange Top of Stack with H & L

SPHL Move content of H & L to Stack Pointer

The I/0 instructions are as follows:

IN Initiate Input Operation

OUT Initiate Output Operation

The Machine Control instructions are as follows:

EI Enable Interrupt System

DI Disable Interrupt System

HLT Halt

NOP No Operation
 8086 Instruction Set
Data Transfer Instructions
MOV -Move byte or word to register or memory
IN, OUT -Input byte or word from port, output word to port
LEA Load effective address
LDS, LES Load pointer using data segment, extra segment
PUSH, POP Push word onto stack, pop word off stack
XCHG Exchange byte or word
XLAT Translate byte using look-up table

Logical Instructions
NOT Logical NOT of byte or word (one's complement)
AND Logical AND of byte or word
OR Logical OR of byte or word
XOR Logical exclusive-OR of byte or word
TEST Test byte or word (AND without storing)

Shift and Rotate Instructions

SHL, SHR Logical shift left, right byte or word by 1 or CL
SAL, SAR Arithmetic shift left, right byte or word by 1 or CL
ROL, ROR Rotate left, right byte or word by 1 or CL
RCL, RCR Rotate left, right through carry byte or word by 1 or CL

Arithmetic Instructions
ADD, SUB Add, subtract byte or word
ADC, SBB Add, subtract byte or word and carry (borrow)
INC, DEC Increment, decrement byte or word
NEG Negate byte or word (two's complement)
CMP Compare byte or word (subtract without storing)
MUL, DIV Multiply, divide byte or word (unsigned)
IMUL, IDIV Integer multiply, divide byte or word (signed)
CBW, CWD Convert byte to word, word to double word (useful before multiply/divide)
DAA, DAS Decimal adjust for addition, subtraction (binary coded decimal numbers)

Transfer Instructions
JMP Unconditional jump
Conditional jumps:
JA (JNBE) Jump if above (not below or equal), +127, -128 range only
JAE (JNB) Jump if above or equal (not below), +127, -128 range only
JB (JNAE) Jump if below (not above or equal), +127, -128 range only
JBE (JNA) Jump if below or equal (not above), +127, -128 range only
JE (JZ) Jump if equal (zero), +127, -128 range only
JG (JNLE) Jump if greater (not less or equal), +127, -128 range only
JGE (JNL) Jump if greater or equal (not less), +127, -128 range only
JL (JNGE) Jump if less (not greater nor equal), +127, -128 range only
JLE (JNG) Jump if less or equal (not greater), +127, -128 range only
JC, JNC Jump if carry set, carry not set, +127, -128 range only
JO, JNO Jump if overflow, no overflow, +127, -128 range only
JS, JNS Jump if sign, no sign, +127, -128 range only
JNP (JPO) Jump if no parity (parity odd), +127, -128 range only
JP (JPE) Jump if parity (parity even), +127, -128 range only

Loop control:
LOOP Loop unconditional, count in CX, short jump to target address
LOOPE (LOOPZ) Loop if equal (zero), count in CX, short jump to target address
LOOPNE (LOOPNZ) Loop if not equal (not zero), count in CX, short jump to target
address
JCXZ Jump if CX equals zero (used to skip code in loop)

Subroutine and Interrupt Instructions

CALL, RET Call, return from procedure (inside or outside current segment)
INT, INTO Software interrupt, interrupt if overflow
IRET Return from interrupt

String Instructions
MOVS Move byte or word string
MOVSB, MOVSW Move byte, word string
CMPS Compare byte or word string
SCAS Scan byte or word string (comparing to A or AX)
LODS, STOS Load, store byte or word string to AL or AX
Repeat instructions (placed in front of other string operations):
REP Repeat
REPE, REPZ Repeat while equal, zero
REPNE, REPNZ Repeat while not equal (zero)

Processor Control Instructions

Flag manipulation:
STC, CLC, and CMC Set, clear, complement carry flag
STD, CLD Set, clear direction flag
STI, CLI Set, clear interrupts enable flag
LAHF, SAHF Load AH from flags, store AH into flags
PUSHF, POPF Push flags onto stack, pop flags off stack
Coprocessor, multiprocessor interface:
ESC Escape to external processor interface
LOCK Lock bus during next instruction
Inactive states:
NOP No operation
WAIT Wait for TEST pin activity
HLT Halt processor