Ain Shams Engineering Journal (2015) xxx, xxxxxx

Ain Shams University

Ain Shams Engineering Journal

www.elsevier.com/locate/asej
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ELECTRICAL ENGINEERING

Analytical modeling of threshold voltage for

Cylindrical Gate All Around (CGAA) MOSFET
using center potential
K.P. Pradhan *, M.R. Kumar, S.K. Mohapatra, P.K. Sahu
Department of Electrical Engineering, National Institute of Technology (NIT), Rourkela, 769008 Odisha, India
Received 23 October 2014; revised 20 March 2015; accepted 19 April 2015

KEYWORDS
Cylindrical Gate All Around
(CGAA) MOSFET;
Surface potential;
Center potential;
Threshold voltage;
Short channel effects (SCEs)

Abstract In this paper, an analytical threshold voltage model is proposed for a cylindrical gate-allaround (CGAA) MOSFET by solving the 2-D Poissons equation in the cylindrical coordinate system. A comparison is made for both the center and the surface potential model of CGAA
MOSFET. This paper claims that the calculation of threshold voltage using center potential is more
accurate rather than the calculation from surface potential. The effects of the device parameters like
the drain bias VDS , oxide thickness tox , channel thickness (r), etc., on the threshold voltage are
also studied in this paper. The model is veried with 3D numerical device simulator Sentaurus from
Synopsys Inc.
2015 Faculty of Engineering, Ain Shams University. Production and hosting by Elsevier B.V. This is an
open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

1. Introduction
The semiconductor technology particularly CMOS has
encountered its limitations due to aggressive scaling of the
device feature size to improve circuit performance in the subwavelength lithography regime. Many new devices have been
introduced in more than-Moore era [13]. The multiple gate
Metal Oxide Semiconductor Field Effect Transistor
* Corresponding author. Tel.: +91 9438321109.
E-mail addresses: kp2.etc@gmail.com (K.P. Pradhan), madhu.
raj3456@gmail.com (M.R. Kumar), skmctc74@gmail.com (S.K.
Mohapatra), pksahu@nitrkl.ac.in (P.K. Sahu).
Peer review under responsibility of Ain Shams University.

Production and hosting by Elsevier

(MuGFETs) have been proposed for promising solution as

well as a strong candidate for nanoscale technology CMOS
devices because of its excellent immunity toward short channel
effects (SCEs), low leakage current, high driving controllability
and high output resistance. The two main manifestations of
SCE are Drain Induced Barrier Lowering (DIBL) and the
threshold voltage roll off, which consequently increases the
off state current and further the onoff current ratio will be
degraded. In coming future, MuGFETs are emerging devices
for replacing conventional single gate MOSFETs [46]. The
electrostatic control of channel by gate increases in case of
MuGFETs which dramatically reduces SCEs and also the
lightly doped channel helps to alleviate the mobility degradation problem [2].
The Cylindrical Gate All Around (CGAA) MOSFET is
considered one of the most promising device structures for further scaling down of CMOS technology. In this architecture,
the channel is completely surrounded by the gate so that the

http://dx.doi.org/10.1016/j.asej.2015.04.009
2090-4479 2015 Faculty of Engineering, Ain Shams University. Production and hosting by Elsevier B.V.
This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).
Please cite this article in press as: Pradhan KP et al., Analytical modeling of threshold voltage for Cylindrical Gate All Around (CGAA) MOSFET using center potential, Ain Shams Eng J (2015), http://dx.doi.org/10.1016/j.asej.2015.04.009

2
gate has more control over the channel which further minimizes the SCEs [7,8]. The downscaling of CMOS technology
is the primary factor for the improvement in IC performance
and cost, which contributes to a rapid growth in semiconductor industry. Because of the shorter dimension and higher
drive current, CGAA MOSFETs can achieve higher packing
density as compared to double gate (DG) MOSFETs [8,9].
So, the CGAA MOSFET has excellent electrostatic control
of the channel, robustness against SCEs, better scaling options,
no oating body effect, larger Equivalent Number of Gate,
ideal subthreshold swing, suppress corner effects, nonconnement of carriers near to Si/SiO2 interface, reduced natural length as compared to other MuGFETs and gives volume
inversion [2,7,10,11].
In this paper, it has been observed that solving the center
potential in the channel may produce more accurate results as
compared to surface potential [12]. To solve the Poissons equation, an assumption is made as the potential inside the channel
has parabolic nature [13]. Again the threshold voltage expression of CGAA MOSFET is derived by using the center potential model. The model results are veried with commercially
available device simulator Sentaurus TCAD from Synopsis.
The whole manuscript is organized as follows. Along with
the introduction, Section 2 describes the device structure
description that includes all the dimensions, materials and
doping concentrations of CGAA-MOSFET. This section also
analyzes the physics of the device using numerical simulations
and models activated for simulation. Section 3 comprises of
two subsections that includes the formulation of center potential and modeling of threshold voltage. The impact of numerous device parameters on the center potential as well as on the
threshold voltage of the CGAA MOSFET is discussed in
Section 4. Finally, the concluding remarks in Section 5 substantiates the novelty of the paper.
2. Device structure and simulation setup
The schematic diagram of the fully depleted Cylindrical Gate All
Around (CGAA) MOSFET structure used for modeling and
simulation is shown in Fig. 1. The radial and lateral directions
are assumed to be along the radius and the z-axis of the cylinder
as shown in Fig. 1. The device has uniformly doped source
drain with doping concentration of ND 1  1020 cm3. The
channel is kept lightly doped with doping concentration of
NA 1  1016 cm3. The gate oxide thickness and the diameter
of the silicon pillar are tox 2 nm and 2 * r = 10 nm,
respectively.

K.P. Pradhan et al.

The work function of the gate material is: /M 4:6 eV
(e.g., Au). The Table 1 shows the list of parameters used in
the simulation. The simulation is carried out by the device simulator Sentaurus, a 3-D numerical simulator from Synopsis
Inc. [14]. To study the center potential along the channel we
have taken the cutline at the middle of the channel thickness
across the z-axis of the device. In Figs. 36 the lateral position
15 nm in z-axis indicates the center of the channel of the structure. To obtain accurate results for MOSFET simulation we
need to account for the mobility degradation that occurs inside
inversion layers. The driftdiffusion model which is the default
carrier transport model in Sentaurus Device is activated. For
the driftdiffusion model, the current densities for electrons
and holes are given by the following:
!

J n ln nrEC  1:5nkTr ln mn Dn rn  nr ln cn
~
Jp lp prEV 1:5pkTr ln mp  Dp rp  pr ln cp

where J~n , and J~p are electron and hole current density. ln , and
lp represent electron and hole mobility. n, and p describe electron and hole density. cn ; cp are Fermi statistic constants, and
mn ; mp present spatial effective masses of electron and hole
respectively. T and k describe temperature and Boltzmann
constant. EC , and EV are conduction and valance energy
bands. Dn , and Dp represent the diffusion constants for electron and holes respectively. The rst term takes into account
the contribution due to the spatial variations of the electrostatic potential, the electron afnity, and the band gap
[15,16]. The remaining terms take into account the contribution due to the gradient of concentration, and the spatial variation of the effective masses mn and mp . All other terms used
are usual meaning. In the simulation basic mobility model is
used, that takes into account the effect of doping dependence,
high-eld saturation (velocity saturation), and transverse eld
dependence. The inversion layer mobility models Lombardi
(constant voltage and temperature, CVT), along with Shockl
eyReadHall (SRH) and Auger recombination models are
included. The impact ionization effects are ignored in our simulation. The silicon band gap narrowing model that determines
the intrinsic carrier concentration is also activated. The solution of the device equations are done self-consistently, on the

Table 1

Parameter used for the simulation.

Parameter
symbol

Technology parameter

Value

Na

1016 cm3

R
tSi
tox
L
e0

Impurity doping concentration in the

channel
Impurity doping concentration in the
source and drain
Channel radius
Silicon lm thickness = 2r
Oxide thickness
Channel length
Permittivity of vacuum

eSi
eox
k

Permittivity of silicon
Permittivity of oxide
Boltzmann constant

Absolute temperature in kelvin

Nd

Fig. 1 Schematic Structure of Cylindrical Gate All Around

(CGAA) MOSFET.

1020 cm3
5 nm
10 nm
2 nm
30 nm
8:8 1012 F/
m
11:85 e0
3:9 e0
1:38 1023 J/
K
300 K

Please cite this article in press as: Pradhan KP et al., Analytical modeling of threshold voltage for Cylindrical Gate All Around (CGAA) MOSFET using center potential, Ain Shams Eng J (2015), http://dx.doi.org/10.1016/j.asej.2015.04.009

Analytical modeling of threshold voltage for Cylindrical Gate All Around (CGAA) MOSFET
3


@
eox Vgs  Vfb  /r; z
discrete mesh, in an iterative fashion. For each iteration, an
/r; z

11
error is calculated and device attempts to converge on a solu@
t;ox
esi
rtsi =2
tion that has an acceptably small error. The Poisson equation,


continuity equations, and the different thermal and energy
where t;ox t2Si ln 1 2ttsiox , Vgs is gate to source voltage eox and
equations are included in simulation [14]. All the structure
esi are the permittivity of SiO2 and Si respectively and Vfb is the
junctions are assumed as abrupt, and the biasing conditions
at band voltage which is given as below:
are considered at room temperature in the simulation.
Vfb /M  /S
12
 
vSi Eg;Si kT
Na
3. Analytical modeling
13

ln
/S
q
q
2q
ni
3.1. Center potential formulation
By differentiating the Eq. (4) with respect to r and equating it
with Eq. (10), one can get
The potential distribution /r; z in the channel region has
c1 z 0
14
been obtained by solving the following 2-D Poissons equation
in cylindrical coordinate system. The 2-dimensional cross secFurther putting Eq. (14) in Eq. (4), we can get as
tional view of the structure is shown in Fig. 2.
/r; z c0 z c2 zr2
15


1@
@
@2
q  Na
r /r; z 2 /r; z
3
Then by solving Eq. (15) using the given boundary conditions,
r @ @r
@z
esi
the value of c2 z can be calculated.
 
1
The potential distributions inside the channel region are
2esi t;ox
approximated by a parabolic polynomial as:
c2 z Vgs  Vfb  c0 z t2si 1
16
eox tsi
/r; z c0 z c1 zr c2 zr2
4
From Eq. (9), we can express the center potential as:
The coefcients c0 ; c1 and c2 are the functions of z- only, and
/r; z /c z c2 zr2
17
can be determined by using the given boundary conditions.
The center potential can be calculated by calculating the
/0; 0 Vbi
5
potential at r 0
/0; L Vbi Vds
6





1@
@
@2
qNa
r /r; z  2 /r; z
18
where Vds is the drain to source voltage and Vbi is the built-in
r @ @r
@z
esi
r0
r0
potential between the source/drain and Si channel junction and
is given by
So, nally by solving the Eq. (18) at r 0 with the help of


above said boundary conditions and other expressions, one
KT
Na Nd
7
Vbi
ln
can get the center potential as given below:
n2i
q
r !
r !
4
4
From the Eq. (2), if we consider r 0 then that will become
/c z A exp
z B exp  z
k
k
our center potential as given below:


kqNa
/r; zjr0 c0 z
8
Vgs  Vfb 
19
4esi
/0; z /c z c0 z
9
where
where c0 z will be the center potential and is a function of z

only. The electric eld at the center of the lm is zero
2esi t;ox
2
20
k tsi 1

eox tsi

@
/r; z 0
10
2
3
@r


 q 
r0
kqNa
4
V
1

exp


V
z
bi  Vgs  Vfb  4esi
ds
k
6
7
The electric eld at the silicon oxide interface is given by
A4
q 
 q 
5
4
4
exp

exp

L
L
k
k
21
2


q 
kqNa
4
z Vds 7
k
6Vbi  Vgs  Vfb  4esi 1  exp
q
B 4
q 
5
4
exp
L  exp 4kL
k
22
3.2. Threshold voltage formulation
Fig. 2 A 2-dimensional cross-sectional view of the structure of
Cylindrical Gate All Around (CGAA) MOSFET.

By utilizing (5)(9), the potential at the body center /c z and

at the surface /s z can be related as below

Please cite this article in press as: Pradhan KP et al., Analytical modeling of threshold voltage for Cylindrical Gate All Around (CGAA) MOSFET using center potential, Ain Shams Eng J (2015), http://dx.doi.org/10.1016/j.asej.2015.04.009

K.P. Pradhan et al.

/s z /c z Vgs  Vfb  /c z

t2si
k

23

The position zmin of the minimum center potential can be calculated by differentiating the center potential and equating it
to zero as given below.


d
d
t2 d
/s z
/c z  si /c z 0
24
dz
dz
k dz
zzmin
d
/ z 0
dz c

25

By solving the above equation with the help of boundary condition, we can get the zmin point as
r  
k
B
26
ln
zmin
16
A
Putting the zmin value in Eq. (23), the minimum surface potential can be calculated as (27)



p kqNa
t2si
/s min Vgs  Vfb 2 AB 
1
27
4esi
k
The threshold voltage of the CGAA device can be found as
follows [17]:
us min jVgs Vth /s min th 2/F

28

Na
/F KT ln
ni

29

where /F is the difference between the Fermi potential and the

intrinsic Fermi level in the bulk region, /s min th is the value of
surface potential at which the volumetric inversion electron
charge density in the Si device is equal to the body doping.
By solving (27) and (28), one can calculate the threshold voltage as given below:


kqNa
t2
Vth Vfb /s min th
1  Si
4eSi
k


p
t2Si
30
 2 AB 1 
k

p
t2
If channel length (L) is very large then 2 AB 1  kSi becomes
negligible, so that we can re-write Eq. (30) as:



kqNa
t2
VthL /s min th Vfb
1  si
4esi
k

3
 q 
4
1

exp

L
k
7
6
q 
 q 5
N2 4
4
4
exp
L  exp  kL
k
2

31

3

q 
kqNa
4
V
1

exp

V
L
bi Vfb 4esi
ds
k
6
7
N3 4
q 
 q 
5
4
4

exp

exp
L
L
k
k

36

2

37

3
q 
4
L
1

exp
k
6
7
N4 4
q 
 q 5
4
4
L  exp  kL
exp
k

38



t2
N5 4 1  si
k

39

4. Results and discussion

In this section, results obtained from theoretical models of the
center potential are compared with the numerical simulation
results. The center potential, /0; z, and the surface potential,


/ t2Si ; z for the CGAA MOSFET are compared in Fig. 3. The
center potential curve lies above the surface potential along
with their minimum potential points.
It can be noted that source channel barrier height at channel center is lower than that of the surface and hence the
threshold voltage should be calculated by using the center
potential minima.
Fig. 4 shows the variation of the center potential along the
channel for three different radius/thin lm thicknesses of GAA
MOSFET. When the thin lm thickness is reduced, the controllability of the gate over the channel becomes stronger in
comparison with the inuence exerted by the source/drain.
Fig. 5 shows the variation of the center potential along the
channel for different oxide thicknesses. When the oxide thickness is reduced, the controllability of the gate over the channel
potential increases. Therefore, continuous scaling down of the
oxide thickness reduces SCEs. However, the oxide thickness
should not be scaled down to very small values so that, tunneling through the thin oxide and hot-carrier effects become
prominent.

Finally by putting A and B values in (30) and replacing VGS

with Vth , we get:
p
b b2  4ac
Vth
32
2a
Where a, b, and c are constants and given as below:
a 1  N2 N4 N5

33

b N1 N4 N5 N2 N3 N5  2VthL

34

c V2thL  N2 N4 N5
3

 q 
kqNa
4
V
1

exp


V
L
bi Vfb 4esi
ds
k
7
6
q 
 q 
N1 4
5
4
4

exp

L
L
exp
k
k
2

35

Fig. 3 Potential along the channel length at body center and at

the surface. Parameters used /M 4:6 eV, NA 1  1016 cm3,
VGS 0:1 V
and
r = 7.5 nm,
L = 30 nm,
tox 2 nm,
VDS 0:1 V.

Please cite this article in press as: Pradhan KP et al., Analytical modeling of threshold voltage for Cylindrical Gate All Around (CGAA) MOSFET using center potential, Ain Shams Eng J (2015), http://dx.doi.org/10.1016/j.asej.2015.04.009

Analytical modeling of threshold voltage for Cylindrical Gate All Around (CGAA) MOSFET

Fig. 4 Center potential along the channel length at various

silicon thicknesses (r). Parameters used /M 4:6 eV,
NA 1  1016 cm3, L = 30 nm, tox 2 nm, VGS 0:1 V and
VDS 0:1 V.

Fig. 5 Center potential along the channel length with various

oxide thicknesses tox . Parameters used /M 4:6 eV,
NA 1  1016 cm3, tSi 7:5 nm, L = 30 nm, VGS 0:1 V and
VDS 0:1 V.

Fig. 6 demonstrates the center potential curve along the

channel length at various values of the drain voltage. The presence of DIBL effect can be easily observed from Fig. 6 as the
center potential minima point shows an upward movement
with the increasing of drain voltage. The threshold voltage
depends on the drain bias, gate length, body and oxide thickness, oxide properties, gate work function, doping prole (uniform or non-uniform), etc. In this paper, only the gate length,
drain bias, body and oxide thickness are taken as parameters.
Fig. 7 demonstrate the variation of threshold voltage along
the channel length for different drain bias. From Fig. 7, it is
clear that the threshold voltage appears to be very sensitive
to the gate length. It is also evident that as the channel length
decreases, the drain capacitance increases which lowers the
barrier. So to turn on the transistor, a lower gate voltage is
needed to overcome the barrier height. As a result, with
decreasing channel length there is a decrease in the threshold

Fig. 6 Center potential along the channel length at various

Drain
Voltages.
Parameters
used
/M 4:6 eV,
NA 1  1016 cm3, tSi 7:5 nm, L = 30 nm, and VGS 0:1 V.

Fig. 7 Threshold voltage along the channel length at various

Drain
Voltages.
Parameters
used
/M 4:6 eV,
NA 1  1016 cm3, tSi 7:5 nm, L = 30 nm, and VGS 0:1 V.

voltage. From the same gure it also can be observed that as

drain bias increases, the barrier potential decreases which lowers the threshold voltage. Fig. 8 shows the variation of the
threshold voltage along the channel for different radius/Si thin
lm thicknesses. It can be seen that Vth also reduces as Si thin
lm thickness increases. This is because of the decrease in the
total depletion charge under the gate with increase in the Si
thin-lm thickness, leading to an early onset of inversion.
Thus, higher short channel effect immunity can be achieved
by reducing the body thickness of silicon-on-insulator (SOI).
Therefore, the ultra-thin body (UTB) MOSFET is considered
as one of the promising structures for future very large scale
integrated circuit (VLSI) applications [18].
Fig. 9 examines the variation of the threshold voltage along
the channel for different gate oxide thicknesses. The plot indicates that a larger gate oxide thickness will induce a greater
threshold voltage roll-off. The gate gradually loses control of

Fig. 8 Threshold voltage along the channel length at various

silicon
thicknesses.
Parameters
used
/M 4:6 eV,
NA 1  1016 cm3, L = 30 nm, tox 2 nm, VGS 0:1 V and
VDS 0:1 V.

Fig. 9 Threshold voltage along the channel length at various

oxide
thicknesses.
Parameters
used
/M 4:6 eV,
NA 1  1016 cm3, tSi 7:5 nm, L = 30 nm, VGS 0:1 V and
VDS 0:1 V.

Please cite this article in press as: Pradhan KP et al., Analytical modeling of threshold voltage for Cylindrical Gate All Around (CGAA) MOSFET using center potential, Ain Shams Eng J (2015), http://dx.doi.org/10.1016/j.asej.2015.04.009

6
the channel as the gate oxide thickness steadily increases. This
is because a larger oxide thickness will resist the vertical electric eld from the gate into the channel resulting in the degradation of threshold behavior. Therefore, to suppress the
threshold voltage roll-off, thin gate oxide is preferred. So, continuous scaling down of the oxide thickness gives rise to better
device performances but on the other hand, oxide thickness
cannot be scaled down to very small values because tunneling
through the thin oxide and hot-carrier effects become prominent. It is clear that there is a close match between the analytical results and the 3-D simulation results.
5. Conclusion
An analytical center potential model for the CGAA MOSFET
is derived using a parabolic approximation of the channel prole. The paper proposes that the threshold voltage calculation
using center potential is more accurate than to the previous
work wherein the threshold voltage is based on surface potential. An extensive analysis is carried out to nd the impact of
numerous device parameters on the center potential as well
as on the threshold voltage of the CGAA MOSFET. Also,
an appropriate selection of the oxide and the silicon thickness,
gives an optimum threshold voltage at a given channel length
and drain bias. The derived 2-D analytical model is well
matched with the simulation results obtained from
Sentaurus from Synopsys. The developed model may further
be useful to optimize the device parameters for a desired
performance.
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[11] Ferain I, Colinge CA, Colinge J. Multigate transistors as the
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analytical threshold voltage model for triple-material cylindrical
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[13] Chiang TK. A compact model for threshold voltage of surrounding-gate MOSFETs with localized interface trapped charges.
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[15] Tsividis Yannis, Operation and Modeling of the MOS Transistor,
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[17] Chiang TK. A new two-dimensional threshold voltage model for
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K.P. Pradhan completed M.Tech (Res) degree

in
Nanoelectronic
Devices,
Electrical
Engineering Department from National
Institute of Technology (NIT), Rourkela,
Odisha, India, in 2013, where he is currently
working towards the Ph.D degree in
Nanoelectronics and Nanotechnology. His
current research interests are in the area of
modeling and simulation of Silicon on
Insulator, Strained Silicon and Underlap
Multigate MOSFETs, FinFETs etc. He has
authored more than 30 research articles in referred journals and
international conferences. He is a student member of IEEE.
M.R. Kumar completed his M.Tech degree in
Electronic Systems and Communication,
Electrical Engineering Department, National
Institute of Technology (NIT), Rourkela,
Odisha, India in 2014.

S.K. Mohapatra received M.E. Degree in

Communication Control & Networking from
the Madhav Institute of Technology and
Science, Gwalior, M.P., India, in 2001. He
joined as an Asst. Professor in dept. of
Electronics & Telecommunication at Ajay
Binay Institute of Technology, Cuttack,
Odisha, India, from 2001. He is currently
working as a Ph.D research scholar in
department Electrical Engineering at National
Institute of Technology (NIT), Rourkela,
India. His research interests include modeling and simulation of
nanoscale semiconducting devices and its characterization for digital
and high frequency applications. He is a member of IEEE, and also a
life member of ISTE and IETE.

Please cite this article in press as: Pradhan KP et al., Analytical modeling of threshold voltage for Cylindrical Gate All Around (CGAA) MOSFET using center potential, Ain Shams Eng J (2015), http://dx.doi.org/10.1016/j.asej.2015.04.009

Analytical modeling of threshold voltage for Cylindrical Gate All Around (CGAA) MOSFET

P.K. Sahu received B.Sc Engineering

(El&TCE) and M.Sc Engineering (ESC) from
Sambalpur University, Odisha, India. Received
his Ph.D degree from Jadavpur University,
Kolkota, India, in the year 2008. Currently he is
Associate Professor in Department of
Electrical Engineering at National Institute of
Technology, Rourkela, Odisha, India. His
research interest includes Micro and Nano
Electronic Devices, VLSI, Communication
Systems. He is a member of IEEE, and also a
life member of IE and ISTE etc.

Please cite this article in press as: Pradhan KP et al., Analytical modeling of threshold voltage for Cylindrical Gate All Around (CGAA) MOSFET using center potential, Ain Shams Eng J (2015), http://dx.doi.org/10.1016/j.asej.2015.04.009