Professional Documents
Culture Documents
DEPARTMENT OF
PHYSICS AND MATERIALS SCIENCE
by
March 2007
by
March 2007
Project Supervisor :
Prof. S. T. Lee
A. Content
A. Content
B. List of graphs
III
C. List of figures
IV
D. Acknowledgment
E. Abstract
VI
1. Introduction
1.1 Silicon Nanowires
2-3
2. Literature Review
2.1. Various methods in the synthesis of silicon nanowires
2.1.1 Template-Directed Synthesis
5-6
6-7
7-9
3. Experimental Procedures
9-11
12
12
12
3.1.1.1 SEM
12
3.1.1.2 TEM
13
3.1.1.3 EDX
13
13
13
14
14
I
14
14
15
15
15
16
17-18
19-20
21
21
22-23
24-25
26-27
28-32
28-32
32-35
5. Conclusion
35
36-37
6. Future Work
37
7. List of Reference
38-41
II
B List of graphs:
Fig.2.1. Shadow sputtering against an array of V-grooves to form 1D nanomaterial
Fig.2.2 Vapor-phase deposition of 1D nanomaterials into V-grooves
Fig.2.3. Porous membrane used in the 1D structure synthesis
Fig.2.4 Nanomaterial synthesized by VLS mechanism
Fig.2.5 Phase diagram of Si-Au alloy
Fig.2.6 Schematic graph showing the Ag particle is pinned
Fig.2.7 Schematic graph showing the sinking track of Ag
Fig.2.8 Cross-section of SiNW synthesized
Fig.3.1. Electrode pattern on the wafer prepared by photolithography
Fig.3.2 Magnified electrode with marks
Fig.3.3. Schematic illustration of a two point probe station
Fig.3.4 The configuration of the SiNW device
Fig.3.5 Photolithography Technique
Fig.3.6 Experimental flow chart
Fig.4.1 SEM micrograph of SiNW synthesized by MNCCE
Fig.4.2 EDX pattern showing the composition of the SiNW
Fig.4.3 Band diagram for Schottky barrier
Fig.4.4 I-V curve of a Schottky barrier
Fig.4.5. Exchange electrode measurement of I-V
Fig.4.6 SEM of Sample A prepared by shadow mask
Fig.4.7.SEM of Sample B prepared by shadow mask
Fig.4.8 I-V characteristics of 3 samples prepared by shadow mask
Fig.4.9 Electrode pattern fabricated by photolithography without metal coating
Fig.4.10 Electrode pattern fabricated by photolithography with metal coating
Fig.4.11 SEM image of NW on electrode prepared by photolithography (Sp A)
Fig.4.12 SEM image of NW on electrode prepared by photolithography (Sp B)
Fig.4.13 Schematic illustration of contact area
Fig.4.14 I-V characteristics of the FET device
Fig.4.15 Explanation of linear region in the curve
III
C. List of Tables:
Table.4.1 Resistivity of SiNW measured from the photolithographic samples and
shadow mask samples
Table 4.2 Mobility obtained in the ambient condition and in SiO2 treated condition
IV
D. Acknowledgement
I would like to take this opportunity to express my gratitude and appreciation to my
supervisor, Professor S.T. Lee for his constant encouragement and support. The
enlightening discussion between Professor Lee and me has aroused great passion in
me to explore the beauty of science and technology.
I would also like to thank Dr.Jie for helping me get familiar with research
environment in the lab while demonstrating to me so many experiments that kept me
gravitated to the field of nanotechnology. The valuable advice he shared with me
inspired me a lot throughout the project.
I wish to thank all the Mphil students and PhD students in the Center of
Super-Diamond and Advanced Films for giving me so many help during the
experiment and sharing their research experience with me. Hereby, I would like to
thank Mr. Tang Hao, Mr. Chen Zhenhua, Mr Jack Chung and Mr. Ye Qing and etc.
particularly for their invaluable discussion with me on my project.
Also, I would like to thank my parents and my friends for their encouragement and
support without which the project will never be so successful. I treasure the kindness
of all the people who have helped me in the project and I believe I will live up to your
expectations.
E. Abstract:
Microelectronic technology has made a big difference in almost every corner of our
lives thanks to the progressive development of semiconductor industry. Nowadays,
people are making all those electronic devices smaller in size, and better in
performance. Yet, challenges also come along since further miniaturization of devices
require even better precision technology and the traditional planar fabrication
technology will soon feel its confinement. 1D nanostructured materials have brought
possibilities to overcome the difficulties and their potential to be applied in the
electronic industry has created excitement in a lot of research labs all over the world.
In this project, the SiNWs are used for all the experiments. They are synthesized by
the Metal-Nanoparticle-Catalyzed-Chemical-Etching method which provides a better
alignment of nanowires and easier controllability of its doping concentration as
compared to the chemical vapor deposition, laser ablation and thermal evaporation.
In order to measure the conductivity of the as-synthesized SiNWs, they were
dispersed onto the silicon wafer randomly. Different masks for lithography were used
to fabricate the electrodes. Shadow masking and photolithography defined the size and
the pattern of electrode layout. The electrode material to be deposited was also
carefully selected since either Schottky contact or ohmic contact would influence the
charge flow in the SiNW due to the difference between the work function of the metal
and that of the semiconductor. In order to achieve ohmic contact that allows the
current flow in either direction, metals with work function higher than the
semiconductor was used such as Au.
Once the I-V characteristic of the SiNW was measured, gate voltage applied to the
silicon substrate was also examined and the SiNW based field effect transistor was
thus constructed (similar to a metal-oxide-semiconductor structure). The transport
property of SiNW was manipulated by the application of different gate voltages. Since
the SiNW is of p-type, positive gate voltage tends to expel the holes in the nanowire to
the negative electrode, thus forming a depletion region with high resistance and a
VI
shallow conducting channel. The response of the SiNW FET shows an increase in the
conductivity of the SiNW and higher saturation voltage with the negative increase of
the gate voltage. Instead of scanning the source-drain voltage, the gate voltage was
scanned while keeping the source-drain voltage fixed. The current flow in the source
and drain and the corresponding gate voltage applied plotted in either linear or
logarithmic scale shed light on the threshold voltage and the depletion threshold
voltage of the device.
To improve the performance of SiNW FET, silicon dioxide layer was used to cover the
SiNW exposed in ambient environment. The surface was said to be isolated from
external environment and the transport properties were observed to change quite a lot.
The main mechanism accounting for the increase in hole mobility is the suppression
of reaction between the surface and molecular species and reduction of scattering by
the surface defects.
VII
1. Introduction:
1.1 Silicon Nanowires
A nanowire is a wire of dimension of the order of a nanometer (109 meters).
Alternatively, nanowires can be defined as structures that have a lateral size
constrained to tens of nanometers or less and an unconstrained longitudinal size. At
these scales, quantum mechanical effects are important hence such wires are also
known as "quantum wires". Many different types of nanowires exist, including
metallic (e.g., Ni, Pt, Au), semiconducting (e.g., InP, Si, GaN, etc.), and insulating
(e.g., SiO2, TiO2). Nanowires usually exhibit an aspect ratio of 1000 and more. As
such they are often referred to as 1-Dimensional materials. Nanowires have many
interesting properties that are not seen in bulk or 3-D materials. This is because
electrons in nanowires are quantum confined laterally and thus occupy energy levels
that are different from the traditional continuum of energy levels or bands found in
bulk materials.
As for the synthesis of SiNW, much effort has been made to prepare them by different
methods, such as chemical vapor deposition,[1] laser ablation,[2,3] thermal
evaporation decomposition,[4,5] supercritical fluid liquid solid (SFLS) synthesis,[6-7]
and other methods. These methods are quite accessible and will be briefed in the
second chapter.
As the building blocks for future nanoelectronics, the 1D nanowire can be employed
as active devices or interconnects that have great potential in improving the
performance of the electronic devices prevailing in the market now because of their
small size and reduced power consumption. Yet, everything has a trade off and the
same for semiconducting nanowires. The conductivity of a nanowire is expected to be
much less than the bulk material. The primary reason is that the scattering from the
wire boundary will severely hinder the effective transport of carriers when the width
of the nanowires is less than the mean free path of charge carriers. The so-called edge
1
effects come from atoms that lay at the nanowire surface and are not fully bonded to
neighboring atoms like the atoms within the bulk of the nanowire. The unbonded
atoms are often a source of defects within the nanowire, and may cause the nanowire
to conduct electricity more poorly than the bulk material.
different kinds of thin films, namely, thermal oxides, dielectric layers, polycrystalline
silicon, and metal films. Semiconductors can be oxidized by various methods; thermal
oxidation is by far the most important for silicon devices. Thermal oxidation of silicon
contains a reactor [9] consisting of a resistance-heated furnace, a cylindrical
fused-quartz tube containing the silicon wafers held vertically in a slotted quartz boat,
and a source of either pure dry oxygen or pure water vapor. The oxidation temperature
is generally in the range of 900-1200C and the typical gas flow rate is about
1liter/min.
Lithography and etching: lithography is the process of transferring patterns of
geometric shapes on a mask to a thin layer of radiation-sensitive material (called resist)
covering the surface of a semiconductor wafer. These patterns define the various
regions in an integrated circuit such as the implantation regions, the contact windows,
and the bonding-pad areas. The resist patterns defined by the lithographic process are
not permanent elements of the final device but only replicas of circuit features. To
produce circuit features, these resist patterns must be transferred once more into the
underlying layers comprising the device. The pattern transfer is accomplished by an
etching process that selectively removes unmasked portions of a layer.
Impurity doping: Diffusion and ion implantation are the two key methods of impurity
doping. Until the early 1970s, impurity doping was done mainly by diffusion at
elevated temperatures. In this method the dopant atoms are placed on or near the
surface of the wafer by deposition from the gas phase of the dopant or by using
doped-oxide sources. The doping concentration decreases monotonically from the
surface, and the profile of the dopant distribution is determined mainly by the
temperature and diffusion time. Since the early 1970s, many doping operation have
been performed by ion implantation. The doping concentration has a peak distribution
inside the semiconductor and the profile of the dopant distribution is determined by
the ion mass and implanted-ion energy. Both diffusion and ion implantation are used
for fabricating discrete devices because these processes complement each other.[10]
3
2. Literature Review
2.1. Various methods in the synthesis of silicon nanowires
2.1.1 Template-Directed Synthesis
Template-directed synthesis represents a straightforward route to 1D nanostructure.
The template simply serves as a scaffold within (or around) which a different material
is generated in situ and shaped into a nanostructure with its morphology
complementary to that of the template. When the template is only involved physically,
it is often necessary to selectively remove the template using post-synthesis treatment
(such as chemical etching and calcination) in order to harvest the resultant
nanostructures. In a chemical process, the template is usually consumed as the
reaction proceeds and it is possible to directly obtain the nanostructures as a pure
product.
As shown by Jorritsma and co-workers [13], metal nanowires as thin as 15nm could
be prepared by shadow sputtering a metal source against an array of V-grooves etched
on the surface of a Si(100) wafer. Fig.2.1. In another procedure, metal or
semiconductor was applied at normal incidence using techniques based on
vapor-phase deposition or solution-phase electrochemical plating, and then allowed to
reconstruct into 1D nanostructure at the bottom of each V-groove Fig.2.2.[14] Using
these approaches, continuous thin nanowires with lengths up to hundreds of
micrometers could be routinely prepared as parallel arrays on the surfaces of solid
supports that could be subsequently released into the free-standing form or be
transferred onto the surfaces of other substrates.
Channels in porous membranes provide another class of templates for use in the
synthesis of 1D nanostructure pioneered by Martin and several others. [15] Two types
of porous membranes Fig.2.3 are commonly used in such synthesis: polymer films
containing track-etched channels and alumina films containing anodically etched
pores. For track-etching, a polymer film (6-20 microns) is irradiated with heavy ions
5
to generate damage spots in the surface of this film. The spots are amplified by
chemical etching which facilitates the penetration of cylindrical pores into the films.
[16] A variety of materials have been examined for use with this class of templates.
The requirement for this method is that the material can be loaded into the pores using
liquid phase injection, or solution-phase chemical or electrochemical deposition.
Although the nanowires synthesized by this method are usually polycrystalline, the
major advantage associated with membrane-based templates is that both the
dimension and composition of nanowires can be easily controlled by varying
experimental conditions.
Fig. 2.1
Fig. 2.2
Fig. 2.3
Fig.2.1. Shadow sputtering against an array of V-grooves. Fig.2.2 Vapor-phase
deposition of 1D nanomaterials into V-grooves. Fig.2.3. Porous membrane used in the
1D structure synthesis.
will alloy with gold nanoparticles which are in a melted state when heated. As long as
the temperature is higher than the eutectic temperature of the binary system Fig.2.5,
the silane will decompose at the surface of the gold nanoparticle and the silicon will
dissolve into the liquid gold nanoparticle. As silicon continues to dissolve in the gold,
saturation will eventually occur as predicted by the phase diagram of the binary alloy
system. After that, the silicon will precipitate out from the liquid phase to form the
solid nanowire as we require. Since the eutectic temperature of Si-Au binary alloy
system is around 363C [21], theoretically the temperature of synthesizing the silicon
nanowire can be around 400 degrees which is not that high. The size of the as-grown
silicon nanowires is controlled by the dimensions of gold nanoparticles and the growth
rate is dependant on the partial pressure and temperature of the growing environment.
Growth defects such as kinking and bending are observed from the experiment due to
the different conditions used to grow the nanowires. The growth direction, as can be
predicted by thermodynamic principles, is along <111> family.[22-23]
Fig. 2.4
Fig.2.5
VLS mechanism
Si and SiO2. The vapor phase SixO generated by laser ablation seemed to be the key
intermediate in this oxide assisted process. The formation of silicon was believed to
occur through the following two steps:
SixO Six-1 + SiO (x>1)
2SiOSi + SiO2
The TEM observations suggested that these decomposition reactions first led to the
precipitation of Si nanoparticles encapsulated in shells of silicon oxide. Some of these
particles might be piled up on the surface of the silicon oxide matrix, and served as
seeds for the growth of nanowires in the following steps. SixO (x >1) layer at the tip of
each nanowire seemed to have a catalytic effect. This layer might be in or near a
molten state and thus capable of enhancing atomic absorption, diffusion, and
deposition. The SiO2 component in the shell might help to retard the lateral growth of
each nanowire. The precipitation, nucleation and growth of Si nanowires always
occurred in the region closest to the cold finger suggesting that the temperature
gradient was the driving force for the nanowire growth.[24-30]
and OAG, such as the absence of toxic and flammable gases and the control of size
and epitaxial growth of SiNW. The nanowires primarily grew along the <1 1 2> and
<1 1 0> directions, similar to SiNWs grown by the OAG method without any catalysts.
The side surfaces of the SiNW are made of the {1 1 1} and {1 1 0} facets for the
nanowire grown along [1 1 2] direction. The presence of those crystal facets could
minimize the total energy of the nanowire because the surface energy of the {1 1 1}
facets is the lowest and the energy of the side surfaces dictates the total surface energy
of a SiNW [32]
immersion time in the solution, the Ag particles that do not enter the pits will grow
into the branched silver dendrites.
In another system involving Fe (NO3)3/HF solution with Ag nanoparticles dispersed
on the silicon substrate, the temperature is as low as 50 degrees, the redox reaction
between the silicon atoms and Fe ions is very slow. Yet, the whole process can be
speed up by covering the silicon substrate with a layer of Ag nanoparticle film. Metal
contamination has a strong catalytic activity for the cathodic reaction. The Ag
nanoparticle can act as local micro-cathodes which are for the reduction of Fe ions,
owing to the more positive redox potential of Ag+/Ag system compared to Fe3+/Fe2+
couple, the general reaction equation is presented below:
Fe3+ + e-Fe2+;
Si (s) + H2OSiO2 + 4H+ + 4e-;
SiO2 + 6HF H2SiF6 + 2H2O;
Therefore, in the Ag/Si/HF/Fe(NO3)3 system, the Fe3+ ions have a strong tendency to
obtain electrons preferentially from Ag particles and be reduced to Fe2+ ions, while the
silicon underneath the Ag nanoparticles is locally oxidized into SiO2. The reaction
proceeds as long as the Si atoms are able to dissolve into the solution, or until thick
SiO2 forms, thereby halting electron transfer. In the present HF/ Fe (NO3)3 solution,
the dissolution rate of SiO2 by HF is higher than the Si oxidation rate by Fe (NO3)3.
Therefore, the Si surface is always exposed to the solution.
Since the Ag nanoparticle is pinned Fig.2.6 in the hole there is confinement in the
horizontal movement. All Ag nanoparticles will just sink Fig.2.7 in the holes and their
sinking tracks will interconnect with each other and the silicon substrate looks porous
in this sense. The walls of the pores Fig.2.8 that are left by the Ag nanoparticle
constitute the 1D SiNWs as observed in the SEM. The galvanic displacement process
will not come to a halt until the Fe3+ ions are exhausted in the reaction solution. By
utilizing this method, single-crystalline SiNWs with desirable crystallographic
10
orientations can be readily and controllably created by the selection of Si wafers with
the corresponding crystallographic orientations. [38]
Fig.2.6
Fig.2.7
SiNW
synthesized
Fig.2.8
Fig.2.6 schematic graph showing the Ag particle is pinned. Fig.2.7 schematic graph
showing the sinking track of Ag. Fig.2.8 cross-section of SiNW synthesized
11
3. Experimental
3.1 Synthesis of silicon nanowires by metal-nanoparticle catalyzed chemical
etching
The synthesis of large-area oriented 1D silicon nanostructure arrays was conducted in
a Teflon-lined stainless steel autoclave. The production process comprises 3 steps: 1)
the silicon wafers were cleaned with acetone (5 min), ethanol (5 min), deionized water
(2-3 times) and H2SO4/H2O2 (3:1 H2SO4 (97%)/H2O2 (30%),10 min), then the wafers
were thoroughly rinsed with deionized water (10 min) and dipped into a solution of
HF (1 min); 2) electroplating the metal-nanoparticle films onto the cleaned silicon
surface; and 3) immersion of the metal-nanoparticle-covered silicon wafers into
HF-based aqueous chemical etching solutions contained in a sealed vessel and treated
for the desired time (2060 degrees).
All the experiments described here were performed at 50 degrees. The thickness of
films (or the length of 1D silicon nanostructures) could be effectively controlled
through adjusting the etching time, and film sizes could be readily made as large as
needed and are ultimately limited only by the vessel dimensions. The concentrations
of HF and AgNO3 for the deposition of Ag nanoparticle films were 4.6 and 0.01m,
respectively.
12
3.1.1.2 TEM
Transmission electron microscope (TEM) was used to examine the crystal structure of
SiNWs. TEM working principle is like a slide projector. The electron gun in the TEM
projects a beam of electron through the sample. While the electron beam passes
through the sample, the beam is deflected by the lattice structures and the materials of
the sample. The transmitted beam is then projected onto the viewing screen, forming
an enlarged image of the sample. The diffraction mode in TEM could clearly show the
electron diffraction pattern of the SiNW showing the crystal structure of the material.
3.1.1.3 EDX
EDX is used in conjunction with SEM. An electron beam strikes the surface of a
conducting sample. The energy of the beam is typically in the range of 10-20keV.
This causes X-rays to be emitted from the point of the material. The energy of the
X-rays emitted depends on the particular material. Therefore, EDX was used to
characterize the composition of SiNWs.
13
14
Polymeric Developers were applied to remove the exposed photoresist. Gold was then
deposited onto the windows etched away by the developer and lift-off technique was
used to remove the unexposed photoresist.
Fig.3.1
Fig.3.2
2
the substrate, it was rather difficult to apply the voltage directly. A piece of copper was
attached to the conducting glue which directly contacted the bottom of the silicon
substrate. A MOS structure was formed and the electrostatic potential could be altered
by changing the gate voltage.
A two point probe station Fig.3.3 was used to measure the I-V characteristics of the
device and data could be collected automatically by the computer to calculate the
mobility of the charge carriers in the SiNW.
2 point probe
Copper plate
Glass
Conducting glue
Silicon Wafer
16
SiNW
Silicon oxide
Gold
Substrate
Fig.3.4 the configuration of the SiNW device
17
18
19
20
than that of p-type SiNW, since there are more energetic holes in the metal side, they
will tunnel to the semiconductor in search of lower energy until the equilibrium is
reached, i.e. the alignment of Fermi energy in both sides. The holes will accumulate at
the contact region and the conducting holes in either side have about the same energy
level and there is no barrier in between when they cross the junction in either direction
under the influence of an applied field. In the case of ohmic contact, the linear region
is used to calculate the resistance of the SiNW together with its contact resistance
once the slope of the curve is obtained by OriginPro 7.5.
and L is the length of the SiNW; A is the cross-section area of the SiNW, respectively.
23
Fig.4.6 SEM of Sp A
Fig.4.7.SEM of Sp B
in which the gap length is long and the electrical property that we have measured may
consist of a bundle of SiNWs instead of a single one. SEM images Fig.4.11-12 show
the sample A and B prepared by photolithography.
SiNW found lying on the central
25
The table presents the results of the calculated resistivity of the SiNWs either through
photolithography technique or shadow mask technique.
Shadow Mask
R(B-1)
(cm)
Sample A
3.0E-4
1.26E-9
3.80E-7
2.6E6
10.92
Sample B
2.0E-4
1.14E-9
2.151E-7 4.65E6
26.5
Sample C
5.3E-4
1.26E-9
5.031E-8
2.0E7
47.4
R(B-1)
(cm)
Sample A
2.0E-4
3.14E-10
9.86E-8
10E7
15.7
Sample B
2.0E-4
2.15E-10
1.06E-7
9.4E6
10.11
the developer etches the photoresist, the underlying oxide is exposed to the air. Gold
can not be directed evaporated onto the silicon substrate because of its poor tackiness
to the oxide. The layer of Ti acts as a buffer layer so that gold can contact well with
the SiNW as well as the substrate. Due to the extreme thinness of Ti layer, the contact
between the Au and the SiNW is still ohmic. The quality of metal evaporation and the
coverage of gold film onto the nanowires are of great importance in calculating the
resistance of the bulk SiNW. The surface of the interface might be very rough all the
way along the contact, making the actual contact area much smaller than the apparent
contact area illustrated in Fig.4.13. When the SiNW is synthesized by MNCCE and
prior to electrode deposition, the surface of silicon oxide might be oxidized to a
certain extent in the atmosphere. This layer of oxide film might be gapped between
the metal and the semiconductor restricting the flow of charge carriers. The surface
defects such as voids and pores and impurities could serve as scattering sites reducing
the MFP of the charge carriers and the contact resistance could be very high in this
case. Possible solution to reduce the contact resistance is to anneal the
metal-semiconductor in high temperature for a while, the stress and strains could be
annealed out with time and gold film could flow to cover the SiNW well in order to
increase the contact area.
27
attributed to the fact that the pinch-off voltage remains the same, so do the number of
holes that are attracted to the pinch-off point P.
Conducting
channel of SiNW
(shaded)
SiO2
Si
Depletion Region
29
30
Fig.4.17 Ids vs Vg plotted in the linear scale and log scale. Inset is the SEM image of
the measured sample
The capacitance of the SiNW is calculated from the following equation assuming the
metal cylinder on an infinite metal plate model [39]:
C= 2 0 L / ln(4h / d )
is the dielectric constant of SiO2 and 0 is the dielectric constant of vacuum. L is
the source-drain nanowire length, h is the SiO2 thickness and d is the diameter of
SiNW.
The hole mobility of SiNW is obtained with the equation described below:
C
1
Vsd
g m Vsd = 0.2V ,
L2
33
Fig.4.20 Ids vs Vg plotted in the linear scale and log scale with threshold voltage about
2 V. Inset is the SEM image of the measured sample
The results of the samples in the ambient condition and the result from the sample
coated by a layer of oxide are presented in this table with key parameters highlighted:
Table 4.2 mobility obtained in the ambient condition and SiO2 treated condition
Air
Diameter(m)
Length(m)
h (m)
Vsd(V)
gm
Sp A
1.5E-7
2.5E-6
3E-7
0.2
Sp B
1.5E-7
4E-6
3E-7
0.2
8E-9
SiO2
Diameter(m)
Length(m)
h (m)
Vsd(V)
gm
Sp A
1.5E-7
2.5E-6
3E-7
0.06
6.8E-8
3.34E-8 2.61E-16
4.17E-16
C(F)
40.03
15.34
2.61E-16 271.68
35
5. Conclusion
In this project, p-type SiNWs are synthesized by metal-nanoparticle-catalyzed
chemical etching method. The as-synthesized SiNWs have exhibited good alignment
and easier control of doping concentration within the SiNW. It provides us a very
convenient way to cast the SiNW with the desired doping concentration for practical
application without going through the complicated process of doping the SiNW during
its synthesis. The cross section of the as-synthesized SiNW is irregular due to the
mechanism of etching and this may affect the charge transport in the SiNW devices
and their overall performances.
Simple devices can be constructed with the 1D nanowire through several processes,
namely, preparation of silicon wafer, dispersion of nanowires randomly onto the wafer,
lithography technique to transfer a pattern of a mask onto the silicon substrate,
deposition of electrode contact material followed by measurement of transport
properties of the particular nanowires. Among all these processes, deposition of
electrode material into the open windows can be critical in device construction.
Electrode materials with an appropriate work function should also be carefully
selected to form ohmic contact with the semiconductor nanowire instead of a contact
barrier. In addition, the contact resistance between the semiconductor and the metal
also affect the behavior of devices due to the defects in the interface of the two
materials serving the scattering sites for charge carrier and the real contact area is
much less than the apparent one.
To measure the transport characteristic of SiNW such as the conductance of SiNW and
mobility of charge carriers, a gate voltage is applied to the silicon substrate to
construct a SiNW-based FET. The response of SiNW in terms of its Ids vs. Vds curve
will show the effects of the gate. For p-type devices, negative gate voltage attracts
more holes to the conducting channel so as to increase the carrier density while
positive voltage expels the holes and form a depletion region. Current saturation will
36
occur when pinch-off point is reached meaning the depletion region is so wide as to
cut off the conducting channel in the SiNW.
Improvement is observed when the surface of SiNW is covered with a layer of
insulating silicon oxide which has effectively eliminated the influence of external
environment. The conductance and mobility increases quite compared with the result
obtained in the ambient environment. This is a clear indication of the effect of
molecular species on the surface property of SiNW. It is predicted that certain
molecules in the atmosphere can trap the holes in the surface of the nanomaterials
although the details of the mechanism is not clear yet.
6. Future work
Since the performance of SiNW FET, namely the conductance, the mobility is affected
by the surface property a lot due to the large surface to volume ratio. Passivation of
the surface defects seem to be very important. Once the defect in the surface region is
saturated, its dangling bonds which may carry certain charge will be neutralized and
form a stable chemical species, reducing the possibility of attracting charge carriers in
the conducting channel. Certain chemicals can be used to react with the surface of
SiNW, altering the nature of its property. In addition, the quality of contact area should
further be improved so that resistance in the contact can be further reduced.
37
7. List of Reference
[1] J. Westwater, D. P. Gosain, S. Tomiya, S. Usui, H. Ruda, J. Vac. Sci. Technol. B
1997, 15, 554.
[2] A. M. Morales, C. M. Lieber, Science 1998, 279, 208.
[3] N. Wang, Y. F. Zhang, Y. H. Tang, C. S. Lee, S. T. Lee, Appl. Phys. Lett. 1998, 73,
3902.
[4] D. P. Yu, Z. G. Bai, Y. Ding, Q. L. Hang, H. Z. Zhang, J. J. Wang, Y. H. Zou, W.
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