Sources of Mismatches

Analog Layout Techniques

Howard Luong
eeluong@ee.ust.hk
852-2358-8514

Mask Production and Alignment

Lateral Diffusion
Over-Etching / Undercut
Boundary Conditions
Non-Uniformity
Analog Layout, Howard Luong

Layout Guidelines

Resistor Layout

Build Large Components Out of Many Identical

Units
Use Stacked Layout for Large Devices
Use Common-Centroid Symmetry Whenever
Possible

L L
=
W tW
1
=
qN D

Consider Boundary Conditions and Use Dummy

Devices if Necessary

Analog Layout, Howard Luong

R = Rsh

Analog Layout, Howard Luong

Resistor Layout

Resistor Layout

For Large Resistance, Serpentine Structures Should

Be Used to Minimize Area
Each Corner Can Be Approximated as 0.5 to 0.55
Squares
Round Corners Can Be Estimated More Accurately
Each Contact Can Be Estimated to Contribute 0.14
Squares
Number of Squares
= 6 x 4 + 5 + 5 x 2 x 0.55 + 2 x 0.14 = 34.78
Analog Layout, Howard Luong

Resistor Layout

Analog Layout, Howard Luong

Layout of Two Matched Resistors

Typically ,
L >> W
R L W Rsh
W

R
L
W
Rsh
W
Absolute Resistance Error Can Be Minimized by
Maximizing Width W
Layout Guidelines Should Be Observed to Obtain
Good Matching Ratio Between Two Resistors (~
0.1%)
Analog Layout, Howard Luong

Analog Layout, Howard Luong

Properties of Different Capacitor Types

Capacitor Layout
MOS Capacitors Using Gate-Oxide Thickness Can Be
Used to Achieve Maximum Capacitance Per Unit Area
Fringing and Parasitic Capacitance Can Be Significant
and Should Be Included for Accuracy
Poly-To-Poly Capacitors Are Good In Terms of
Linearity
Without Poly-To-Poly, Metal-To-Metal Capacitors
Can Be Used
To Minimize Chip Area, Sandwiched-Type Capacitors
Can Be Used

Analog Layout, Howard Luong

Characteristics of Poly Capacitors

Analog Layout, Howard Luong

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Sandwiched-Type Capacitors
C21

Analog Layout, Howard Luong

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Analog Layout, Howard Luong

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Capacitor Layout
C=

ox
tox

Matched Capacitors
Capacitor Error Proportional To Ratio of The
Perimeter to The Area

A = CoxWL

A Capacitor Error Is Minimized If Dimension Are

Designed to Minimize P/A Ratio => Squared
Structures Would Yield Minimum Error For A
Given Capacitance

C L W (W + L) P P
=
+
=
=

2A A
C
L
W
WL
P = Perimeter
A = Area
= W = L
Analog Layout, Howard Luong

Same Layout Guidelines Should Be Observed to

Minimize Mismatches Between Two Capacitors
Moreover, Good Matching Can Be Achieved if Two
P/A Ratios Are Designed to Be The Same
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Analog Layout, Howard Luong

Matched Capacitors with A Non-Integer

Ratio

Layout of Matched Capacitors

K=

C2 A2 x2 y2
=
= 2
C1 A1
x1

K=

A2 P2 x2 + y2
= =
2 x1
A1 P1

y2 = x1[ K K ( K 1)] = Kx1 (1 1

x2 =
Analog Layout, Howard Luong

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15

1
)
K

x1
1 1

1
K
Analog Layout, Howard Luong

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Transistor Layout

Transistor Layout

In Addition to All Layout Guidelines Discussed,

Following Guidelines Should Also Be Used:
Minimize Parasitic Series Resistance By Using
Many Contacts As Possible
Use Multiple Small Contacts As Opposed to
Single Large Contact to Reduce Metal Surface
Curvature to Reduce Risk of Micro-Fracture

Analog Layout, Howard Luong

Use Stacked Structures to Realize Large

Transistors to Minimize Total Area and Diffusion
Capacitance
Use Multiple Fingers to Minimize Gate
Resistance to Minimize Noise and Maximize
Speed

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Stacked Transistor Layout

Analog Layout, Howard Luong

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Stacked Transistor Layout

'

RG
1
= 2
RG kn
Odd Number of Fingers :
Cdb ' Csb ' nodd + 1 1
=
=

Cdb Csb
2nodd
2
Even Number of Fingers :
Cd ,out ' neven + 2 Cd ,in ' 1
;
=
=
Cd ,out
2neven
Cd ,in 2
Analog Layout, Howard Luong

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Analog Layout, Howard Luong

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Layout Guidelines for Noise

Minimization

Layout of Differential Pair

D1

Maximize Separation Between Analog and Digital

Bias Lines

D2

Use Multiple Supply and Ground Connections and

I/O Pins When Possible and Put Them As Close to
Pads As Possible

G1
G2

Use Guard Rings for Isolation

S12

Use Wells for Isolation, Shielding, and As Bypass

Capacitors for Supply Lines
Analog Layout, Howard Luong

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Supply and Ground Connections

A1

Analog Layout, Howard Luong

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Supply and Ground Connections

D1

A2

A1

V Vsup

A2

D1
V Vsup

VR
VR

VL = L(di/dt)

I/O Pin

Multiple I/O Pins

Vsup

Analog Layout, Howard Luong

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Analog Layout, Howard Luong

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Guard Rings and Shields

Layout Guidelines for Noise

Minimization

p+

Use Metal Lines with Constant Bias As Shields

Circuit

Fill Up Unused Space with Substrate Contacts

Always Connect Bottom Plate of Capacitors to
Less-Critical Nodes To Minimize Noise Coupling
Through Substrate

VDD

GND
p+

n+
n well

p- substrate

Guard rings
top views
VB
signal
VB

p+

Cbypass

cross-section views
VB

VB

VB
shields

Analog Layout, Howard Luong

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System Layout and Floorplan

Analog Layout, Howard Luong

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Example of a Layout Floorplan

Similar to Device Layout, System Layout Require

Careful Floorplan and All Layout Techniques
Discussed Should Be Used:
Maximize Spacing Between Critical Analog and
Digital Components
Minimize Connection to Critical Nodes
Minimize Coupling or Crossing Between
Sensitive Lines
Use Shields Whenever Space and Speed Allow
Analog Layout, Howard Luong

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Analog Layout, Howard Luong

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Potential Oscillation for Bias Lines

Potential Oscillation for Bias Lines

RS

Bias Lines May Cause Oscillation if Not Handled

Properly

Bondwire

Bondwire / Cable
Pad

Bias Node

VB

IB

Bias Devices together with Capacitive Feedback C1

and C2 or Coupling May Become Negative Gm

Bias
Device

LS

If Bias Current IB Large Enough, Oscillation May

Occur Due to LC Tank and Negative Gm

C1

CB

C2

Bypass Capacitor CB Actually Hurts Stability by

Shorting Damping Resistor RS

DUT
Package / PCB

Analog Layout, Howard Luong

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Potential Oscillation for Bias Lines Solution

Remove Bypass Capacitor CB (Although May Sound
Counter-Intuitive!)
Increase Damping Resistor RS
Avoid Sharing Bias Lines to Minimize Bias Current IB
Add Bypass Capacitance CB As Close to Bias Node
As Possible
Use a Current Bias to Provide Low-Impedance Node
(to Decrease Inductor Q and to Damp Out Oscillation)
Analog Layout, Howard Luong

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Analog Layout, Howard Luong

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References
D. Johns, and K. Martin, Analog Integrated Circuit
Design, New York, Wiley, 1997
P. Gray, et al, Analysis and Design of Analog Integrated
Circuits, New York, Wiley, 4th ed., 2001.
B. Razavi, Design of Analog CMOS Integrated Circuits,
McGraw Hill, 2001
R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit
Design, Layout, and Simulation, IEEE Press, 1998
M. Ismail and T. Fiez, Analog VLSI Signal and
Information Processing, Mc-Graw-Hill, 1994.

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