FIELD PROGRAMMABLE GATE ARRAYS

A SEMINAR REPORT
Submitted in partial fulfilment for the award of the Degree of

Bachelor of Technology
in
Electrical and Electronics Engineering
By
ARCHANA SASIKUMAR
(Roll No: B120760EE)

Department of Electrical Engineering

NATIONAL INSTITUTE OF TECHNOLOGY CALICUT
NIT Campus P.O., Calicut - 673601, India
2016
1

CERTIFICATE

This is to certify that the thesis entitled FIELD PROGRAMMABLE GATE

ARRAYS is a bona fide record of the seminar done by ARCHANA SASIKUMAR
(Roll No.B120760EE) under my supervision and guidance, in partial fulfilment of the
requirements for the award of Degree of Bachelor of Technology in Electrical &
Electronic Engineering from National Institute of Technology Calicut for the year
2016.

Dr. Sunitha R
Assistant Professor
Dept. of Electrical Engineering
NIT Calicut
Place: Kozhikode
Date: 01-02-2016

ACKNOWLEDGEMENT

I would like to express my gratitude to our teacher in-charge Dr. Sunitha R., for
giving us an opportunity to undertake this seminar. I would also like to thank my
parents. Their constant encouragement and motivation has always helped me in all the
challenges that I have undertaken. Last but not the least; I would like to thank God
Almighty for showering his blessings on us.

ARCHANA SASIKUMAR
(Roll No. : B120760EE)

.
.

ABSTRACT

A field-programmable gate array (FPGA) is an integrated circuit designed to be

configured by a customer or a designer after manufacturing hence "fieldprogrammable". The FPGA configuration is generally specified using a hardware
description language (HDL), similar to that used for an application-specific integrated
circuit (ASIC). FPGAs contain an array of programmable logic blocks, and a
hierarchy of reconfigurable interconnects that allow the blocks to be "wired together",
like many logic gates that can be inter-wired in different configurations. Logic
blocks can be configured to perform complex combinational functions, or merely
simple logic gates like AND and XOR. In most FPGAs, logic blocks also include
memory elements, which may be simple flip-flops or more complete blocks of
memory. As a part of this project a basic introduction about FPGAs is given. The
architecture of FPGA and differences between FPGAs and processors has been
discussed. The advantages and applications have also been mentioned.

CONTENTS

Chapter No.

Title

Page No.

List of Abbreviations

ii

List of Figures

iii

List of Tables

iv

INTRODUCTION
FPGA ARCHITECTURE
2.1
Introduction
2.2
Configurable Logic Blocks
2.3
Interconnects
2.4
I/O Blocks

1
2
3
5
5

2.5
3.

FPGA Pins

FPGA FUNDAMENTALS
3.1
3.2
3.3
3.4

FPGA vs Processors
FPGA Programming
Applications of FPGA
Advantages of FPGA

8
10
12
14

4.

Conclusion

16

8.

References

17

List of Figures

Figure No.

Title

Page No.

2.1

Different parts of an FPGA

2.2

Flip-Flop Symbol

2.3

Four input LUT

2.4

FPGA Pins

4.1

Graphical Design for Half Adder

10

List of Tables

Table No.
2.1

Title
Truth Table for Boolean AND Operation

Page No.
4

CHAPTER 1
INTRODUCTION
Field-programmable gate arrays (FPGAs) are reprogrammable silicon chips. Ross
Freeman, the cofounder of Xilinx, invented the first FPGA in 1985. FPGA chip
adoption across all industries is driven by the fact that FPGAs combine the best parts
of application-specific integrated circuits (ASICs) and processor-based systems.
FPGAs provide hardware-timed speed and reliability, but they do not require high
volumes to justify the large upfront expense of custom ASIC design.
FPGA is an integrated circuit. However the difference from the others is that they can
be configurable as we wish. We can explain this as follows: In ordinary or standard
ICs which cannot be programmable, there are fixed interconnections between the
transistors. Unless they are burned or another unfortunate event does not come, they
cannot be changed.
Reprogrammable silicon also has the same flexibility of software running on a
processor-based system, but it is not limited by the number of processing cores
available.

Unlike processors, FPGAs are truly parallel in nature, so different processing

operations do not have to compete for the same resources. Each independent
processing task is assigned to a dedicated section of the chip, and can function
autonomously without any influence from other logic blocks. As a result, the
performance of one part of the application is not affected when you add more
processing.

CHAPTER 2
FPGA ARCHITECTURE
2.1 INTRODUCTION
Every FPGA chip is made up of a finite number of predefined resources with
programmable interconnects to implement a reconfigurable digital circuit and I/O
blocks to allow the circuit to access the outside world. Figure 2.1 shows the different
parts of an FPGA.

Figure2.1 Different Parts of an FPGA

FPGA resource specifications often include the number of configurable logic blocks,
number of fixed function logic blocks such as multipliers, and size of memory
resources like embedded block RAM. Of the many FPGA chip parts, these are
typically the most important when selecting and comparing FPGAs for a particular
application.
Embedded Block RAM memory is available in most FPGAs, which allows for onchip memory in your design. These allow for on-chip memory for your design.

2.2 CONFIGURABLE LOGIC BLOCKS

The configurable logic blocks (CLBs) are the basic logic unit of an FPGA. The
purpose of programmable logic block in a FPGA is to provide the basic computation
and storage elements used in digital systems. Sometimes referred to as slices or logic
cells, CLBs are made up of two basic components: flip-flops and lookup tables
(LUTs). In addition to a basic logic block, many modern FPGAs contains a
heterogeneous mixture of different blocks, some of which can only be used for
specific functions, such as dedicated memory blocks, multipliers or multiplexers; of
course, configuration memory is used throughout the logic block to control the
specific function of each element within the block. Various FPGA families differ in
the way flip-flops and LUTs are packaged together, so it is important to understand
flip-flops and LUTs.

FLIP-FLOPS

Flip-flops are binary shift registers used to synchronize logic and save logical states
between clock cycles within an FPGA circuit. On every clock edge, a flip-flop latches
the 1 or 0 (TRUE or FALSE) value on its input and holds that value constant until the
next clock edge. Figure 2.2 shows a typical Flip-Flop Symbol.

Figure 2.2 Flip-Flop Symbol

LOOK-UP TABLES (LUTs)

Figure 2.3 Four-Input LUT

Much of the logic in a CLB is implemented using very small amounts of RAM in the
form of LUTs. It is easy to assume that the number of system gates in an FPGA refers
to the number of NAND gates and NOR gates in a particular chip. But, in reality, all
combinatorial logic (ANDs, Ors, NANDs, XORs, and so on) is implemented as truth
tables within LUT memory. A truth table is a predefined list of outputs for every
combination of inputs. A four-input LUT is shown in Figure 2.3.

The corresponding truth table for the two inputs of an AND operation is shown in
Table 2.
Table 2.1. Truth Table for Boolean AND Operation

Input 1

Input 2

Output

MULTIPLIERS AND DSP SLICES

The seemingly simple task of multiplying two numbers together can get extremely
resource intensive and complex to implement in digital circuitry.
Multiplying two 32-bit numbers together will take up more than 2000 operations for a
single multiply. Because of this, FPGAs have prebuilt multiplier circuitry to save on
LUT and flip-flop usage in math and signal processing applications.
Many signal processing algorithms involve keeping the running total of numbers
being multiplied, and, as a result, higher-performance FPGAs like Xilinx Virtex-5
FPGAs have prebuilt multiplier-accumulate circuitry. These prebuilt processing
blocks, also known as DSP48 slices, integrate a 25-bit by 18-bit multiplier with adder
circuitry.

2.3 INTERCONNECTS
While the CLB provides the logic capability, flexible interconnect routing routes the
signals between CLBs and to and from I/Os. Routing comes in several flavours, from
that designed to interconnect between CLBs to fast horizontal and vertical long lines
spanning the device to global low-skew routing for Clocking and other global signals.
The design software make the interconnect routing task hidden to the user unless
specified otherwise, thus significantly reducing design complexity.

2.4 I/O BLOCKS

The media or mean required to interface the logic blocks and routing architectures to
the wide range of external components to FPGA called as I/O pads or programmable
I/O. The I/O pad and surrounding supporting logic circuitry forms as an I/O cells.
These cells are important components of an FPGA and consume a significant portion
(approximately 40%) of FPGAs area. The design of I/O programmable blocks is
challenging as there is a great diversity in the supply voltage and reference voltage
standards. One of the most important decisions in I/O architecture design is the
selection of standards that will be supported. This involves carefully made trade-offs
because, unlike LUTs, which can implement any digital functions, I/O cells can
generally implement the voltage standards selected by designers. Supporting large
number of standards can increase the silicon area required for I/O cells significantly.
Additionally to support more number of standards pin capacitance may increase with
more number of pins, which can limit the performance.

Over the time, the basic FPGA architecture has been further developed through the
addition of more specialized programmable functional blocks. The special function
blocks like- embedded memory (Block RAMs), arithmetic logic (ALUs), multipliers,

DSP-48 and even embedded microprocessors have been added due to a frequent need
of such resources for an application. The result is that many FPGAs have the
heterogeneous mixture of resources than early FPGAs.

Todays FPGAs provide support for dozens of I/O standards thus providing the ideal
interface bridge in your system. I/O in FPGAs is grouped in banks with each bank
independently able to support different I/O standards. Todays leading FPGAs provide
over a dozen I/O banks, thus allowing flexibility in I/O support.

2.5 FPGA PINS

FPGA pins are generally divided into two categories.

Dedicated pins

User pins

a) Dedicated pins
20% to 30% of all the pins of an FPGA are reserved. According to the special
functions they realized, these pins are divided into three categories.

Power Pins: They provide power and ground which is needed by FPGA.

Configuration Pins: They are used to upload the created program to FPGA.

Clock Pins: They are reserved pins for Clock signals.

b) User Pins:

These are standard I/O pins that can be configurable by user. They are divided
into three categories such as Input, Output, Input / Output Each I/O pin is
connected to an I/O cell in FPGA. Power needed by I/O cells is provided by
VCCIO.
Despite having more than one VCCIO pins, all pins with the same voltage to
feed in former FPGAs.
Whereas in the new production FPGAs, I/Os can be divided into groups and
these groups can be fed from different voltages. So, a group of I/O pins can be
working with 3.3 V, while other groups of I/O pins work with 2.5 volt.

Fig. 2.4 FPGA Pins

CHAPTER 3
FPGA FUNDAMENTALS

3.1 FPGA vs PROCESSORS

The main and the most significant difference between the microcontroller processor
and the FPGA is that FPGA doesnt have a fixed hardware structure; on the contrary
it is programmable according to user applications. However processors have a fixed
hardware structure. It means that all the transistors memory, peripheral structures and
the connections are constant. Operations which processor can do (addition,
multiplication, I/O control, etc.) are predefined. And users make the processor do
these operations "in a sequential manner" by using a software, in accordance with
their own purposes.

Hardware structure in the FPGA is not fixed so it is defined by the user. Although

logic cells are fixed in FPGA, the functions that they perform and the
interconnections between them are determined by the user. So operations that FPGAs
can do are not predefined. You can have the processes done according to the written
HDL (Hardware Description Language) code "in parallel" which means
simultaneously. Ability of parallel processing is one of the most important features
that separate FPGA from processor and makes it superior in many areas.
CPU's are sequential processing devices. They break an algorithm up into a sequence
of operations and execute them one at a time.
FPGA's are (or, can be configured as) parallel processing devices. An entire algorithm
might be executed in a single tick of the clock, or, worst case, far fewer clock ticks
than it takes a sequential processor. One of the costs to the increased logic complexity
is typically a lower limit at which the device can be clocked.
Bearing the above in mind, FPGA's can outperform CPU's doing certain tasks
because they can do the same task in less clock ticks, albeit at a lower overall clock
rate. The gains that can be achieved are highly dependent on the algorithm.
Further, because you can build multiple parallel execution units into an FPGA, if you
have a large volume of data that you want to pass through the same algorithm, you
can distribute the data across the parallel execution units and obtain further orders of
magnitude higher throughput than cant be achieved with even a multi-core CPU.
Processors are generally more useful for routine control of a particular circuit. For
example, using FPGA for simple functions such as turn on and off any device from a
computer may be overstated. This process can be easily done with many ordinary
microcontroller (PIC series, etc.). However, FPGA solution is more reasonable, if you
want

to

process

on

high-resolution

video

data

on

the

computer.

Because video processing requires processing large data in high speed and make these
types of applications are very suitable for FPGA that is capable of parallel
processing. Since the user can determine the hardware structure of FPGAs, you can

program FPGA to process larger data with few clock cycles, whereas this is not
possible with the processor because data flow is limited by processor bus (16-bit, 32
bit, etc.) and the processing speed.
As a result, applications that require more performance such as intensive data
processing FPGA has come to the fore, and processor / microcontroller has come to
the fore for routine control operations. Nevertheless, processors / microcontrollers can
be embedded into the FPGA since they are logic circuits in fact. Thus it is possible to
define and use processor and user-specific hardware functions on only one chip by
using FPGA. This solution gives engineers the opportunity to control the hardware
because of its great flexibility.
You can modify and update whole design (FPGA on the processor and other logic
circuits) by only changing the code on FPGA, without any change on circuit board
layout. In this way, you can add different functions, improve performance and make
your design resistant of time without having to redesign the cards.

3.2 FPGA PROGRAMMING

FPGAs are programmable hardware. Programming the FPGAs are necessary in order
to make them ready for use. (ISE Compiler for Xilinx, and Quartus II for Altera are
used for this purpose.)
Two methods are used to program the FPGA.

Graphical Design

Hardware Description Language (HDL)

Logic gates and tools in the library of the compiler program (ISE, Quartus, etc) are
used in graphical design method. HDL is a programming language which helps to

model hardware. VHDL and Verilog are the most widely used types of HLDs. Figure
4.1 shows of screen shot for the Graphical Design of a Half-Adder.

Fig 4.1 Graphical Design for Half Adder

To describe the hardware of a half adder, write a VHDL code like below:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity HALF_ADDER is
Port ( A

: in STD_LOGIC;

: in STD_LOGIC;

SUM

: out STD_LOGIC;

CARRY : out STD_LOGIC);

end HALF_ADDER;
architecture Behavioral of HALF_ADDER is
begin
SUM

<= A XOR B;

CARRY <= A AND B;

end Behavioral;

3.3 ADVANTAGES OF FPGAS

1.

PerformanceTaking advantage of hardware parallelism, FPGAs exceed the

computing power of digital signal processors (DSPs) by breaking the paradigm of
sequential execution and accomplishing more per clock cycle. BDTI, a noted
analyst and benchmarking firm, released benchmarks showing how FPGAs can
deliver many times the processing power per dollar of a DSP solution in some
applications. Controlling inputs and outputs (I/O) at the hardware level provides
faster response times and specialized functionality to closely match application
requirements.

2.

Time to marketFPGA technology offers flexibility and rapid prototyping

capabilities in the face of increased time-to-market concerns. You can test an idea
or concept and verify it in hardware without going through the long fabrication
process of custom ASIC design. You can then implement incremental changes
and iterate on an FPGA design within hours instead of weeks. Commercial offthe-shelf (COTS) hardware is also available with different types of I/O already
connected to a user-programmable FPGA chip. The growing availability of highlevel software tools decreases the learning curve with layers of abstraction and
often offers valuable IP cores (prebuilt functions) for advanced control and signal
processing.

3.

Cost The nonrecurring engineering (NRE) expense of custom ASIC design

far exceeds that of FPGA-based hardware solutions. The large initial investment
in ASICs is easy to justify for OEMs shipping thousands of chips per year, but
many end users need custom hardware functionality for the tens to hundreds of
systems in development. The very nature of programmable silicon means you

have no fabrication costs or long lead times for assembly. Because system
requirements often change over time, the cost of making incremental changes to
FPGA designs is negligible when compared to the large expense of respinning an
ASIC.

4.

ReliabilityWhile software tools provide the programming environment,

FPGA circuitry is truly a hard implementation of program execution. Processorbased systems often involve several layers of abstraction to help schedule tasks
and share resources among multiple processes. The driver layer controls hardware
resources and the OS manages memory and processor bandwidth. For any given
processor core, only one instruction can execute at a time, and processor-based
systems are continually at risk of time-critical tasks pre-empting one another.
FPGAs, which do not use OSs, minimize reliability concerns with true parallel
execution and deterministic hardware dedicated to every task.

5.

Long-term maintenanceAs mentioned earlier, FPGA chips are fieldupgradable and do not require the time and expense involved with ASIC redesign.
Digital communication protocols, for example, have specifications that can
change over time, and ASIC-based interfaces may cause maintenance and
forward-compatibility challenges. Being reconfigurable, FPGA chips can keep up
with future modifications that might be necessary. As a product or system
matures, you can make functional enhancements without spending time
redesigning hardware or modifying the board layout.

3.4 APPLICATIONS OF FPGA

From high-speed signal processing and I/O synchronization to custom triggering and
advanced control algorithms, field-programmable gate arrays (FPGAs) deliver the
functionality you need for the most demanding test, monitoring, and control
applications.
1. Precision control systems
FPGAs were used for developing feedback control of a single atom.
The challenge was to develop a custom time digitizer to study
fundamental quantum properties of light-matter interaction. This
problem was solved by using an FPGA module to build a powerful and
versatile custom instrument that allows us to implement real-time
execution of time-critical tasks in hardware. This makes it possible to
implement feedback control for systems as small as a single atom
interacting with single photons.
2. Embedded Monitoring
An FPGA based tachometer signal acquisition for vibration monitoring
applications was developed. The challenge was to develop a
tachometer signal acquisition module to seamlessly integrate into a
vibration monitoring system. Provide the flexibility to connect a
variety of sensor types in which signal frequency, amplitude, and DC
offset may vary substantially. Avoid the use of expensive signal
conditioning hardware while also minimizing processor loading during
intensive vibration analysis and display. Using an FPGA, a solution
was rapidly developed to address the requirements. The selfconfiguring

algorithm

automatically

identifies

input

signal

characteristics and provides reliable tachometer speed readings.

Customized hardware is not necessary, and no additional load is
introduced to the processor performing vibration analysis calculations.

3. Robotics and Autonomous Vehicles

A dynamic radiographic imaging control software was designed and
implemented on a Mitsubishi Robotic Manipulator. An already exiting
control system was replicated in order to decrease the amount of
equipment necessary to perform controls tasks, and achieve faster loop
times. FPGAs were used to replace real-time Linux, ANSI C++, and
single-purpose proprietary hardware to create an easy-to-use, highperformance control system for a robotic manipulator.

4. High-Speed Test
An FPGA-based hardware was used to dynamically evaluate an
electrical machine. The main aim was to measure the characteristics
and performance of an electrical machine running as a motor and
generator more efficiently. A dynamic synthetic loading technique
using an FPGA was implemented to test the motors and generators.

5. Monitoring Systems
FPGA based modules are being used to control rocket operation and
acquire, log, and publish temperature, pressure, and thrust data.
Analysis of the data received is also incorporated within the FPGA
module. At the same time, the vacuum chamber temperatures are also
closely and instantly monitored using the same module.

CHAPTER 4
CONCLUSION
Since their introduction in the 1985, field programmable gate arrays (FPGAs) have
become increasingly important to the electronics industry. They have the potential for
higher performance and lower power consumption than microprocessors and
compared with application specific integrated circuits (ASICs), offer lower nonrecurrent engineering (NRE) costs, reduced development time, easier debugging and
reduced risk. Since modern FPGAs can meet many of the performance requirements
of ASICs, they are being increasingly used in their place.

REFERENCES

a. A complete guide on FPGA. Avaliable from:

<http://fpgacenter.com/fpga/fpga_conf.php>. [26 January 2016]
b. National Instruments, FPGA Fundamentals, May 03, 2012
c. Altera Official Website. Available from: <https://www.altera.com/>.
[26 January 2016]
d. Xilinx Official Website. Available from: <http://www.xilinx.com/>.
[26 January 2016]