Professional Documents
Culture Documents
SynthWorks
SynthWorks
SynthWorks
SynthWorks
Testbench Architecture
O
Stim
Core
Stim
UartCmd
UART
UartCmd
System
Uart
Memio
Stim
CpuIf
UART
UartCmd
Uart
SynthWorks
Testbench Architecture
O
Model
Memio
CpuIf
UART
UartCmd
Uart
SynthWorks
Testbench Architecture
TbMemIO
TestCtrl
CPU
Model
Clock &
Reset
DUT: MemIO
CpuIf
MemIf
IntCtrl
UART
Timer
UartRx
Model
UartTx
Model
SRAM
Model
TestCtrl
Entity
Test1
Architecture
Test2
Architecture
...
TestN
Architecture
Plan to pre-use system level models for Core and RTL tests
6
SynthWorks
Transactions
O
O
O
Invalid
Data
Invalid
ADDR0
ADDR0
D1
Invalid
D1
Inv
nRdy
CpuWrite
CpuRead
Transaction Initiation
O
SynthWorks
Writing tests by wiggling signals is slow, error prone, and inhibits reuse
-- CPU Write
nAds <= '0' after tpd, '1' after tperiod + tpd ;
Addr <= ADDR0 after tpd ;
Data <= X"A5A5" after tperiod + tpd ;
Wr_nRd <= '0' after tpd ;
wait until nRdy = '0' and rising_edge(Clk) ;
SynthWorks
Transaction Implementation
O
Subprograms do both
O Transaction initiation by calling the subprogram
O Transaction implementation (signal wiggling) internal to subprogram
procedure CpuWrite (
signal
CpuRec : InOut
CpuRecType ;
constant AddrI : In
std_logic_vector;
constant DataI : In
std_logic_vector
) is
begin
CpuRec.nAds
<= '0' after tpd, '1' after tperiod + tpd ;
CpuRec.Addr
<= AddrI after tpd ;
CpuRec.Data
<= DataI after tperiod + tpd ;
CpuRec.Wr_nRd <= '1' after tpd ;
wait until CpuRec.nRdy = '0' and rising_edge(CpuRec.Clk);
end procedure ;
SynthWorks
Transaction Implementation
O
Entities +
O Transaction initiation by calling the subprogram
O Transaction implementation (signal wiggling) done by entity
TestCtrl
CpuTestProc
CpuModel
CpuRec
DUT
CpuBus
CpuWrite(...)
CpuRead(...)
10
SynthWorks
Transaction Interface
O
: unsigned(15 downto 0) ;
: unsigned(15 downto 0) ;
:
:
:
:
resolved
resolved
resolved
resolved
integer ;
integer ;
time ;
real ;
Writing Tests
11
SynthWorks
12
SynthWorks
Writing Tests
O
TestCtrl
TestCtrl
TestCtrl
CpuRec
CpuTestProc
CpuWrite(...)
CpuRead(...)
CPU Bus
UartTxBfm
Serial Data
to DUT
UartRxBfm
Serial Data
from DUT
UartTxRec
UartTbTxProc
UartSend(...)
UartTbRxProc
UartCheck(
CpuModel
UartRxRec
)
13
Writing Tests
SynthWorks
1414
SynthWorks
Key Benefits
O Works in any VHDL testbench
O Mixes well with other approaches (directed, algorithmic, file, random)
O Recommended to be use with transaction based testbenches
O Readable by All (in particular RTL engineers)
Why Randomize?
O
Randomization
O Is ideal for large variety of similar items
O Modes, processor instructions, network packets.
O Generates realistic stimulus in a timely fashion (to write)
O Is more thorough since stimulus is not ordered (not looping)
SynthWorks
16
SynthWorks
Randomization in OSVVM
O
SynthWorks
Randomization in OSVVM
O
-- Select sequence
when 0 =>
. . .
-- Normal Handling
-- Selected 70%
when 1 =>
. . .
-- Error Case 1
-- Selected 20%
when 2 =>
. . .
-- Error Case 2
-- Selected 10%
SynthWorks
Test Done =
O 100 % Functional Coverage + 100 % Code Coverage
19
SynthWorks
"I have written a directed test for each item in the test plan, I am done right?"
O For a small design maybe
O However, this assumes coverage, but does not verify it
20
SynthWorks
...
...
Mux
SRC1
... 8:1
SRC2
... 8:1
D7 Q7
Mux
S
R
C
1
R1 R2
SRC2
R3 R4 R5 R6
R7
R0
R1
R2
R3
R4
R5
R6
R7
21
SynthWorks
Coverage Object
CollectCov : process
variable RV : RandomPType ; -- randomization object
variable Src1, Src2 : integer ;
Create Cross
begin
Coverage Bins
ACov.AddCross( GenBin(0,7), GenBin(0,7) );
while not ACov.IsCovered loop
Src1 := RV.RandInt(0, 7) ;
Src2 := RV.RandInt(0, 7) ;
Covered = Done
Uniform
Randomization
Do Transaction
Collect Coverage
at Transaction
end loop ;
ACov.WriteBin ;
EndStatus(. . . ) ;
end process ;
22
SynthWorks
S
R
C
1
R0
R1
R2
R3
R4
R5
R6
R7
SRC2
R0 R1 R2 R3 R4 R5 R6 R7
5
6
6 9
1 4 6 6
3
4 3
6 9 5 5
4
3 2 3 4
6
4
1 5
5
5 6
3 3 4 4
6
4
5 5 10 9 10 7
7
4
6 3
6 3 5 3
8
3
6 3
4 7 1 4
6
7
3 4
6 6 5 4
5
"From Volume to Velocity" shows CR tests that are 10X to 100X too slow
SynthWorks
Intelligent Coverage
O
23
S
R
C
1
R0
R1
R2
R3
R4
R0
1
1
1
R1 R2
1
1
1
1
1
1
R3 R4 R5 R6
1
1
1
1
1
1
1
1
1
1
1
1
R7
1
1
1
R5
R6
R7
SynthWorks
Intelligent Coverage
Runs 64 iterations
@ 5X faster
Intelligent Coverage
Randomization
SynthWorks
SynthWorks
-- Normal Handling
-- 70%
when 1 =>
. . .
-- Error Case 1
-- 20%
when 2 =>
. . .
-- Error Case 2
-- 10%
Select sequence
Generates this
exact distribution
27
SynthWorks
GenBin(j));
GenBin(j));
28
SynthWorks
Coverage Closure
O
Intelligent Coverage
O Write FC.
O Only selects bins that are not covered in the FC
O Closure depends on running test long enough.
O Tests partitioned based on what coverage we want in this test.
Constrained Random
O Write CR. Write FC.
O Closure depends on CR driving inputs to FC.
O After simulation, analyze FC
O Prune out tests that are not increasing FC
O Tests partitioned based on modified controls, constraint sets, and seeds
O Must merge FC database for all tests
SynthWorks
Self-Checking
O
Self-Checking methods:
Embedding Data
Reference Model
DUT: MemIO
Check Process
CpuRead(CR, UD, X"4A")
30
SynthWorks
Stimulus
Generator
Output
Monitor
T
Scoreboard
Memory Modeling
O Large memories need space saving algorithm
O Data structure needs to be easy to use and help readabity
Synchronization Utilities
O Used to synchronize independent processes (threads) of code
Reporting Utilities
31
SynthWorks
32
Dispelling FUD
SynthWorks
SynthWorks
SystemVerilog?
O Less capable, slower, requires a specialist , alienates RTL engineers
35
SynthWorks
www.synthworks.com/blog/osvvm
OSVVM Website:
www.osvvm.org
36