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VDD
REFIN/OUT
AD7323
2.5V
VREF
VIN0
VIN1
VIN2
VIN3
I/P
MUX
T/H
DOUT
CS
VDRIVE
AGND
VSS
DGND
Figure 1.
1.
SCLK
DIN
PRODUCT HIGHLIGHTS
13-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL LOGIC
AND REGISTERS
CHANNEL
SEQUENCER
GENERAL DESCRIPTION
The AD7323 can accept true bipolar analog input signals. The
AD7323 has four software selectable input ranges, 10 V, 5 V,
2.5 V, and 0 V to +10 V. Each analog input channel can be
independently programmed to one of the four input ranges.
The analog input channels on the AD7323 can be programmed
to be single-ended, true differential, or pseudo differential.
VCC
05400-001
Data Sheet
2.
3.
4.
5.
Throughput
Rate
1000 kSPS
1000 kSPS
500 kSPS
1000 kSPS
1000 kSPS
500 kSPS
Number of bits
12-bit plus sign
12-bit plus sign
12-bit plus sign
12-bit plus sign
12-bit plus sign
12-bit plus sign
Number of
Channels
8
8
8
4
2
2
Rev. B
Document Feedback
AD7323
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Reference ..................................................................................... 28
Specifications..................................................................................... 3
VDRIVE ............................................................................................ 28
Terminology .................................................................................... 14
Registers ........................................................................................... 22
REVISION HISTORY
12/13Rev. A to Rev. B
Changes to Circuit Information Section and Table 6 ................ 16
Changes to Addressing Registers Section.................................... 22
Changes to Power Supply Configuration Section ...................... 34
1/10Rev. 0 to Rev. A
Changes to Features and General Description Sections.............. 1
Changes to Power Requirements, Normal Mode (Operational),
ICC and IDRIVE Parameter; and Power Dissipation, Normal Mode
(Operational) Parameter, Table 2 ................................................... 5
Changes to Endnote 1, Table 4 ........................................................ 8
Changes to Table 6, Figure 23, and Figure 24 ............................. 16
Changes to Figure 25, Figure 26, and Figure 29 ......................... 17
Rev. B | Page 2 of 36
Data Sheet
AD7323
SPECIFICATIONS
VDD = 12 V to 16.5 V, VSS = 12 V to 16.5 V, VCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V to 3.0 V internal/external,
fSCLK = 10 MHz, fS = 500 kSPS, TA = TMAX to TMIN, unless otherwise noted.
Table 2.
Parameter 1
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR) 2
Signal-to-Noise + Distortion
(SINAD)2
Min
B Version
Typ
Max
76
75.5
72.5
dB
dB
dB
72
dB
75
dB
74
76
dB
dB
dB
72.5
dB
72
80
dB
79
dB
dB
dB
dB
dB
82
77
79
80
Peak Harmonic or Spurious
Noise (SFDR)2
81
dB
80
dB
dB
dB
82
78
80
Intermodulation Distortion
(IMD)2
Second-Order Terms
Third-Order Terms
Aperture Delay 3
Aperture Jitter3
Common-Mode Rejection
(CMRR)2
Channel-to-Channel
Isolation2
Full Power Bandwidth
Unit
Test Conditions/Comments
fIN = 50 kHz sine wave
Differential mode, VCC = 4.75 V to 5.25 V
Differential mode, VCC < 4.75 V
Single-ended/pseudo differential mode; 10 V, 2.5 V and
5 V ranges, VCC = 4.75 V to 5.25 V
Single-ended/pseudo differential mode; 0 V to 10 V,
VCC = 4.75 V to 5.25 V and all ranges at VCC < 4.75 V
Differential mode; 2.5 V and 5 V ranges
Differential mode; 0 V to 10 V
Differential mode; 10 V range
Single-ended/pseudo differential mode; 2.5 V and 5 V
ranges
Single-ended/pseudo differential mode; 0 V to +10 V and
10 V ranges
Differential mode; 2.5 V and 5 V ranges
Differential mode; 0 V to 10 V ranges
Differential mode; 10 V range
Single-ended/pseudo differential mode; 5 V range
Single-ended/pseudo differential mode; 2.5 V range
Single-ended/pseudo differential mode; 0 V to +10 V and
10 V ranges
Differential mode; 2.5 V and 5 V ranges
Differential mode; 0 V to 10 V ranges
Differential mode; 10 V ranges
Single-ended/pseudo differential mode; 5 V range
Single-ended/pseudo differential mode; 2.5 V range
Single-ended/pseudo differential mode; 0 V to +10 V and
10 V ranges
fa = 50 kHz, fb = 30 kHz
79
dB
88
90
7
50
79
dB
dB
ns
ps
dB
72
dB
22
5
MHz
MHz
At 3 dB
At 0.1 dB
Rev. B | Page 3 of 36
AD7323
Parameter 1
DC ACCURACY
Data Sheet
Min
B Version
Typ
Max
Unit
Test Conditions/Comments
Single-ended/pseudo differential mode:
1 LSB = FSR/4096; unless otherwise noted
Differential mode: 1 LSB = FSR/8192;
unless otherwise noted
Resolution
No Missing Codes
13
12-bit plus
sign (13 bits)
11-bit plus
sign (12 bits)
1.1
1
Differential mode
Bits
LSB
LSB
0.9/+1.2
0.9
LSB
LSB
LSB
4/+9
7/+10
0.6
0.5
8
14
0.5
0.5
4
7
0.5
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
0.5
8.5
7.5
0.5
0.5
4
6
0.5
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
0.5
LSB
Differential mode
10
5
2.5
0 to 10
V
V
V
3.5
6
5
+3/5
V
V
V
V
nA
nA
Integral Nonlinearity2
0.7/+1.2
Differential Nonlinearity2
LSB
0.7/+1
Offset Error2, 4
Offset Error Match2, 4
Gain Error2, 4
Gain Error Match2, 4
Positive Full-Scale Error2, 5
Positive Full-Scale Error
Match2, 5
Bipolar Zero Error2, 5
Bipolar Zero Error Match2, 5
Negative Full-Scale Error2, 5
Negative Full-Scale Error
Match2, 5
ANALOG INPUT
Input Voltage Ranges
(Programmed via Range
Register)
Bits
Bits
Figure 41
DC Leakage Current
80
3
Rev. B | Page 4 of 36
Data Sheet
Parameter 1
Input Capacitance3
REFERENCE INPUT/OUTPUT
Input Voltage Range
Input DC Leakage Current
Input Capacitance
Reference Output Voltage
Reference Output Voltage
Error at 25C
Reference Output Voltage
TMIN to TMAX
Reference Temperature
Coefficient
Reference Output
Impedance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN3
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage
Current
Floating-State Output
Capacitance3
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition
Time2, 3
Throughput Rate
POWER REQUIREMENTS
VDD
VSS
VCC
VDRIVE
Normal Mode (Static)
Normal Mode (Operational)
IDD
ISS
ICC and IDRIVE
Autostandby Mode
(Dynamic)
IDD
ISS
ICC and IDRIVE
AD7323
B Version
Typ
13.5
16.5
21.5
3
Min
2.5
Max
Unit
pF
pF
pF
pF
3
1
V
A
pF
V
mV
10
mV
25
ppm/C
10
2.5
3
7
2.4
0.8
0.4
1
10
VDRIVE 0.2 V
0.4
1
5
V
V
V
A
pF
V
V
A
ISOURCE = 200 A
ISINK = 200 A
pF
12
12
2.7
2.7
Test Conditions/Comments
When in track, 10 V range
When in track, 5 V and 0 V to +10 V ranges
When in track, 2.5 V range
When in hold, all ranges
1.6
305
s
ns
500
kSPS
16.5
16.5
5.25
5.25
V
V
V
V
mA
0.9
180
205
2.2
A
A
mA
100
110
0.75
A
A
mA
Rev. B | Page 5 of 36
AD7323
Parameter 1
Autoshutdown Mode (Static)
IDD
ISS
ICC and IDRIVE
Full Shutdown Mode
IDD
ISS
ICC and IDRIVE
POWER DISSIPATION
Normal Mode (Operational)
Full Shutdown Mode
Data Sheet
Min
B Version
Typ
Max
Unit
1
1
1
A
A
A
1
1
1
A
A
A
Test Conditions/Comments
SCLK on or off
VDD = 16.5 V
VSS = 16.5 V
VCC/VDRIVE = 5.25 V
SCLK on or off
VDD = 16.5 V
VSS = 16.5 V
VCC/VDRIVE = 5.25 V
18
38.25
mW
W
Rev. B | Page 6 of 36
Data Sheet
AD7323
TIMING SPECIFICATIONS
VDD = 12 V to 16.5 V, VSS = 12 V to 16.5 V, VCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VDRIVE VCC, VREF = 2.5 V to 3.0 V
internal/external, TA = TMAX to TMIN. Timing specifications apply with a 32 pF load, unless otherwise noted. 1
Table 3.
Parameter
fSCLK
tCONVERT
tQUIET
t1
t2 2
t3
t4
t5
t6
t7
t8
t9
t10
tPOWER-UP
Unit
kHz min
MHz max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns max
s max
s typ
Description
tSCLK = 1/fSCLK
Minimum time between end of serial read and next falling edge of CS
Minimum CS pulse width
CS to SCLK set-up time; bipolar input ranges (10 V, 5 V, 2.5 V)
Unipolar input range (0 V to 10 V)
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to DOUT high impedance
SCLK falling edge to DOUT high impedance
DIN set-up time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Power-up from autostandby
Power-up from full shutdown/autoshutdown mode, internal reference
Power-up from full shutdown/autoshutdown mode, external reference
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
When using the 0 V to 10 V unipolar range, running at 500 kSPS throughput rate with t2 at 20 ns, the mark space ratio must be limited to 50:50.
t1
CS
tCONVERT
t2
SCLK
t6
1
2 IDENTIFICATION BITS
t3
ADD1
DOUT
THREE- ZERO
t9
STATE
DIN
WRITE
REG
SEL1
ADD0
SIGN
t4
13
14
DB11
15
16
t5
t7
DB10
DB2
t8
DB1
t10
REG
SEL2
tQUIET
DB0
THREE-STATE
MSB
LSB
Rev. B | Page 7 of 36
DONT
CARE
05400-002
AD7323
Data Sheet
Rating
0.3 V to +16.5 V
+0.3 V to 16.5 V
VCC 0.3 V to 16.5 V
0.3 V to +7 V
0.3 V to +7 V
0.3 V to +0.3 V
VSS 0.3 V to VDD + 0.3 V
0.3 V to +7 V
0.3 V to VDRIVE + 0.3 V
0.3 V to VCC + 0.3 V
10 mA
ESD CAUTION
40C to +85C
65C to +150C
150C
150C/W
27.6C/W
260(0)C
2.5 kV
If the analog inputs are driven from alternative VDD and VSS supply circuitry,
Schottky diodes should be placed in series with the AD7323s VDD and VSS
supplies. See the Power Supply Configuration section.
2
Transient currents of up to 100 mA do not cause SCR latch-up.
1
Rev. B | Page 8 of 36
Data Sheet
AD7323
16
DIN 2
15
DGND
14
DOUT
AD7323
AGND
TOP VIEW
(Not to Scale)
REFIN/OUT 5
VSS
13
VDRIVE
12
VCC
11
VDD
VIN0 7
10
VIN2
VIN1 8
VIN3
05400-003
DGND
SCLK
Mnemonic
CS
DIN
3, 15
DGND
AGND
REFIN/OUT
6
7, 8, 9, 10
VSS
VIN0 to VIN3
11
12
VDD
VCC
13
VDRIVE
14
DOUT
16
SCLK
Description
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7323 and frames the serial data transfer.
Data Input. Data to be written to the on-chip registers is provided on this input and is clocked into the
register on the falling edge of SCLK (see the Registers section).
Digital Ground. Ground reference point for all digital circuitry on the AD7323. The DGND and AGND
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
Analog Ground. Ground reference point for all analog circuitry on the AD7323. All analog input signals
and any external reference signal should be referred to this AGND voltage. The AGND and DGND
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
Reference Input/Reference Output. The on-chip reference is available on this pin for use external to the
AD7323. The nominal internal reference voltage is 2.5 V, which appears at this pin. A 680 nF capacitor
should be placed on the reference pin (see the Reference section). Alternatively, the internal reference
can be disabled and an external reference applied to this input. On power-up, the external reference
mode is the default condition.
Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.
Analog Input 0 to Analog Input 3. The analog inputs are multiplexed into the on-chip track-and-hold.
The analog input channel for conversion is selected by programming the ADD1 and ADD0 channel
address bits in the control register. The inputs can be configured as four single-ended inputs, two true
differential input pairs, two pseudo differential inputs, or three pseudo differential inputs (see Table 10).
The configuration of the analog inputs is selected by programming the mode bits, Mode 1 and Mode 0,
in the control register. The input range on each input channel is controlled by programming the range
register. Input ranges of 10 V, 5 V, 2.5 V, and 0 V to +10 V can be selected on each analog input
channel when a 2.5 V reference voltage is used (see the Registers section).
Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.
Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7323.
This supply should be decoupled to AGND.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
operates. This pin should be decoupled to DGND. The voltage at this pin may be different from that at
VCC, but it should not exceed VCC by more than 0.3 V.
Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits
are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data.
The data stream consists of a leading zero, two channel identification bits, the sign bit, and 12 bits of
conversion data. The data is provided MSB first (see the Serial Interface section).
Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the
AD7323. This clock is also used as the clock source for the conversion process.
Rev. B | Page 9 of 36
AD7323
Data Sheet
1.0
SNR (dB)
40
60
80
0.8
0.6
0.4
20
0.2
0
0.2
0.4
100
0.6
120
50
100
150
200
250
FREQUENCY (kHz)
05400-004
1.0
1024
2048
3072
4096
5120
6144
7168
8192
512
1536
2560
3584
4608
5632
6656
7680
CODE
05400-007
0.8
140
0
4096 POINT FFT
VCC = VDRIVE = 5V
VDD, VSS = 15V
TA = 25C
INT/EXT 2.5V REFERENCE
10V RANGE
fIN = 50kHz
SNR = 74.67dB
SINAD = 74.03dB
THD = 82.68dB
SFDR = 85.40dB
SNR (dB)
40
60
80
0.8
0.6
20
0.4
0.2
0
0.2
0.4
0.8
120
50
100
150
200
250
FREQUENCY (kHz)
05400-005
1.0
140
7168
6144
1024
2048
3072
4096
5120
8192
4608
5632
6656
7680
2560
3584
512
1536
CODE
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0
0.2
VCC = VDRIVE = 5V
TA = 25C
VDD, VSS = 15V
INT/EXT 2.5V REFERENCE
10V RANGE
+DNL = +0.72LSB
DNL = 0.22LSB
0.6
0.8
0
1024
2048
3072
4096
5120
6144
7168
8192
512
1536
2560
3584
4608
5632
6656
7680
CODE
0.2
0
0.2
VCC = VDRIVE = 5V
TA = 25C
VDD, VSS = 15V
0.6
INT/EXT 2.5V REFERENCE
10V RANGE
0.8
+INL = +0.87LSB
INL = 0.49LSB
1.0
0
1024
2048
3072
4096
5120
6144
7168
8192
512
1536
2560
3584
4608
5632
6656
7680
CODE
0.4
Rev. B | Page 10 of 36
05400-044
0.4
05400-006
1.0
10V RANGE
VCC = VDRIVE = 5V
+DNL = +0.79LSB
TA = 25C
DNL = 0.38LSB
VDD, VSS = 15V
INT/EXT 2.5V REFERENCE
0.6
05400-043
100
Data Sheet
AD7323
50
75
2.5V SE
65
70
10V DIFF
75
0V TO +10V DIFF
80
5V SE
10V SE
65
0V TO +10V SE
60
5V DIFF
85
10V DIFF
2.5V DIFF
90
2.5V SE
100
1000
50
10
05400-060
100
10
Figure 10. THD vs. Analog Input Frequency for Single-Ended (SE) and True
Differential Mode (Diff) at 3 V VCC
50
VCC = VDRIVE = 5V
VDD/VSS = 12V
TA = 25C
fS = 500kSPS
INTERNAL REFERENCE
0V TO +10V SE
THD (dB)
65
10V SE
70
10V DIFF
75
0V TO +10V DIFF
80
5V SE
85
5V DIFF
90
2.5V SE
95
55
VCC = 3V
60
VCC = 5V
65
70
75
80
VDD/VSS = 12V
SINGLE-ENDED MODE
fS = 500kSPS
TA = 25C
50kHz ON SELECTED CHANNEL
85
90
2.5V DIFF
100
1000
95
05400-061
100
10
200
0V TO +10V DIFF
70
10V DIFF
10V SE
65
0V TO +10V SE
60
VCC = VDRIVE = 3V
VDD/VSS = 12V
TA = 25C
fS = 500kSPS
INTERNAL REFERENCE
100
ANALOG INPUT FREQUENCY (kHz)
1000
8k
Rev. B | Page 11 of 36
600
VCC = 5V
VDD/VSS = 12V
RANGE = 10V
10k SAMPLES
TA = 25C
6k
5k
4k
3k
2k
Figure 12.SINAD vs. Analog Input Frequency for Single-Ended (SE) and True
Differential Mode (Diff) at 3 V VCC
500
7k
1k
05400-062
55
9469
9k
NUMBER OF OCCURRENCES
75
400
5V DIFF
2.5V DIFF
5V SE
2.5V SE
300
80
SINAD (dB)
100
Figure 11. THD vs. Analog Input Frequency for Single-Ended (SE) and True
Differential Mode (Diff) at 5 V VCC
50
10
1000
Figure 13. SINAD vs. Analog Input Frequency for Single-Ended (SE) and True
Differential Mode (Diff) at 5 V VCC
60
100
ANALOG INPUT FREQUENCY (kHz)
50
55
VCC = VDRIVE = 5V
VDD/VSS = 12V
TA = 25C
fS = 500kSPS
INTERNAL REFERENCE
55
95
0V TO +10V DIFF
05400-063
70
SINAD (dB)
10V SE
THD (dB)
5V SE
0V TO +10V SE
05400-012
60
5V DIFF
2.5V DIFF
228
303
0
2
CODE
05400-013
55
80
VCC = VDRIVE = 3V
VDD/VSS = 12V
TA = 25C
fS = 500kSPS
INTERNAL REFERENCE
AD7323
Data Sheet
8k
7600
7k
6k
1.5
1.0
5k
4k
3k
0.5
INL = 500kSPS
0
0.5
1.0
1201
5V RANGE
VCC = VDRIVE = 5V
INTERNAL REFERENCE
SINGLE-ENDED MODE
1165
1.5
1k
0
23
11
2.0
05400-014
CODE
13
15
17
19
50
55
55
60
60
65
65
PSRR (dB)
VCC = 5V
75
80
VCC = 3V
85
DIFFERENTIAL MODE
fIN = 50kHz
VDD/VSS = 12V
fS = 500kSPS
TA = 25C
95
0
200
400
600
800
1000
VCC = 5V
VCC = 3V
70
75
VDD = 12V
80
85
VSS = 12V
90
95
1200
100
05400-055
90
400
600
800
1.5
55
60
1.0
65
THD (dB)
0.5
DNL = 500kSPS
0
0.5
VCC = VDRIVE = 5V
VDD/VSS = 12V
TA = 25C
INTERNAL REF
RANGE = 10V AND 2.5V
fS = 500kSPS
DIFFERENTIAL MODE
10V RANGE
RIN = 4000
RIN = 3000
RIN = 2000
RIN = 1000
RIN = 100
RIN = 12
70
75
2.5V RANGE
RIN = 9000
RIN = 5500
RIN = 2000
RIN = 100
RIN = 12
80
85
1.0
5V RANGE
VCC = VDRIVE = 5V
INTERNAL REFERENCE
SINGLE-ENDED MODE
7
90
95
11
13
15
17
19
100
10
05400-049
1200
Figure 20. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
50
1.5
1000
2.0
2.0
200
05400-054
70
CMRR (dB)
11
50
100
05400-050
2k
100
INPUT FREQUENCY (kHz)
1000
05400-064
NUMBER OF OCCURRENCES
2.0
VCC = 5V
VDD/VSS = 12V
RANGE = 10V
10k SAMPLES
TA = 25C
Figure 21. THD vs. Analog Input Frequency for Various Source Impedances,
True Differential Mode
Rev. B | Page 12 of 36
Data Sheet
AD7323
50
THD (dB)
10V RANGE
RIN = 4000
RIN = 2000
RIN = 1000
RIN = 100
RIN = 50
70
75
2.5V RANGE
RIN = 4700
RIN = 3000
RIN = 1000
RIN = 100
RIN = 50
80
85
90
100
INPUT FREQUENCY (kHz)
1000
05400-065
95
100
10
Figure 22. THD vs. Analog Input Frequency for Various Source Impedances,
Single-Ended Mode
Rev. B | Page 13 of 36
AD7323
Data Sheet
TERMINOLOGY
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale (a point 1 LSB
below the first code transition) and full scale (a point 1 LSB
above the last code transition).
Offset Code Error
This applies to straight binary output coding. It is the deviation
of the first code transition (00000) to (00001) from the
ideal, that is, AGND + 1 LSB.
Offset Error Match
This is the difference in offset error between any two input
channels.
Gain Error
This applies to straight binary output coding. It is the deviation
of the last code transition (111110) to (111111) from the
ideal (that is, 4 VREF 1 LSB, 2 VREF 1 LSB, VREF 1 LSB)
after adjusting for the offset error.
Gain Error Match
This is the difference in gain error between any two input
channels.
Bipolar Zero Code Error
This applies when using twos complement output coding and a
bipolar analog input. It is the deviation of the midscale transition (all 1s to all 0s) from the ideal input voltage, that is, AGND
1 LSB.
V2 2 + V3 2 + V 4 2 + V5 2 + V6 2
V1
Rev. B | Page 14 of 36
Data Sheet
AD7323
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between any two channels. It is measured by applying a
full-scale, 100 kHz sine wave signal to all unselected input channels
and determining the degree to which the signal attenuates in the
selected channel with a 50 kHz signal. Figure 14 shows the worstcase across all eight channels for the AD7323. The analog input
range is programmed to be the same on all channels.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa nfb, where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n are equal to 0. For example,
the second-order terms include (fa + fb) and (fa fb), whereas
the third-order terms include (2fa + fb), (2fa fb), (fa + 2fb),
and (fa 2fb).
The AD7323 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves, whereas the third-order
Rev. B | Page 15 of 36
AD7323
Data Sheet
THEORY OF OPERATION
The AD7323 requires VDD and VSS dual supplies for the high voltage
analog input structures. These supplies must be equal to or greater
than the largest analog input range selected. See Table 6 for the
requirements of these supplies for each analog input range. The
AD7323 requires a low voltage 2.7 V to 5.25 V VCC supply to
power the ADC core.
Table 6. Reference and Supply Requirements for Each
Analog Input Range
Selected
Analog Input
Range (V)
10
5
2.5
0 to +10
1
Reference
Voltage (V)
2.5
3.0
2.5
3.0
2.5
3.0
2.5
3.0
Full-Scale
Input
Range (V)
10
12
5
6
2.5
3
0 to +10
0 to +12
VCC (V)
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
Minimum
VDD/VSS (V)1
10
12
5
6
5
5
+10/AGND
+12/AGND
CONVERTER OPERATION
The AD7323 is a successive approximation ADC built around
two capacitive DACs. Figure 23 and Figure 24 show simplified
schematics of the ADC in single-ended mode during the acquisition and conversion phases, respectively. Figure 25 and Figure 26
show simplified schematics of the ADC in differential mode
during acquisition and conversion phases, respectively. The
ADC is composed of control logic, a SAR, and capacitive DACs.
In Figure 23 (the acquisition phase), SW2 is closed and SW1 is
in Position A, the comparator is held in a balanced condition,
and the sampling capacitor array acquires the signal on the input.
CAPACITIVE
DAC
B
VINx
COMPARATOR
CS
A SW1
CONTROL
LOGIC
SW2
AGND
05400-017
When the ADC starts a conversion (see Figure 24), SW2 opens
and SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and the charge redistribution
DAC are used to add and subtract fixed amounts of charge from
the capacitive DAC to bring the comparator back into a balanced
condition. When the comparator is rebalanced, the conversion
is complete. The control logic generates the ADC output code.
CAPACITIVE
DAC
B
VINx
COMPARATOR
CS
A SW1
SW2
CONTROL
LOGIC
AGND
05400-018
CIRCUIT INFORMATION
Data Sheet
AD7323
CS
VREF
100...010
100...001
100...000
CAPACITIVE
DAC
NOTES
1. VIN+ CAN BE VIN0 OR VIN2, AND VIN CAN BE VIN1 OR VIN3.
FSR/2 + 1LSB
AGND + 1LSB
CAPACITIVE
DAC
A SW1
A SW2
B
SW3
ADC CODE
CONTROL
LOGIC
CS
VREF
FSR/2 + 1LSB
+FSR/2 1LSB BIPOLAR RANGES
AGND + 1LSB
+FSR 1LSB
UNIPOLAR RANGE
ANALOG INPUT
Output Coding
Transfer Functions
The designed code transitions occur at successive integer
LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is
dependent on the analog input range selected.
011...111
000...010
000...001
000...000
05400-020
CAPACITIVE
DAC
NOTES
1. VIN+ CAN BE VIN0 OR VIN2, AND VIN CAN BE VIN1 OR VIN3.
111...000
LSB Size
2.441 mV
1.22 mV
0.61 mV
1.22 mV
VDD
D
VINx
C1
D
VSS
R1
C2
05400-023
VIN
111...111
111...110
COMPARATOR
CS
VIN+
AGND 1LSB
05400-021
CONTROL
LOGIC
SW3
000...001
000...000
111...111
05400-022
A SW1
A SW2
05400-019
VIN
COMPARATOR
CS
B
VIN+
011...111
011...110
ADC CODE
CAPACITIVE
DAC
Rev. B | Page 17 of 36
AD7323
Data Sheet
VDD
VIN+
C1
R1
The AD7323 enters track mode on the 14th SCLK rising edge.
When running the AD7323 at a throughput rate of 1 MSPS with
a 10 MHz SCLK signal, the ADC has approximately
C2
VSS
to acquire the analog input signal. The ADC goes back into
hold mode on the CS falling edge.
D
VIN
C2
VSS
NOTES
1. VIN+ CAN BE VIN0 OR VIN2, AND VIN CAN BE VIN1 OR VIN3.
05400-024
C1
R1
Care should be taken to ensure that the analog input does not
exceed the VDD and VSS supply rails by more than 300 mV. Exceeding this value causes the diodes to become forward biased and
to start conducting into either the VDD supply rail or VSS supply
rail. These diodes can conduct up to 10 mA without causing
irreversible damage to the part.
In Figure 29 and Figure 30, Capacitor C1 is typically 4 pF and
can primarily be attributed to pin capacitance. Resistor R1 is a
lumped component made up of the on resistance of the input
multiplexer and the track-and-hold switch. Capacitor C2 is the
sampling capacitor; its capacitance varies depending on the
analog input range selected (see the Specifications section).
VCC = VDRIVE = 5V
INTERNAL REFERENCE
TA = 25C
fIN = 10kHz
5V RANGE
SE MODE
80
THD (dB)
VDD
85
90
500kSPS
Track-and-Hold Section
The track-and-hold on the analog input of the AD7323 allows
the ADC to accurately convert an input sine wave of full-scale
amplitude to 13-bit accuracy. The input bandwidth of the trackand-hold is greater than the Nyquist rate of the ADC. The
AD7323 can handle frequencies up to 22 MHz.
The track-and-hold enters its tracking mode on the 14 SCLK
rising edge after the CS falling edge. The time required to
acquire an input signal depends on how quickly the sampling
capacitor is charged. With zero source impedance, 305 ns is
sufficient to acquire the signal to the 13-bit level. The
acquisition time required is calculated using the following
formula:
th
tACQ = 10 ((RSOURCE + R) C)
where C is the sampling capacitance and R is the resistance seen
by the track-and-hold amplifier looking back on the input. For
the AD7323, the value of R includes the on resistance of the
input multiplexer and is typically 300 . RSOURCE should include
any extra source impedance on the analog input.
95
5
11
13
15
17
19
05400-051
Rev. B | Page 18 of 36
Data Sheet
AD7323
V+
VDD1
VINx
V
1ADDITIONAL
AD73231
VIN
+3V SUPPLY
10F +
NOTES
1. VIN+ CAN BE VIN0 OR VIN2, AND VIN CAN BE VIN1 OR VIN3.
0.1F
AD7323
1ADDITIONAL
CS
VIN0
VIN1
VIN2
VIN3
DOUT
C/P
DIN
DGND
VSS1
SERIAL
INTERFACE
AGND
15V
10F
1MINIMUM V
DD AND V SS SUPPLY VOLTAGES
05400-025
0.1F
SCLK
REFIN/OUT
680nF
05400-026
VSS
0.1F
VCC
VDRIVE
ANALOG INPUTS
10V, 5V, 2.5V
0V TO +10V
VDD VCC
AD73231
05400-027
10F
0.1F
AGND
5V
ANALOG INPUT
(VIN+ + VIN)/2
Single-Ended Inputs
The AD7323 has a total of four analog inputs when operating
the AD7323 in single-ended mode. Each analog input can be
independently programmed to one of the four analog input
ranges. In applications where the signal source is high
impedance, it is recommended to buffer the signal before
applying it to the ADC analog inputs. Figure 33 shows the
configuration of the AD7323 in single-ended mode.
and is therefore the voltage on which the two input signals are
centered.
This voltage is set up externally, and its range varies with
reference voltage. As the reference voltage increases, the
common-mode range decreases. When driving the differential
inputs with an amplifier, the actual common-mode range is
determined by the amplifiers output swing. If the differential
inputs are not driven from an amplifier, the common-mode
range is determined by the supply voltage on the VDD supply pin
and the VSS supply pin.
Rev. B | Page 19 of 36
AD7323
Data Sheet
8
5V RANGE
2.5V
RANGE
6
10V
RANGE
10V
RANGE
2.5V
RANGE
5V RANGE
2.5V
RANGE
VCC = 5V
VREF = 2.5V
12V VDD/VSS
16.5V VDD/VSS
10V
RANGE
05400-048
5V RANGE
5V RANGE
2.5V
RANGE
5
4
10V
RANGE
VCC = 3V
VREF = 3V
05400-045
5
6
16.5V VDD/VSS
12V VDD/VSS
5V RANGE
2.5V
RANGE
2.5V
RANGE
10V
RANGE
2
10V
RANGE
2
VCC = 5V
VREF = 3V
16.5V VDD/VSS
V+
05400-046
4
12V VDD/VSS
5V
VIN+
VDD VCC
AD73231
VIN
4
5V RANGE
VSS
5V RANGE
10V
RANGE
10V
2.5V
RANGE RANGE
VCC = 3V
VREF = 2.5V
8
16.5V VDD/VSS
12V VDD/VSS
2.5V
RANGE
05400-028
V
NOTES
1. VIN+ CAN BE VIN0, VIN1, OR VIN2, AND VIN CAN BE VIN1
OR VIN3.
05400-047
Rev. B | Page 20 of 36
Data Sheet
AD7323
2.5V
RANGE
2
0
2
10V
RANGE
4
6
8
0V TO +10V
RANGE
VCC = 5V
VREF = 2.5V
12V VDD/VSS
16.5V VDD/VSS
Differential operation requires that VIN+ and VIN be simultaneously driven with two signals of equal amplitude that are 180
out of phase. The common mode must be set up externally to the
AD7323. The common-mode range is determined by the REFIN/
OUT voltage, the VCC supply voltage, and the particular amplifier
used to drive the analog inputs. Differential mode with either an
ac input or a dc input provides the best THD performance over a
wide frequency range. Because not all applications have a signal
preconditioned for differential operation, there is often a need to
perform the single-ended-to-differential conversion.
0V TO +10V
RANGE
2.5V
RANGE
2
10V
RANGE
4
10V
RANGE
2.5V
RANGE
0V TO +10V
RANGE
0V TO +10V
RANGE
VCC = 3V
VREF = 2.5V
1.5k
8
16.5V VDD/VSS
12V VDD/VSS
05400-040
5V RANGE
5V RANGE
3k
AD845
VIN
V+
1.5k
1.5k
In applications where the harmonic distortion and signal-tonoise ratio are critical specifications, the analog input of the
AD7323 should be driven from a low impedance source. Large
source impedances significantly affect the ac performance of the
ADC and can necessitate the use of an input buffer amplifier.
1.5k
V
10k
VCOM
05400-029
AD845
20k
VIN
442
AD8021
V+
442
442
442
442
AD8021
100
05400-030
5V RANGE
5V RANGE
2.5V
RANGE
10V
RANGE
05400-039
Rev. B | Page 21 of 36
AD7323
Data Sheet
REGISTERS
The AD7323 has three programmable registers: the control
register, sequence register, and range register. These registers
are write-only registers.
ADDRESSING REGISTERS
A serial transfer on the AD7323 consists of 16 SCLK cycles. The
three MSBs on the DIN line during the 16 SCLK transfer are
decoded to determine which register is addressed. The three
MSBs consist of the write bit, the Register Select 1 bit, and the
Register Select 2 bit. The register select bits are used to
determine which of the three on-board registers is selected. The
write bit determines if the data on the DIN line following the
register select bits loads into the addressed register. If the write
bit is 1, the bits load into the register addressed by the register
select bits. If the write bit is 0, the data on the DIN line does not
load into any register.
Combinations of the write bit, the Register Select 1 bit, and the
Register Select 2 bit other than those specified in Table 8 access
registers for Analog Devices internal use only. Accessing these
registers may lead to unspecified operation of the device.
Register Select 1
0
0
Register Select 2
0
0
Description
Data on the DIN line during this serial transfer is ignored.
This combination selects the control register. The subsequent 12 bits are loaded into
the control register.
This combination selects the range register. The subsequent eight bits are loaded into
the range register.
This combination selects the sequence register. The subsequent four bits are loaded
into the sequence register.
Rev. B | Page 22 of 36
Data Sheet
AD7323
CONTROL REGISTER
register and the sequence register have been initialized. The bit
functions of the control register are shown in Table 9 (the powerup status of all bits is 0).
MSB
15
Write
14
Register Select 1
13
Register Select 2
12
Zero
11
ADD1
10
ADD0
The four analog input channels can be configured as four singleended analog inputs, two true differential input pairs, two
pseudo differential inputs, or three pseudo differential inputs.
9
Mode 1
8
Mode 0
7
PM1
6
PM0
5
Coding
4
Ref
3
Seq1
2
Seq2
1
Zero
LSB
0
0
Mnemonic
Zero
ADD1, ADD0
9, 8
Mode 1, Mode 0
7, 6
5
PM1, PM0
Coding
Ref
3, 2
Seq1, Seq2
Description
A 0 should be written to these bits.
These two channel address bits are used to select the analog input channel for the next conversion if the
sequencer is not being used. If the sequencer is being used, the two channel address bits are used to
select the final channel in a consecutive sequence.
These two mode bits are used to select the configuration of the four analog input pins, VIN0 to VIN3. These
pins are used in conjunction with the channel address bits. On the AD7323, the analog inputs can be
configured as four single-ended inputs, two true differential input pairs, two pseudo differential inputs, or
three pseudo differential inputs (see Table 10).
The power management bits are used to select different power mode options on the AD7323 (see Table 11).
This bit is used to select the type of output coding the AD7323 uses for the next conversion result. If
coding = 0, the output coding is twos complement. If coding = 1, the output coding is straight binary.
When operating in sequence mode, the output coding for each channel is the value written to the coding
bit during the last write to the control register.
The reference bit is used to enable or disable the internal reference. If Ref = 0, the external reference is
enabled and used for the next conversion, and the internal reference is disabled. If Ref = 1, the internal
reference is used for the next conversion. When operating in sequence mode, the reference used for each
channel is the value written to the Ref bit during the last write to the control register.
The Sequence 1 and Sequence 2 bits are used to control the operation of the sequencer (see Table 12).
Mode 1 = 1, Mode 0 = 1
3 Pseudo Differential Inputs
VIN+
VIN
VIN0
VIN3
VIN1
VIN3
VIN2
VIN3
Not allowed
Mode 1 = 1, Mode 0 = 0
2 Fully Differential Inputs
VIN+
VIN
VIN0
VIN1
VIN0
VIN1
VIN2
VIN3
VIN2
VIN3
Rev. B | Page 23 of 36
Mode 1 = 0, Mode 0 = 1
2 Pseudo Differential Inputs
VIN+
VIN
VIN0
VIN1
VIN0
VIN1
VIN2
VIN3
VIN2
VIN3
Mode 1 = 0, Mode 0 = 0
4 Single-Ended Inputs
VIN+
VIN
VIN0
AGND
VIN1
AGND
VIN2
AGND
VIN3
AGND
AD7323
Data Sheet
PM0
1
Description
Full shutdown mode. In this mode, all internal circuitry on the AD7323 is powered down. Information in the control register
is retained when the AD7323 is in full shutdown mode.
Autoshutdown mode. The AD7323 enters autoshutdown on the 15th SCLK rising edge when the control register is updated.
All internal circuitry is powered down in autoshutdown.
Autostandby mode. In this mode, all internal circuitry is powered down, excluding the internal reference. The AD7323 enters
autostandby mode on the 15th SCLK rising edge after the control register is updated.
Normal mode. All internal circuitry is powered up at all times.
Seq2
0
Description
The channel sequencer is not used. The analog channel, selected by programming the ADD1 bit and ADD0 bit in the
control register, selects the next channel for conversion.
Uses the sequence of channels previously programmed into the sequence register for conversion. The AD7323 starts
converting on the lowest channel in the sequence. The channels are converted in ascending order. If uninterrupted, the
AD7323 keeps converting the sequence. The range for each channel defaults to the range previously written into the range
register.
Used in conjunction with the channel address bits in the control register. This allows continuous conversions on a
consecutive sequence of channels, from Channel 0 through a final channel selected by the channel address bits in the
control register. The range for each channel defaults to the range previously written into the range register.
The channel sequencer is not used. The analog channel, selected by programming the ADD1 bit and ADD0 bit in the
control register, selects the next channel for conversion.
Rev. B | Page 24 of 36
Data Sheet
AD7323
dedicated range bits for each of the analog input channels from
Channel 0 to Channel 3. There are four analog input ranges,
10 V, 5 V, 2.5 V, and 0 V to +10 V. A write to the range
register is selected by setting the write bit to 1 and the register
select bits to 0 and 1. After the initial write to the range register
occurs, each time an analog input is selected, the AD7323
automatically configures the analog input to the appropriate
range, as indicated by the range register. The 10 V input range
is selected by default on each analog input channel (see Table 13).
SEQUENCE REGISTER
The sequence register on the AD7323 is a 4-bit, write-only register.
Each of the four analog input channels has one corresponding
bit in the sequence register. To select a channel for inclusion in
the sequence, set the corresponding channel bit to 1 in the
sequence register.
RANGE REGISTER
The range register is used to select one analog input range per
analog input channel. It is an 8-bit, write-only register with two
MSB
16
Write
15
Register Select 1
MSB
16
Write
15
Register Select 1
14
Register Select 2
14
Register Select 2
13
VIN0
13
VIN0A
12
VIN1
12
VIN0B
11
VIN2
10
VIN3
11
VIN1A
10
VIN1B
9
0
8
0
7
0
9
VIN2A
8
VIN2B
7
VIN3A
VINxB
0
1
0
1
Description
This combination selects the 10 V input range on VINx.
This combination selects the 5 V input range on VINx.
This combination selects the 2.5 V input range on VINx.
This combination selects the 0 V to +10 V input range on VINx.
Rev. B | Page 25 of 36
6
0
6
VIN3B
5
0
5
0
4
0
4
0
3
0
3
0
2
0
LSB
1
0
2
0
LSB
1
0
AD7323
Data Sheet
SEQUENCER OPERATION
The AD7323 can be configured to automatically cycle through
a number of selected channels using the on-chip sequence
register with the Seq1 bit and the Seq2 bit in the control register.
Figure 44 shows how to program the AD7323 register to
operate in sequence mode.
After power-up, all of the three on-chip registers contain default
values. Each analog input has a default input range of 10 V. If
different analog input ranges are required, a write to the range
register is required. This is shown in the first serial transfer of
Figure 44.
POWER ON.
CS
STOPPING
A SEQUENCE.
CONTINUOUSLY CONVERT
ON THE SELECTED SEQUENCE
OF CHANNELS.
05400-031
Rev. B | Page 26 of 36
Data Sheet
AD7323
POWER ON.
CS
STOPPING
A SEQUENCE.
CONTINUOUSLY CONVERT
ON CONSECUTIVE SEQUENCE
OF CHANNELS.
CS
Rev. B | Page 27 of 36
05400-032
AD7323
Data Sheet
REFERENCE
The AD7323 can operate with either the internal 2.5 V on-chip
reference or an externally applied reference. The internal
reference is selected by setting the Ref bit in the control register
to 1. On power-up, the Ref bit is 0, which selects the external
reference for the AD7323 conversion. Suitable reference sources
for the AD7323 include AD780, AD1582, ADR431, REF193,
and ADR391.
The internal reference circuitry consists of a 2.5 V band gap
reference and a reference buffer. When operating the AD7323
in internal reference mode, the 2.5 V internal reference is available
at the REFIN/OUT pin, which should be decoupled to AGND
using a 680 nF capacitor. It is recommended that the internal
reference be buffered before applying it elsewhere in the system.
The internal reference is capable of sourcing up to 90 A.
VDRIVE
The AD7323 has a VDRIVE feature to control the voltage at which
the serial interface operates. VDRIVE allows the ADC to easily
interface to both 3 V and 5 V processors. For example, if the
AD7323 is operated with a VCC of 5 V, the VDRIVE pin can be
powered from a 3 V supply. This allows the AD7323 to accept
large bipolar input signals with low voltage digital processing.
Rev. B | Page 28 of 36
Data Sheet
AD7323
MODES OF OPERATION
The AD7323 has several modes of operation that are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for different application requirements. The mode of
operation of the AD7323 is controlled by the power management
bits, Bit PM1 and Bit PM0, in the control register as shown in
Table 11. The default mode is normal mode, where all internal
circuitry is fully powered up.
CS
1
16
SCLK
DIN
05400-035
DOUT
PART IS IN FULL
SHUTDOWN
tPOWER-UP
CS
16
16
SDATA
DIN
INVALID DATA
Rev. B | Page 29 of 36
05400-041
SCLK
AD7323
Data Sheet
CS
tPOWER-UP
15 16
15 16
SCLK
DIN
VALID DATA
VALID DATA
SDATA
Rev. B | Page 30 of 36
Data Sheet
AD7323
16
14
12
10
8
6
VARIABLE SCLK
VCC = 3V
VDD/VSS = 12V
TA = 25C
10 INTERNAL REFERENCE
VARIABLE SCLK
0
300
400
500
05400-052
200
300
400
100
200
100
Rev. B | Page 31 of 36
500
05400-053
2
0
12
VCC = 5V
VDD/VSS = 12V
TA = 25C
INTERNAL REFERENCE
18
AD7323
Data Sheet
SERIAL INTERFACE
Data is clocked into the AD7323 on the SCLK falling edge. The
three MSBs on the DIN line are decoded to select which register
is being addressed. The control register is a 12-bit register. If the
control register is addressed by the three MSBs, the data on the
DIN line is loaded into the control on the 15th SCLK falling
edge. If the sequence register or the range register is addressed,
the data on the DIN line is loaded into the addressed register on
the 11th SCLK falling edge.
The track-and-hold goes back into track mode on the 14th SCLK
rising edge. On the 16th SCLK falling edge, the DOUT line returns
to three-state. If the rising edge of CS occurs before 16 SCLK
cycles have elapsed, the conversion is terminated, and the
DOUT line returns to three-state. Depending on where the CS
signal is brought high, the addressed register may be updated.
t1
CS
tCONVERT
t2
1
2 IDENTIFICATION BITS
t3
ADD1
DOUT
THREE- ZERO
t9
STATE
DIN
WRITE
REG
SEL1
ADD0
SIGN
t4
13
14
DB11
15
16
t5
t7
DB10
DB2
t8
DB1
t10
REG
SEL2
tQUIET
DB0
THREE-STATE
MSB
LSB
DONT
CARE
Rev. B | Page 32 of 36
05400-036
SCLK
t6
Data Sheet
AD7323
MICROPROCESSOR INTERFACING
The serial interface on the AD7323 allows the part to be directly
connected to a range of different microprocessors. This section
explains how to interface the AD7323 with some common
microcontroller and DSP serial interface protocols.
AD7323 TO ADSP-21xx
The ADSP-21xx family of DSPs interface directly to the AD7323
without requiring glue logic. The VDRIVE pin of the AD7323 takes
the same supply voltage as that of the ADSP-21xx. This allows
the ADC to operate at a higher supply voltage than its serial
interface. The SPORT0 on the ADSP-21xx should be configured
as shown in Table 14.
Table 14. SPORT0 Control Register Setup
Description
Alternative framing
Active low frame signal
Right justify data
16-bit data-word
Internal serial clock
Frame every word
Internal receive frame sync
Internal transmit frame sync
AD7323 TO ADSP-BF53x
The ADSP-BF53x family of DSPs interfaces directly to the
AD7323 without requiring glue logic, as shown in Figure 53.
The SPORT0 Receive Configuration 1 register should be set up
as outlined in Table 15.
SCLK
SCLK
CS
DOUT
DR0
RFS0
DIN
DT0
DOUT
DR0
VDD
TFS0
RFS0
DT0
CS
SCLK0
DIN
RSCLK0
VDRIVE
ADSP-21xx1
AD73231
ADSP-BF53x1
AD73231
05400-038
Setting
TFSW = RFSW = 1
INVRFS = INVTFS = 1
DTYPE = 00
SLEN = 1111
ISCLK = 1
TFSR = RFSR = 1
IRFS = 0
ITFS = 1
VDD
1ADDITIONAL PINS OMITTED FOR CLARITY.
05400-037
VDRIVE
Setting
RCKFE = 1
LRFS = 1
RFSR = 1
IRFS = 1
RLSBIT = 0
RDTYPE = 00
IRCLK = 1
RSPEN = 1
SLEN = 1111
TFSR = RFSR = 1
Rev. B | Page 33 of 36
Description
Sample data with falling edge of RSCLK
Active low frame signal
Frame every word
Internal RFS used
Receive MSB first
Zero fill
Internal receive clock
Receive enable
16-bit data-word
Transmit and receive frame sync
AD7323
Data Sheet
APPLICATION HINTS
LAYOUT AND GROUNDING
3V/5V
VDD
VCC
AD73231
CS
VIN1
SCLK
VIN2
DOUT
VIN3
DIN
VSS
V
1ADDITIONAL PINS OMITTED FOR CLARITY.
05400-056
VIN0
V+
Rev. B | Page 34 of 36
Data Sheet
AD7323
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.65
BSC
0.30
0.19
COPLANARITY
0.10
8
0
SEATING
PLANE
0.75
0.60
0.45
ORDERING GUIDE
Model 1
AD7323BRUZ
AD7323BRUZ-REEL
AD7323BRUZ-REEL7
1
Temperature Range
40C to +85C
40C to +85C
40C to +85C
Package Description
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Rev. B | Page 35 of 36
Package Option
RU-16
RU-16
RU-16
AD7323
Data Sheet
NOTES
Rev. B | Page 36 of 36