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1. General description
The 74HC4051; 74HCT4051 is a single-pole octal-throw analog switch (SP8T) suitable for
use in analog or digital 8:1 multiplexer/demultiplexer applications. The switch features
three digital select inputs (S0, S1 and S2), eight independent inputs/outputs (Yn), a
common input/output (Z) and a digital enable input (E). When E is HIGH, the switches are
turned off. Inputs include clamp diodes. This enables the use of current limiting resistors
to interface inputs to voltages in excess of VCC.
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
74HC4051; 74HCT4051
NXP Semiconductors
4. Ordering information
Table 1.
Ordering information
Type number
74HC4051D
Package
Temperature range
Name
Description
Version
40 C to +125 C
SO16
SOT109-1
40 C to +125 C
SSOP16
SOT338-1
40 C to +125 C
TSSOP16
SOT403-1
40 C to +125 C
74HCT4051D
74HC4051DB
74HCT4051DB
74HC4051PW
74HCT4051PW
74HC4051BQ
74HCT4051BQ
SOT763-1
5. Functional diagram
9&&
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6
<
<
6
<
/2*,&
/(9(/
&219(56,21
<
2)
'(&2'(5
6
<
<
(
<
=
*1'
Fig 1.
9((
DDG
Functional diagram
74HC_HCT4051
2 of 31
74HC4051; 74HCT4051
NXP Semiconductors
6
6
6
;
*
<
<
08;'08;
<
<
<
<
<
<
DDG
DDG
Fig 2.
Logic symbol
Fig 3.
<
9((
9&&
9&&
9&&
9&&
9((
IURP
ORJLF
9((
=
DDG
Fig 4.
74HC_HCT4051
3 of 31
74HC4051; 74HCT4051
NXP Semiconductors
6. Pinning information
6.1 Pinning
<
WHUPLQDO
LQGH[DUHD
+&
+&7
9&&
+&
+&7
<
<
<
9&&
<
<
<
<
<
<
<
<
<
<
<
<
6
9((
9((
6
*1'
6
6
6
6
*1'
9&&
DDG
7UDQVSDUHQWWRSYLHZ
DDG
Fig 5.
Fig 6.
Pin description
Symbol
Pin
Description
VEE
supply voltage
GND
S0, S1, S2
11, 10, 9
select input
VCC
16
supply voltage
74HC_HCT4051
4 of 31
74HC4051; 74HCT4051
NXP Semiconductors
7. Functional description
7.1 Function table
Table 3.
Function table[1]
Input
Channel ON
S2
S1
S0
Y0 to Z
Y1 to Z
Y2 to Z
Y3 to Z
Y4 to Z
Y5 to Z
Y6 to Z
Y7 to Z
switches off
[1]
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol
Parameter
VCC
supply voltage
Conditions
[1]
Min
Max
Unit
0.5
+11.0
IIK
20
mA
ISK
20
mA
ISW
switch current
25
mA
IEE
supply current
20
mA
ICC
supply current
50
mA
IGND
ground current
50
mA
Tstg
storage temperature
65
+150
500
mW
100
mW
Ptot
power dissipation
per switch
[2]
[1]
To avoid drawing VCC current out of terminal Z, when switch current flows into terminals Yn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VCC current will flow out of terminals Yn, and in this case
there is no limit for the voltage drop across the switch, but the voltages at Yn and Z may not exceed VCC or VEE.
[2]
For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
74HC_HCT4051
5 of 31
74HC4051; 74HCT4051
NXP Semiconductors
Symbol
Parameter
Conditions
supply voltage
VCC
74HC4051
74HCT4051
Unit
Min
Typ
Max
Min
Typ
Max
VCC GND
2.0
5.0
10.0
4.5
5.0
5.5
VCC VEE
2.0
5.0
10.0
2.0
5.0
10.0
see Figure 7
and Figure 8
VI
input voltage
GND
VCC
GND
VCC
VSW
switch voltage
VEE
VCC
VEE
VCC
Tamb
ambient temperature
40
+25
+125
40
+25
+125
t/V
625
VCC = 4.5 V
1.67
139
1.67
139
ns/V
VCC = 6.0 V
83
ns/V
VCC = 10.0 V
31
ns/V
VCC = 2.0 V
DDG
9&& *1'
9
ns/V
DDG
9&& *1'
9
RSHUDWLQJDUHD
RSHUDWLQJDUHD
Fig 7.
9&& 9((9
74HC_HCT4051
Fig 8.
9&& 9((9
6 of 31
74HC4051; 74HCT4051
NXP Semiconductors
Parameter
Conditions
Min
Typ
Max
Unit
100
180
Tamb = 25 C
RON(peak) ON resistance (peak)
[1]
RON(rail)
ON resistance (rail)
90
160
70
130
150
80
140
70
120
60
105
Vis = VEE
VCC = 2.0 V; VEE = 0 V; ISW = 100 A
[1]
Vis = VCC
VCC = 2.0 V; VEE = 0 V; ISW = 100 A
RON
ON resistance mismatch
between channels
150
90
160
80
140
65
120
225
200
165
[1]
[1]
Tamb = 40 C to +85 C
RON(peak) ON resistance (peak)
74HC_HCT4051
[1]
7 of 31
74HC4051; 74HCT4051
NXP Semiconductors
Table 6.
RON resistance per switch for 74HC4051 and 74HCT4051 continued
VI = VIH or VIL; for test circuit see Figure 9.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
For 74HC4051: VCC GND or VCC VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V.
For 74HCT4051: VCC GND = 4.5 V and 5.5 V, VCC VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V.
Symbol
Parameter
Conditions
RON(rail)
ON resistance (rail)
Vis = VEE
VCC = 2.0 V; VEE = 0 V; ISW = 100 A
Min
Typ
Max
Unit
175
150
130
200
175
150
270
240
195
[1]
Vis = VCC
VCC = 2.0 V; VEE = 0 V; ISW = 100 A
[1]
Tamb = 40 C to +125 C
RON(peak) ON resistance (peak)
RON(rail)
ON resistance (rail)
[1]
Vis = VEE
VCC = 2.0 V; VEE = 0 V; ISW = 100 A
210
180
160
240
210
180
[1]
Vis = VCC
VCC = 2.0 V; VEE = 0 V; ISW = 100 A
[1]
[1]
When supply voltages (VCC VEE) near 2.0 V the analog switch ON resistance becomes extremely non-linear. When using a supply of
2 V, it is recommended to use these devices only for transmitting digital signals.
74HC_HCT4051
8 of 31
74HC4051; 74HCT4051
NXP Semiconductors
PQE
521
9VZ
9&&
IURPVHOHFW
LQSXW
6Q
<Q
9LV
=
*1'
9((
,VZ
V sw
R ON = -------I sw
Fig 9.
9LV9
DDQ
(2) VCC = 6 V
(3) VCC = 9 V
Table 7.
Static characteristics for 74HC4051
Voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at pins Yn or Z, whichever is assigned as an input.
Vos is the output voltage at pins Z or Yn, whichever is assigned as an output.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC = 2.0 V
1.5
1.2
VCC = 4.5 V
3.15
2.4
VCC = 6.0 V
4.2
3.2
VCC = 9.0 V
6.3
4.7
VCC = 2.0 V
0.8
0.5
Tamb = 25 C
VIH
VIL
II
IS(OFF)
IS(ON)
HIGH-level input
voltage
LOW-level input
voltage
OFF-state leakage
current
ON-state leakage
current
74HC_HCT4051
VCC = 4.5 V
2.1
1.35
VCC = 6.0 V
2.8
1.8
VCC = 9.0 V
4.3
2.7
0.1
VCC = 10.0 V
0.2
0.1
all channels
0.4
0.4
9 of 31
74HC4051; 74HCT4051
NXP Semiconductors
Table 7.
Static characteristics for 74HC4051 continued
Voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at pins Yn or Z, whichever is assigned as an input.
Vos is the output voltage at pins Z or Yn, whichever is assigned as an output.
Symbol
Parameter
Conditions
ICC
supply current
CI
input capacitance
Csw
switch capacitance
Min
Typ
Max
Unit
VCC = 6.0 V
8.0
VCC = 10.0 V
16.0
3.5
pF
independent pins Yn
pF
common pins Z
25
pF
VCC = 2.0 V
1.5
VCC = 4.5 V
3.15
VCC = 6.0 V
4.2
VCC = 9.0 V
6.3
VCC = 2.0 V
0.5
VCC = 4.5 V
1.35
VCC = 6.0 V
1.8
VCC = 9.0 V
2.7
VCC = 6.0 V
1.0
VCC = 10.0 V
2.0
per channel
1.0
all channels
4.0
4.0
Tamb = 40 C to +85 C
VIH
VIL
II
IS(OFF)
HIGH-level input
voltage
LOW-level input
voltage
OFF-state leakage
current
IS(ON)
ON-state leakage
current
ICC
supply current
80.0
VCC = 10.0 V
160.0
VCC = 2.0 V
1.5
VCC = 4.5 V
3.15
VCC = 6.0 V
4.2
VCC = 9.0 V
6.3
VCC = 2.0 V
0.5
VCC = 4.5 V
1.35
VCC = 6.0 V
1.8
VCC = 9.0 V
2.7
Tamb = 40 C to +125 C
VIH
VIL
HIGH-level input
voltage
LOW-level input
voltage
74HC_HCT4051
10 of 31
74HC4051; 74HCT4051
NXP Semiconductors
Table 7.
Static characteristics for 74HC4051 continued
Voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at pins Yn or Z, whichever is assigned as an input.
Vos is the output voltage at pins Z or Yn, whichever is assigned as an output.
Symbol
Parameter
Conditions
II
IS(OFF)
OFF-state leakage
current
Min
Typ
Max
Unit
VCC = 6.0 V
1.0
VCC = 10.0 V
2.0
per channel
1.0
all channels
4.0
4.0
IS(ON)
ON-state leakage
current
ICC
supply current
160.0
VCC = 10.0 V
320.0
Conditions
Min
Typ
Max
Unit
Table 8.
Static characteristics for 74HCT4051
Voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at pins Yn or Z, whichever is assigned as an input.
Vos is the output voltage at pins Z or Yn, whichever is assigned as an output.
Symbol
Parameter
Tamb = 25 C
VIH
HIGH-level input
voltage
2.0
1.6
VIL
LOW-level input
voltage
1.2
0.8
II
0.1
IS(OFF)
OFF-state leakage
current
0.1
all channels
0.4
0.4
8.0
16.0
50
180
3.5
pF
independent pins Yn
pF
common pins Z
25
pF
IS(ON)
ON-state leakage
current
ICC
supply current
ICC
additional supply
current
CI
input capacitance
Csw
switch capacitance
74HC_HCT4051
11 of 31
74HC4051; 74HCT4051
NXP Semiconductors
Table 8.
Static characteristics for 74HCT4051 continued
Voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at pins Yn or Z, whichever is assigned as an input.
Vos is the output voltage at pins Z or Yn, whichever is assigned as an output.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 40 C to +85 C
VIH
HIGH-level input
voltage
2.0
VIL
LOW-level input
voltage
0.8
II
1.0
IS(OFF)
OFF-state leakage
current
1.0
all channels
4.0
4.0
80.0
160.0
225
IS(ON)
ON-state leakage
current
ICC
supply current
ICC
additional supply
current
Tamb = 40 C to +125 C
VIH
HIGH-level input
voltage
2.0
VIL
LOW-level input
voltage
0.8
II
1.0
IS(OFF)
OFF-state leakage
current
1.0
all channels
4.0
4.0
160.0
320.0
245
IS(ON)
ON-state leakage
current
ICC
supply current
ICC
additional supply
current
74HC_HCT4051
12 of 31
74HC4051; 74HCT4051
NXP Semiconductors
9&&
IURPVHOHFW
LQSXW
6Q
,VZ
,VZ
Q<Q
Q=
*1'
9LV
9((
9RV
DDK
9&&
+,*+
IURPVHOHFW
LQSXW
6Q
,VZ
Q<Q
9LV
Q=
*1'
9RV
9((
DDK
Parameter
Conditions
Min
Typ
Max
Unit
14
60
ns
12
ns
Tamb = 25 C
tpd
74HC_HCT4051
[1]
10
ns
ns
13 of 31
74HC4051; 74HCT4051
NXP Semiconductors
Table 9.
Dynamic characteristics for 74HC4051 continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol
Parameter
Conditions
ton
turn-on time
Min
Typ
Max
Unit
72
345
ns
29
69
ns
[2]
22
ns
21
59
ns
18
51
ns
66
345
ns
28
69
ns
20
ns
19
59
ns
16
51
ns
58
290
ns
31
58
ns
[2]
turn-off time
[3]
18
ns
17
49
ns
18
42
ns
61
290
ns
25
58
ns
19
ns
18
49
ns
18
42
ns
25
pF
75
ns
15
ns
13
ns
10
ns
[3]
[4]
Tamb = 40 C to +85 C
tpd
74HC_HCT4051
[1]
14 of 31
74HC4051; 74HCT4051
NXP Semiconductors
Table 9.
Dynamic characteristics for 74HC4051 continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol
Parameter
Conditions
ton
turn-on time
Min
Typ
Max
Unit
430
ns
86
ns
[2]
73
ns
64
ns
430
ns
86
ns
73
ns
64
ns
365
ns
73
ns
62
ns
53
ns
365
ns
73
ns
62
ns
53
ns
90
ns
18
ns
15
ns
12
ns
520
ns
104
ns
88
ns
77
ns
520
ns
104
ns
88
ns
77
ns
[2]
turn-off time
[3]
[3]
Tamb = 40 C to +125 C
tpd
[1]
turn-on time
[2]
74HC_HCT4051
[2]
15 of 31
74HC4051; 74HCT4051
NXP Semiconductors
Table 9.
Dynamic characteristics for 74HC4051 continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol
Parameter
Conditions
toff
turn-off time
Min
Typ
Max
Unit
435
ns
87
ns
74
ns
72
ns
435
ns
87
ns
74
ns
72
ns
Min
Typ
Max
12
ns
ns
26
55
ns
22
ns
16
39
ns
28
55
ns
24
ns
16
39
ns
[1]
[2]
[3]
[4]
[3]
[3]
Parameter
Conditions
Unit
Tamb = 25 C
tpd
[1]
turn-on time
[2]
74HC_HCT4051
[2]
16 of 31
74HC4051; 74HCT4051
NXP Semiconductors
Parameter
Conditions
toff
turn-off time
Min
Typ
Max
19
45
ns
16
ns
16
32
ns
23
45
ns
20
ns
16
32
ns
25
pF
15
ns
10
ns
[3]
Unit
[3]
[4]
Tamb = 40 C to +85 C
tpd
[1]
turn-on time
[2]
69
ns
49
ns
69
ns
49
ns
56
ns
40
ns
56
ns
40
ns
18
ns
12
ns
[2]
turn-off time
[3]
[3]
Tamb = 40 C to +125 C
tpd
[1]
turn-on time
83
ns
59
ns
83
ns
59
ns
74HC_HCT4051
[2]
[2]
17 of 31
74HC4051; 74HCT4051
NXP Semiconductors
Parameter
Conditions
toff
turn-off time
Min
Typ
Max
68
ns
48
ns
68
ns
48
ns
[1]
[2]
[3]
[4]
Unit
[3]
9LVLQSXW
W3/+
9RVRXWSXW
W3+/
DDG
74HC_HCT4051
18 of 31
74HC4051; 74HCT4051
NXP Semiconductors
9,
90
(6QLQSXWV
9
W3/=
W3=/
9RVRXWSXW
W3+=
W3=+
9RVRXWSXW
VZLWFK21
VZLWFK21
VZLWFK2))
DDG
9,
W:
QHJDWLYH
SXOVH
90
90
9
WI
WU
WU
9,
SRVLWLYH
SXOVH
9
WI
90
90
W:
9&& 9LV
38/6(
*(1(5$725
9,
9&&
9RV
5/
'87
57
6
RSHQ
&/
*1'
9((
DDH
74HC_HCT4051
19 of 31
74HC4051; 74HCT4051
NXP Semiconductors
Table 11.
Test data
Test
Input
VI
Load
Vis
tr, tf
at fmax
other[1]
S1 position
CL
RL
tPHL, tPLH
[2]
pulse
< 2 ns
6 ns
50 pF
1 k
open
tPZH, tPHZ
[2]
VCC
< 2 ns
6 ns
50 pF
1 k
VEE
tPZL, tPLZ
[2]
VEE
< 2 ns
6 ns
50 pF
1 k
VCC
[1]
[2]
tr = tf = 6 ns; when measuring fmax, there is no constraint to tr and tf with 50 % duty factor.
VI values:
a) For 74HC4051: VI = VCC
b) For 74HCT4051: VI = 3 V
74HC_HCT4051
20 of 31
74HC4051; 74HCT4051
NXP Semiconductors
Parameter
Conditions
Min
Typ
dsin
sine-wave distortion
Max Unit
0.04
0.02
0.12
0.06
iso
isolation (OFF-state)
crosstalk voltage
Vct
f(3dB)
[1]
50
dB
[1]
50
dB
110
mV
220
mV
3 dB frequency response
RL = 50 ; see Figure 19
VCC = 2.25 V; VEE = 2.25 V
[2]
170
MHz
[2]
180
MHz
[1]
[2]
Adjust input voltage Vis to 0 dBm level at Vos for 1 MHz (0 dBm = 1 mW into 50 ).
9&&
6Q
)
9LV
<Q=
=<Q
9((
*1'
9RV
5/
&/
G%
DDQ
74HC_HCT4051
21 of 31
74HC4051; 74HCT4051
NXP Semiconductors
9&&
6Q
)
<Q=
9LV
=<Q
9((
*1'
9RV
5/
&/
G%
DDQ
a. Test circuit
DDH
LVR
G%
ILN+]
5/
5/
9&&
6Q(
9FW
<Q
*
5/
=
9((
*1'
5/
RVFLOORVFRSH
DDQ
Fig 18. Test circuit for measuring crosstalk between control input and any switch
74HC_HCT4051
22 of 31
74HC4051; 74HCT4051
NXP Semiconductors
9&&
6Q
)
9LV
<Q=
=<Q
9((
*1'
9RV
5/
&/
G%
DDQ
a. Test circuit
DDG
9RV
G%
IN+]
74HC_HCT4051
23 of 31
74HC4051; 74HCT4051
NXP Semiconductors
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74HC4051; 74HCT4051
NXP Semiconductors
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13. Abbreviations
Table 13.
Abbreviations
Acronym
Description
CMOS
ESD
ElectroStatic Discharge
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
Revision history
Document ID
Release date
Change notice
Supersedes
74HC_HCT4051 v.8
20160205
74HC_HCT4051 v.7
Modifications:
74HC_HCT4051 v.7
Modifications:
74HC_HCT4051 v.6
Modifications:
20120719
74HC_HCT4051 v.6
74HC_HCT4051 v.5
20111213
74HC_HCT4051 v.5
20110513
74HC_HCT4051 v.4
74HC_HCT4051 v.4
20110117
74HC_HCT4051 v.3
74HC_HCT4051 v.3
20051219
Product specification
74HC_HCT4051_CNV_2
74HC_HCT4051
28 of 31
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NXP Semiconductors
Product status[3]
Definition
Development
This document contains data from the objective specification for product development.
Qualification
Production
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT4051
29 of 31
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NXP Semiconductors
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
74HC_HCT4051
30 of 31
NXP Semiconductors
74HC4051; 74HCT4051
8-channel analog multiplexer/demultiplexer
17. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
8
9
10
11
11.1
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . 13
Additional dynamic characteristics . . . . . . . . . 21
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 24
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 28
Legal information. . . . . . . . . . . . . . . . . . . . . . . 29
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 29
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Contact information. . . . . . . . . . . . . . . . . . . . . 30
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section Legal information.