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Am27C010
1 Megabit (128 K x 8-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
Fast access time
GENERAL DESCRIPTION
The Am27C010 is a 1 Megabit, ultraviolet erasable programmable read-only memory. It is organized as 128K
words by 8 bits per word, operates from a single +5 V
supply, has a static standby mode, and features fast
single address location programming. Products are
available in windowed ceramic DIP packages, as well
as plastic one time programmable (OTP) PDIP and
PLCC packages.
Data can be typically accessed in less than 45 ns, allowing high-performance microprocessors to operate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
BLOCK DIAGRAM
VCC
VSS
Data Outputs
DQ0DQ7
VPP
OE#
CE#
PGM#
A0A16
Address
Inputs
Output Enable
Chip Enable
and
Prog Logic
Output
Buffers
Y
Decoder
Y
Gating
X
Decoder
1,048,576
Bit Cell
Matrix
10205I-1
Publication# 10205 Rev: I
Issue Date: April 26, 1999
Amendment/0
Am27C010
VCC = 5.0 V 5%
-45
-45
-55
-70
-90
-120
-150
-200
45
55
70
90
120
150
200
250
45
55
70
90
120
150
200
250
25
35
35
40
50
65
75
75
Speed Options
-255
CONNECTION DIAGRAMS
Top View
PGM# (P#)
NC
PLCC
VCC
A16
31
PGM# (P#)
A15
30
NC
A12
29
A14
4 3 2 1 32 31 30
A7
28
A13
A7
29
A14
A6
28
A13
A5
A4
7
8
27
26
A8
A9
A3
25
A11
A2
10
24
OE# (G#)
A1
11
23
A10
A0
12
22
DQ0
13
21
CE# (E#)
DQ7
27
A8
A5
26
A9
A3
OE# (G#)
A2
10
23
A10
A1
11
22
CE# (E#)
A0
12
21
DQ7
DQ0
13
20
DQ6
14 15 16 17 18 19 20
DQ1
14
19
DQ5
DQ2
15
18
DQ4
VSS
16
17
DQ3
DQ5
DQ6
A11
24
DQ4
25
A4
VSS
DQ3
DQ1
DQ2
A6
VCC
32
VPP
A16
VPP
A12
A15
DIP
10205I-3
10205I-2
Notes:
1. JEDEC nomenclature is in parenthesis.
2. The 32-pin DIP to 32-pin PLCC configuration varies from the JEDEC 28-pin DIP to 32-pin PLCC configuration.
PIN DESIGNATIONS
LOGIC SYMBOL
A0A16
= Address Inputs
CE# (E#)
DQ0DQ7
= Data Input/Outputs
OE# (G#)
PGM# (P#)
VCC
PGM# (P#)
VPP
OE# (G#)
VSS
= Ground
17
8
A0A16
DQ0DQ7
CE# (E#)
10205I-4
Am27C010
ORDERING INFORMATION
UV EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:
AM27C010
-45
B
OPTIONAL PROCESSING
Blank = Standard Processing
B
= Burn-In
VOLTAGE TOLERANCE
5 = VCC 5%, 45 ns only
See Product Selector Guide and Valid Combinations
TEMPERATURE RANGE
C = Commercial (0C to +70C)
I = Industrial (40C to +85C)
E = Extended (55C to +125C)
PACKAGE TYPE
D = 32-Pin Ceramic DIP (CDV032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am27C010
1 Megabit (128 K x 8-Bit) CMOS UV EPROM
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Valid Combinations
AM27C010-45
VCC = 5.0 V 5%
AM27C010-45
VCC = 5.0 V 10%
AM27C010-55
AM27C010-70
AM27C010-90
AM27C010-120
AM27C010-150
AM27C010-200
AM27C010-255
VCC = 5.0 V 5%
Am27C010
ORDERING INFORMATION
OTP EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:
AM27C010
-45
5
OPTIONAL PROCESSING
Blank = Standard Processing
VOLTAGE TOLERANCE
5 = VCC 5%, 45 ns only
See Product Selector Guide and Valid Combinations
TEMPERATURE RANGE
C = Commercial (0C to +70C)
I = Industrial (40C to +85C)
PACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Plastic Leaded Chip Carrier (PL 032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am27C010
1 Megabit (128 K x 8-Bit) CMOS OTP EPROM
Valid Combinations
Valid Combinations
AM27C010-45
VCC = 5.0 V 5%
AM27C010-45
VCC = 5.0 V 10%
JC, PC
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
AM27C010-55
AM27C010-70
AM27C010-90
AM27C010-120
AM27C010-150
AM27C010-200
AM27C010-255
VCC = 5.0 V 5%
Am27C010
FUNCTIONAL DESCRIPTION
Device Erasure
In order to clear all locations of their programmed contents, the device must be exposed to an ultraviolet light
source. A dosage of 15 W seconds/cm2 is required to
completely erase the device. This dosage can be obtained by exposure to an ultraviolet lampwavelength
of 2537 with intensity of 12,000 W/cm2 for 15 to 20
minutes. The device should be directly under and about
one inch from the source, and all filters should be removed from the UV light source prior to erasure.
Note that all UV erasable devices will erase with light
sources having wavelengths shorter than 4000 , such
as fluorescent light and sunlight. Although the erasure
process happens over a much longer time period, exposure to any light source should be prevented for
maximum system reliability. Simply cover the package
window with an opaque label or substance.
Device Programming
Upon delivery, or after each erasure, the device has
all of its bits in the ONE, or HIGH state. ZEROs are
loaded into the device through the programming procedure.
The device enters the programming mode when 12.75
V 0.25 V is applied to the VPP pin, and CE# and
PGM# are at VIL and OE# is at VIH.
For programming, the data to be programmed is applied 8 bits in parallel to the data pins.
The flowchar t in the Programming section of the
EPROM Products Data Book (Section 5, Figure 5-1)
shows AMDs Flashrite algorithm. The Flashrite algorithm reduces programming time by using a 100 s programming pulse and by giving each address only as
many pulses to reliably program the data. After each
pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional
pulses are given until it verifies or the maximum pulses
allowed is reached. This process is repeated while sequencing through each address of the device. This part
of the algorithm is done at VCC = 6.25 V to assure that
each EPROM bit is programmed to a sufficiently high
threshold voltage. After the final address is completed,
the entire EPROM memory is verified at VCC = VPP =
5.25 V.
Please refer to Section 5 of the EPROM Products Data
Book for additional programming information and specifications.
Program Verify
A verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verify should be performed with OE# and CE#, at
VIL, PGM# at VIH, and VPP between 12.5 V and 13.0 V.
Autoselect Mode
The autoselect mode provides manufacturer and device identification through identifier codes on DQ0
DQ7. This mode is primarily intended for programming
equipment to automatically match a device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C 5C
ambient temperature range that is required when programming the device.
To activate this mode, the programming equipment
must force VH on address line A9. Two identifier bytes
may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH (that is, changing
the address from 00h to 01h). All other address lines
must be held at VIL during the autoselect mode.
Byte 0 (A0 = VIL) represents the manufacturer code,
and Byte 1 (A0 = VIH), the device identifier code. Both
codes have odd parity, with DQ7 as the parity bit.
Read Mode
To obtain data at the device outputs, Chip Enable (CE#)
and Output Enable (OE#) must be driven low. CE# controls the power to the device and is typically used to select the device. OE# enables the device to output data,
independent of device selection. Addresses must be
stable for at least tACC tOE. Refer to the Switching
Waveforms section for the timing diagram.
Standby Mode
The device enters the CMOS standby mode when CE#
is at VCC 0.3 V. Maximum VCC current is reduced to
100 A. The device enters the TTL-standby mode
when CE# is at VIH. Maximum VCC current is reduced
to 1.0 mA. When in either standby mode, the device
places its outputs in a high-impedance state, independent of the OE# input.
Output OR-Tieing
To accommodate multiple memory connections, a
two-line control function provides:
Program Inhibit
Programming different data to multiple devices in parallel is easily accomplished. Except for CE#, all like inputs of the devices may be common. A TTL low-level
program pulse applied to one devices CE# input with
Am27C010
CE# should be decoded and used as the primary device-selecting function, while OE# be made a common
connection to all devices in the array and connected to
the READ line from the system control bus. This assures that all deselected memory devices are in their
low-power standby mode and that the output pins are
only active when data is desired from a particular memory device.
System Applications
During the switch between active and standby conditions, transient current peaks are produced on the ris-
CE#
OE#
PGM#
A0
A9
VPP
Outputs
Read
VIL
VIL
DOUT
Output Disable
VIH
High Z
Standby (TTL)
VIH
High Z
VCC 0.3 V
High Z
Program
VIL
VIH
VIL
VPP
DIN
Program Verify
VIL
VIL
VIH
VPP
DOUT
Program Inhibit
VIH
VPP
High Z
Manufacturer Code
VIL
VIL
VIL
VH
01h
Device Code
VIL
VIL
VIH
VH
0Eh
Standby (CMOS)
Autoselect
(Note 3)
Notes:
1. VH = 12.0 V 0.5 V.
2. X = Either VIH or VIL.
3. A1A8 and A1016 = VIL
4. See DC Programming Characteristics for VPP voltage during programming.
Am27C010
OPERATING RANGES
Storage Temperature
OTP Products. . . . . . . . . . . . . . . . . . 65C to +125C
All Other Products . . . . . . . . . . . . . . 65C to +150C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . 55C to +125C
Notes:
1. Minimum DC voltage on input or I/O pins 0.5 V. During
voltage transitions, the input may overshoot VSS to 2.0 V
for periods of up to 20 ns. Maximum DC voltage on input
and I/O pins is VCC + 5 V. During voltage transitions, input
and I/O pins may overshoot to VCC + 2.0 V for periods up
to 20 ns.
Operating ranges define those limits between which the functionality of the device is guaranteed.
Am27C010
Parameter Description
Test Conditions
Min
Max
VOH
IOH = 400 A
2.4
VOL
IOL = 2.1 mA
VIH
VIL
ILI
VIN = 0 V to VCC
1.0
ILO
VOUT = 0 V to VCC
5.0
ICC1
Unit
V
0.45
2.0
VCC + 0.5
0.5
+0.8
C/I Devices
30
E Devices
60
A
mA
ICC2
CE# = VIH
1.0
mA
ICC3
100
IPP1
100
Caution: The device must not be removed from (or inserted into) a socket when VCC or VPP is applied.
Notes:
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP..
30
30
25
25
Supply Current
in mA
Supply Current
in mA
20
15
Figure 1.
4
5
6
7
Frequency in MHz
15
10
75 50 55
10
1
20
10
10205I-5
10205I-6
Am27C010
TEST CONDITIONS
Table 1.
5.0 V
-45,
-55
Test Condition
2.7 k
Device
Under
Test
Test Specifications
Output Load
CL
30
10205I-7
Figure 3.
100
pF
20
Note:
Diodes are IN3064 or equivalents.
Unit
1 TTL gate
6.2 k
All
others
ns
0.03.0
0.452.4
1.5
0.8, 2.0
1.5
0.8, 2.0
Test Setup
2.4 V
2.0 V
2.0 V
Test Points
1.5 V
Test Points
1.5 V
0.8 V
0V
0.8 V
0.45 V
Input
Output
Output
Input
10205I-8
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
KS000010-PAL
Am27C010
AC CHARACTERISTICS
Parameter Symbols
JEDEC
Standard
tAVQV
tACC
tELQV
Am27C010
Description
Test Setup
-45
-55
-70
CE#,
Max
OE# = VIL
45
55
70
90
120
150
200
250
ns
tCE
45
55
70
90
120
150
200
250
ns
tGLQV
tOE
25
35
35
40
50
65
75
75
ns
tEHQZ
tGHQZ
tDF
(Note 2)
Max
25
25
25
25
35
35
40
40
ns
tAXQX
tOH
Min
ns
Caution: Do not remove the device from (or insert it into) a socket or board that has VPP or VCC applied.
Notes:
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
2. This parameter is sampled and not 100% tested.
3. Switching characteristics are over operating range, unless otherwise specified.
4. See Figure 3 and Table 1 for test specifications.
SWITCHING WAVEFORMS
2.4
Addresses
0.45
2.0
0.8
2.0
0.8
Addresses Valid
CE#
tCE
OE#
tDF (Note 2)
tOE
Output
High Z
tACC
(Note 1)
tOH
High Z
Valid Output
10205I-9
Notes:
1. OE# may be delayed up to tACC tOE after the falling edge of the addresses without impact on tACC.
2. tDF is specified from OE# or CE#, whichever occurs first.
PACKAGE CAPACITANCE
Parameter Symbol
CIN
COUT
Parameter
Description
CDV028
Test Conditions
PD 028
Typ
Max
Typ
Max
Typ
Max
Unit
Input Capacitance
VIN = 0
12
12
12
pF
Output Capacitance
VOUT = 0
13
15
11
14
11
14
pF
Notes:
1. This parameter is only sampled and not 100% tested.
2. TA = +25C, f = 1 MHz.
10
PL 032
Am27C010
PHYSICAL DIMENSIONS*
CDV03232-Pin Ceramic Dual In-Line Package, UV Lens (measured in inches)
DATUM D
CENTER PLANE
UV Lens
.565
.605
1
INDEX AND
TERMINAL NO. 1
I.D. AREA
TOP VIEW
DATUM D
CENTER PLANE
1.635
1.680
.160
.220
BASE PLANE
SEATING PLANE
.015
.060
.700
MAX
94
105
.125
.200
.300 BSC
.005 MIN
.600
BSC
.045
.065
.008
.018
.100 BSC
.014
.026
END VIEW
SIDE VIEW
16-000038H-3
CDV032
DF11
3-30-95 ae
* For reference only. BSC is an ANSI standard for Basic Space Centering.
.600
.625
17
32
.009
.015
.530
.580
Pin 1 I.D.
.630
.700
16
.045
.065
0
10
.005 MIN
.140
.225
SEATING PLANE
.120
.160
.090
.110
.016
.022
.015
.060
Am27C010
16-038-S_AG
PD 032
EC75
5-28-97 lv
11
PHYSICAL DIMENSIONS
PL 03232-Pin Plastic Leaded Chip Carrier (measured in inches)
.447
.453
.485
.495
.009
.015
.585
.595
.042
.056
.125
.140
Pin 1 I.D.
.080
.095
.547
.553
SEATING
PLANE
.400
REF.
.490
.530
.013
.021
.050 REF.
.026
.032
TOP VIEW
SIDE VIEW
16-038FPO-5
PL 032
DA79
6-28-94 ae
Revision H
Global
Revision I
Distinctive Characteristics
Corrected description of packages to 32 pin.
Physical Dimensions
On CerDIP and PDIP package drawings, corrected pin
count to 32.
Trademarks
Copyright 1999 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Flashrite is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
12
Am27C010