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CS 1251 IV SEMESTER
CHAPTER - 1
UNIT 1 --------BASIC STRUCTURE OF COMPUTERS
PART – A
1.Write the basic functional units of computer ?
The basic functional units of a computer are input unit ,output unit ,memory unit , ALU unit and control
unit.
3. Compute the effective CPI for a processor, for the following instruction mix:
An enhancement to the processor is made by adding a branch prediction unit. This decreases the number of
cycles taken to execute a branch from 3 to 2. What is the improvement in performance ?
Speed up =execution time old /execution time new
Execution time old or CPU time=I.C.* Clk Cycles * cycle time
Execution time old =[40*1+20*3+10*2+20*2+10*2]
Cycles*cycles time
The enhancement decreases the number of cycles taken for branch instruction from 3 to 2.
Execution time new =[40*1+20*3+10*2+20*2+10*2]
=180 cycles *cycle time
Speed up = (200*cycles time)/(180 cycles *cycles time) =1.1
5. Why data bus is bidirectional and address bus is unidirectional in most microprocessor?
Data bus:
The data bus consists of 8, 16, 32 or more parallel signal lines. These lines are used to send data to
memory and output ports ,and to receive data from memory and input port. Therefore, data bus lines are
bidirectional. This means that CPU can read data on these lines from memory or from a port, as well as send data
out of these lines to a memory location or to a port. The data bus is connected in parallel to all peripherals. The
communication between peripherals and CPU is activated by giving output enable pulse to the peripherals. Outputs
of peripherals are floated when they are not in use.
Address bus:
It is a unidirectional bus. The address bus consists of 16, 20, 24 or more parallel signal lines. On these lines the
CPU sends out the address of the memory location or IO port that is to be written to or read from. Here, the
communication is one-way, the address is send from CPU to memory and IO port and hence these lines are
unidirectional.
6. What is meant by stored program concepts? Discuss.
Stored program concept is an idea of storing the program and data in the memory.
7. Define multiprogramming?
Multiprogramming is a technique in several jobs are in main memory at once and the processor is switched
from job as needed to keep several jobs advancing while keeping the peripheral devices in use.
8. Define multiprocessing?
Multiprocessing is the ability of an operating system to support more than one process at the same time.
9. Define time sharing?
Time sharing is the process in which the system is designed to allow many users to use the CPU simultaneously.
10. What is a super computer?
A computer with high computational speed, very large memory and expansive parallel structured hardware is
known as a super computer.
EX: CDC 6600
11. What is meant by VLSI technology?
VLSI is the abbreviation for Very Large Scale Integration. In this technology millions of transistors are
put inside a single chip as tiny components. The VLSI chips do the function of millions of transistors. These are
used to implement parallel algorithms directly in hardware.
12. What are the characteristics of Von Neumann computers?
* The program can data were represented in digital form and stored in the memory.
* The architecture has 5 basic parts -> the memory, the ALU, Control Unit, Input unit and output unit.
* It uses binary arithmetic.
* There were only fixed point arithmetic and no floating point arithmetic.
* used a special general purpose register called Accumulator.
* The first general purpose machine.
13. Define parallel processing.
It is an efficient form of information processing to exploit the concurrent events in the computing process.
14. Define pipelining.
Pipelining is technique of decomposing a sequential process in to number of sub operations and each of these
sub operations are carried out independently in dedicated segments concurrently.
15. Mention some applications of parallel processing.
* In simulation and Modeling -> weather forecasting, oceanography, socio economy
* Engineering design and automation -> Aerodynamics, finite element analysis AI
* Medical, military and research -> computer assisted topography genetic engineering etc
* Energy resource explosion.
16. In what way hardware and software are equivalent? Not equivalent.
Software and hardware are logically equivalent. Any operation done by software could be done by hardware.
Any instruction executed by hardware can be simulated by software. They are not equivalent in the sense that,
minimum hardware required to execute software cannot be simulated by software. In other words with out the
hardware software cannot function, whereas with NIL software the hardware function perfectly.
In a load / store architecture, operands must be in registers before they can be processed. The
instructions that refer to memory
Locations are load, store and jump / branch .It supports limited set of addressing modes and use hardware
to execute instructions.
2. Explain the absolute and auto increment addressing modes with an example instruction.
Absolute or direct addressing: To fetch an operand, the address of the operand in the memory is given
in the instruction. This form is called direct addressing. This type of addressing mode is used for handling
STATIC data
Add B=> A = A + M [B]
Auto-increment addressing mode: It is similar to register indirect mode except that register is incremented
after its value is used to access memory.
Add R1, (R2) +; R1 <- R1 + M [R2]
R2 <- R2 +d
This type of addressing mode is useful for stepping through arrays in a loop.
R2 – start of array d – size of an element
3. List out the different computer instruction formats.
4 address instruction
Opcode Source opera Source opera Destination opera Next instructi
address 1 address 2 address address
3 address instruction
Opcode Source operand address Source operand address Destination opera
address
2 address instruction
Opcode Source destination opera Source operand address 2
address
1 address instruction
Opcode Source operand address
0 address instruction
Opcode
Operand R3
Memory
Relative addressing:
The effective address is obtained by adding contents of program counter with displacement.
Effective address = [PC] + displacement
Ex: near, far, short, jump instructions
1. mem address instruction displacement
1000 near 10
EA for next instruction = [PC] + 10
= 1001 + 10
= 1011
2. mem address instruction displacement
4000 JC 50
EA = 4001 + 50
= 4051
12. What are the four basic types of operations that need to be supported by an instruction set?
• Data transfer between memory and the processor register.
• Arithmetic and logic operations on data.
• Program sequencing and control.
• i/o transfer
14. The memory unit of a computer has 256 K words of 32 bits each. The computer has an instruction
format with four fields: an operation code field, a mode field to specify one of seven addressing modes, a
memory address. Specify the instruction format and the number of bits in each field if the instruction is in one
memory word.
Total memory size = 256 K * 32 bits
= 1024 Kbytes
Address bits = 20
Mode field = 3 bit 2^3 = 8 >7
Register address field = 6 bits 2^6 = 64> 60
Opcode field = 32 - 20 – 3 – 6=3 bits.
101101 A
101101 B
101101 C
101101 D
101101 E
101101 F
10110001011 Product(2835)
= XiYi + (Xi+Yi)Ci
= Gi + PiCi
The IEEE standard describes the floating point representations and the way in which the four basic
arithmetic operations are to be performed on these floating point operands.
There are two types of representations for floating point numbers.
1. Single precision
2. Double precision
32 bit
S E’ M
Sign of 8 bit signed 23 bit mantissa/fraction
Number exponent
0-signifies + excess - 127
1-signifies - representation
Double precision
Double precision representation contains 11 bits excess -1023 exponent E’ which has the range 1≤ E’ ≤
2046 for normal values. This means that the actual exponent E is in range -1022 ≤ E ≤ 1023. The 53 bit
mantissa provides a precision equivalent to about 16 decimal digits.
64 bit
S E’ M
Overflow: If the result of an arithmetic operation is outside the representable range, then overflow is
said to occur.
7. Define Underflow
If the result of the arithmetic operation involving n-bit numbers is too small to represent by n- bits,
underflow is said to occur.
The guard bits are the extra bits which is used to retain the intermediate steps to increase the accuracy in
the final results.
Example: In 32 bit single precision floating point representation the Mantissa bits are limited to 24 bit
including leading 1. some operations which results in extra bits are called guard bits.
10. Give the Booth’s recording and bit – pair recording of the number. 1000111101000101.
1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]
-1 0 0 1 0 0 0 -1 1 -1 0 0 1 -1 1 -1
-2 -1 0 -1 1 0 +1 +1
11. Draw the symbolic representation of the full adder and gibe the expression for the sum.
Xi Yi
Ci+1 Ci
Si
12. In conforming to the IEEE standard mention any four situations under which a process sets
exception flag.
1. Under flow
2. Over flow
3. Divide by Zero
4. Invalid.
13. Why floating point number is more difficult to represent and process than integer?
In floating point numbers we have to represent any number in three fields sign, exponent and mantissa.
The IEEE 754 standard gibes the format for these fields and according to format the numbers are to be
represented. In case of any process we have to consider mantissa and exponent separately. Therefore,
floating point numbers are more difficult to represent and process than integer.
14. Draw a full adder circuit and give the truth table.
Inputs Outputs
A B Cin Carry Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Full
A
Adder Sum
B
• Robertson’s algorithm
• Booth’s algorithm
Arithmetic micro operation: performs arithmetic operations on the data stored in the register
Logical micro operation: performs bit manipulation operations on the data stored in the register.
Register transfer micro operation: transfers binary information from one register to another
register
Shift micro operation: performs shift operations on the data stored in the register
CHAPTER 4
1. What are the advantages and disadvantages of hardwired and micro-programmed control?
Hardwired control
Advantages
It is implemented using the gates, Flip Flops and hardware circuits. High speed operation and hence
execution is faster
Smaller implementation (component counts)
Favored approach in RISC style designs.
Disadvantages
Complex sequencing and micro operation logic.
Difficult to design and test
Inflexible design
Difficult to add new instructions
Micro-programmed control
Advantages
It stores the control signals in the sequence in control memory.
Modification is simple by modifying the micro program in the control memory.
Just read from the control memory every clock cycle
Favored approach in CISC style designs.
Disadvantages
Execution is slow
Separate Control memory is used
3. What are the relative advantages and disadvantages of micro-programmed control over
hardwired control?
15. What are the differences between the main memory and control memory?
Ordinary user can access the main Ordinary user can not access the control
memory do modifications. memory. Only the designers can do the
same.
F1 F2 F3 CD BR AD
Where
F1, F2, F3 →Micro operation fields (3 bits each)
CD → Condition for branching (2 bits)
BR→ Branch field (2 bits)
AD → Address field (7 bits).
19. What is a hard wired logic?
If a computer is designed to operate based on the control gates, and other hard ware circuitry then it is
called hard wired control logic.
Advantages
An instruction set can be changed by changing the micro program.
Any up gradation to the existing system require only to modify the micro programs.
Less costly compared to hard wired logic.
Disadvantages
Comparatively slow.
CHAPTER 5
UNIT 3------PIPLINING
1. What is the ideal up expected in a pipelined architecture with ‘n’ stages? Justify your answer.
Ideal Speedup
Pipelining
No. of segments – k
Clock cycle time – tp
Tasks – n
It arises from resource conflicts when the hardware cannot support all possible combination of
instructions in simultaneous overlapped execution.
• Data hazards
It arises when an instruction depends on the result of a previous instruction.
• Control hazards
It arises from pipelining of branches and other instructions that change the program counter.
4. Define nanoprogramming.
Micro instructions are stored in the micro memory (control memory). There is a chance that a group
of micro instructions may occur several times in a micro program. As a result the more memory space is
needed.
By making use of the nano memory we can have significant saving in the memory when a group of
micro operations occur several times in a micro program.
These n micro instructions can be held in a separate memory called the nano memory of size nB bits.
Each of these n bits occurs once in the nano memory. Each micro instruction in the original micro
program is replaced by the address that specifies the location of the nano memory in which the original
B bit wide micro instructions are held.
The micro program control unit reads an address from the micro program. The contents of this
address in the nano memory are the desired control word. The bits in the control word are used by the
control unit to accomplish the desired operation.
The control unit employing the nano memory (two level) is slower than the one using a conventional
control memory (single memory). This is because the nano memory requires two memory reads (one for
the control memory the other for the nano memory).
5. What is pipelining?
Pipelining is a technique of decomposing a sequential process in to sub processes with each sub
process being executed in a special dedicated segment that operates concurrently with all other
programs.
R S1 R S2 R Sn R
1 2 3 N
Where
N → number of tasks.
K → number of pipeline stages.
T → clock period of linear pipeline.
18. Write down the expression for speedup factor in a pipelined architecture.
The speedup for a pipeline computer is
S = (k + n -1) tp
Where
K → number of segments in a pipeline
N → number of instructions to be executed.
Tp → cycle time
Resource conflicts → Caused by access to the memory by two at the same time. Most of the conflicts can
be resolved by using separate instruction and data memories.
Data dependency → Arises when an instruction depends on the results of the previous instruction but this
result is not yet available.
Branch difficulties → Arises from branch and other instruction that change the value of PC (Program
Counter).
CHAPTER 6
1. Distinguish between the write-through and write-back policies pointing out their merits and
demerits.
When the CPU finds a word in the cache during a read operation the main memory is not involved in the
transfer however if the operation is a write, there are two ways that the system can proceed.
The simplest and most commonly used procedure is to update main memory with every memory write
operation with cache memory being updated in parallel if it contains the word at the specified address. This
is called write-through method. This method has an advantage that main memory always contains the same
data as the cache. This care is important in systems with DMA transfers. This method is simple to
implement. This disadvantage is that it requires time to write data in main memory resulting in traffic.
The 2nd procedure is called write-back method. In this method only the cache location is updated during
a write operation. The location is then marked by a flag so that later when the block is removed from the
cache, the changes are copied in to main memory. The disadvantage is that main memory may contain
inconsistent data.
Virtual memory is an important concept related to memory management. It is used to increase the
apparent size of main memory at a very low cost. Data are addressed in a virtual address space that can be as
large as the addressing capability of CPU.
Number of Hits
Hit ratio =
Total Number of references
Number of Hits
=
Hits + Misses
4. What is meant by memory interleaving? Show the distribution of addresses for a memory system
consisting of two banks of four 1k memory modules to form an 8k memory system. Give the man
memory address format.
The memory interleaving is a more effective way to address memory modules.
The low order k bits of the memory address select a module, and high order m bits name a location
within module. Here consecutive addresses are located in consecutive modules.
M bits K bits
Address in Module Module MM Address
ABR Module
Module 0 2k - 1
Module
1
Total memory = 8k
No. of address lines = 13
1k 1k
Memory Bank 0 1k 1k Memory Bank 1
(Capacity 1K) (Capacity 1K)
1k 1k
1k 1k
Address in Module
10. In many computers the cache block size is in the range 32 to 128 bytes. What would be the main
advantages and disadvantages of making the size of the cache blocks larger or smaller?
Larger the size of the cache fewer be the cache misses if most of the data in the block are actually used.
It will be wasteful if much of the data are not used before the cache block is moved from cache. Smaller size
means more misses.
12. An eight-way set-associative cache consists of a total of 256 blocks. The main memory contains
8192 blocks, each consisting of 128 words.
1. How many bits are there in the main memory address?
2. How many bits are there in the TAG, SET and WORD fields?
The main memory contains of 256 blocks, and each block consists of 128 words.
Total words in MM = 8192 X 128 = 1048576
To address 32768 words we required (220 = 1048576) 20 bits
15. List the factors that determine the storage device performance.
The storage device performance based on the following factors:
• Address reference statistics
• Access time storage capacity
• Block size
• Allocation algorithm
16. How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes?
2 – (128 x 8) RAM Chips
Main memory:
This large, fairly fast external memory stores programs and data that are in active use. Storage locations
in main memory are addressed directly by CPU’s load and store instruction.
Secondary memory:
This is larger in capacity but much slower than main memory. Secondary memory stores systems
programs, larger data files that are not continuously required by CPU.
Cache:
Most computers have another level of IC memory-sometimes several such levels called cache memory,
which is positioned logically between the CPU registers and main memory.
36. Mention the causes of access a block of data in serial access memory.
Long access time is due to several factors.
37. How will you calculate time Tb to access a block of data in serial access memory?
The time Tb taken to access the block of data is
Tb = Ts + 1/2r + n/rN
40. Give the basic structure of cache and what is its use?
Cache and main memory form a district sub hierarchy whose design objective is to support CPU access
with a minimum of delay. Hence hardware controllers that are transparent to both user and system programs
usually manage this sub hierarchy.
The average time to move a head from one track is seek time (Ts) of the memory. Once the head is in
position, the desired cell may be in the wrong part of the moving track. Some time is required for the cell to
reach the read/write head so that data transfer can begin. The average time for this movement to take place
is the latency time (T1).
45. Mention two kinds of address locality to achieve their goal.
Two kinds address locality to achieve their goals are
• Associative addressing or content addressing.
• Direct mapping.
Processor Memory
Bus
Single-Bus Structure:
For example, if DATAIN is the address of the input buffer of keyboard, the instruction.
MOVE DATAIN, R0 – Reads the data from DATAIN and stores them into processor register R0.
Similarly if DATAOUT is the address of the output buffer of a display unit or printer, the instruction.
MOVE R0, DATAOUT – sends the data from R0 to location DATAOUT.
2. Consider a computer in which several devices are to be serviced interrupts. How do you handle
this it the processor has only one request line?
Daisy Chain:
Consider the problem of simultaneous request from two or more devices. The processor has to decide
which request to be serviced first. Polling the status register of the I/O devices is the simplest scheme.
Priority is determined by the order in which devices are polled. In daisy chain scheme, interrupt request line
INTR is common to all devices. The interrupt acknowledgement INTA, propagates serially through the
devices.
When several devices raise an interrupt request, the processor responds by setting INTA line to 1. The
signal is received by device 1. Device 1 passes the signal on to device 2 only if it does not require any
service. If device 1 has a pending request for interrupt, it blocks the INTA signal and proceeds to put its
device identifying code on the data lines. Therefore, in daisy chain arrangement, the device that is closest to
the processor has the highest priority.
Processor
INTR
4. Define Peripherals?
Peripheral refers to any external devices connected to a computer. Computer peripherals can be divided
into two categories according to their functions.
• I/O peripherals: Keyboard, Mouse, Video Display Unit, Printer.
• Storage Function: Secondary Memories, Mass Storage Device.
• Eg: CD, Hard disk, Magnetic disk, Magnetic tape.
1 0 1 2 3 4 5 6 7
LSB
0
1. ______________________
2. ______________________
i. ______________________
i+1 _____________________
_______________________
m ______________________
Assume that an interrupt request arises during execution of instruction i. steps to handle interrupt by the
processor is as follow:
1. Processor completes execution of instruction i
2. Processor saves the PC value, program status on to stack.
3. It loads the PC with starting address of ISR
4. After ISR is executed, the processor resumes the main program execution by reloading PC with
(i+1)th instruction address.
12. Why does DMA have priority over the CPU when both request a memory transfer?
Since the data transfer rate using DMA is quite higher than the CPU and memory transfer rate, the DMA
have priority over the CPU when both request a memory transfer.
23. Why the DMA does gets priority over CPU when both request memory transfer.
The CPU can wait to fetch instruction and data from the memory with out any damage occurring except
that the loss of time. DMA usually transfers data from a device that can’t be stopped since information
continues to flow so loss of data may occur.