Professional Documents
Culture Documents
Data Sheet
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been
made are the result of normal data sheet improvement and are noted in the document revision summary.
Revision E
Amendment 8
D at a
S hee t
Am29F400B
DATA SHEET
Am29F400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit)
CMOS 5.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
Single power supply operation
5.0 volt-only operation for read, erase, and
program operations
Minimizes system level requirements
Manufactured on 0.32 m process technology
Compatible with 0.5 m Am29F400 device
High performance
Access times as fast as 45 ns
Low power consumption (typical values at
5 MHz)
Embedded Algorithms
Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
Embedded Program algorithm automatically
writes and verifies data at specified addresses
Minimum 1,000,000 program/erase cycles per
sector guaranteed
20-year data retention at 125 C
Reliable operation for the life of the system
Package option
48-pin TSOP
44-pin SO
30 mA program/erase current
Flexible sector architecture
This Data Sheet states AMDs current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
D A T A
S H E E T
GENERAL DESCRIPTION
The Am29F400B is a 4 Mbit, 5.0 volt-only Flash
memory organized as 524,288 bytes or 262,144 words.
The device is offered in 44-pin SO and 48-pin TSOP
packages. The device is also available in Known Good
Die (KGD) form. For more information, refer to publication number 21258. The word-wide data (x16) appears
on DQ15DQ0; the byte-wide (x8) data appears on
DQ7DQ0. This device is designed to be programmed insystem with the standard system 5.0 volt VCC supply. A 12.0
V VPP is not required for write or erase operations. The
device can also be programmed in standard EPROM
programmers.
This device is manufactured using AMDs 0.32 m
process technology, and offers all the features and benefits of the Am29F400, which was manufactured using
0.5 m process technology.
The standard device offers access times of 45, 50, 55,
70 and 90 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus contention
the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a single 5.0 volt power
supply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command register using
standard microprocessor write timings. Register contents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithman internal algorithm that automatically times the program pulse widths and verifies
proper cell margin.
Am29F400B
D A T A
S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .
Device Bus Operations . . . . . . . . . . . . . . . . . . . . .
4
4
5
6
6
7
8
Command Definitions . . . . . . . . . . . . . . . . . . . . . 13
Reading Array Data ................................................................ 13
Reset Command ..................................................................... 13
Autoselect Command Sequence ............................................ 13
Word/Byte Program Command Sequence ............................. 13
Figure 2. Program Operation .......................................................... 14
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23
TTL/NMOS Compatible .......................................................... 23
CMOS Compatible .................................................................. 24
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 8. Test Setup....................................................................... 25
Table 7. Test Specifications ........................................................... 25
...................................... 28
30
31
32
32
33
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 22
Am29F400B
D A T A
S H E E T
Am29F400B
VCC = 5.0 V 5%
-45
-50
-55
-55
-70
-90
45
50
55
70
90
45
50
55
70
90
30
30
30
30
35
BLOCK DIAGRAM
DQ0DQ15 (A-1)
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
RESET#
WE#
BYTE#
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
Address Latch
STB
Timer
A0A17
Am29F400B
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
D A T A
S H E E T
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21258 for
more information.
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SO
Am29F400B
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
D A T A
PIN CONFIGURATION
A0A17
S H E E T
LOGIC SYMBOL
= 18 addresses
18
A0A17
DQ0DQ15
(A-1)
BYTE#
CE#
= Chip enable
OE#
= Output enable
CE#
WE#
= Write enable
OE#
RESET#
WE#
RY/BY#
= Ready/Busy# output
VCC
VSS
= Device ground
NC
16 or 8
RESET#
BYTE#
Am29F400B
RY/BY#
D A T A
S H E E T
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
Am29F400B
-45
F
OPTIONAL PROCESSING
Blank = Standard Processing
0
= VCC = 5.0 V 10%, 55 ns device only
(Contact an AMD representative for more information)
TEMPERATURE RANGE
I
= Industrial (40 C to +85 C)
F
= Industrial (40 C to +85 C) with Pb-Free Package
E
= Extended (55 C to +125 C)
K
= Extended (55 C to +125 C) with Pb-free Package
PACKAGE TYPE
E
= 48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
S
= 44-Pin Small Outline Package (SO 044)
This device is also available in Known Good Die (KGD) form. See publication number
21258 for more information.
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T
=
Top sector
B
=
Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29F400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory
5.0 Volt-only Read, Program and Erase
Valid Combinations
AM29F400BT-45,
AM29F400BB-45,
AM29F400BT-50,
AM29F400BB-50
AM29F400BT-55,
AM29F400BB-55
AM29F400BT-55,
AM29F400BB-55
AM29F400BT-70,
AM29F400BB-70
AM29F400BT-90,
AM29F400BB-90
Voltage
Range
EI, EF,
SI, SF
5.0 V 5%
EI, EF, EE, EK
SI, SF, SE, SK
EI0,
EF0, EE0, EK0,
SI0,
SF0, SE0, SK0
5.0 V 10%
EI,
EF, EE, EK
SI,
SF, SE, SK
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am29F400B
D A T A
S H E E T
CE#
OE#
WE#
RESET#
A0A17
DQ0DQ7
BYTE#
= VIH
BYTE#
= VIL
Read
AIN
DOUT
DOUT
High-Z
Write
AIN
DIN
DIN
High-Z
VCC
0.5 V
VCC
0.5 V
High-Z
High-Z
High-Z
CMOS Standby
TTL Standby
High-Z
High-Z
High-Z
Output Disable
High-Z
High-Z
High-Z
Hardware Reset
High-Z
High-Z
High-Z
VID
AIN
DIN
DIN
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Dont Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note:See the sections onSector Group Protection and Temporary Sector Unprotect for more information.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic 1, the device is in
word configuration, DQ15DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte
configuration, and only data I/O pins DQ0DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Am29F400B
D A T A
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7DQ0. Standard read cycle timings apply
in this mode. Refer to the Autoselect Mode and
Autoselect Command Sequence sections for more
information.
ICC2 in the DC Characteristics table represents the
active current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC 0.5 V.
(Note that this is a more restricted voltage range than
VIH.) The device enters the TTL standby mode when
CE# and RESET# pins are both held at VIH. The device
requires standard access time (tCE) for read access
when the device is in either of these standby modes,
before it is ready to read data.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
RESET#: Hardware Reset Pin.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
S H E E T
In the CMOS and TTL/NMOS-compatible DC Characteristics tables, ICC3 represents the standby current
specification.
Am29F400B
D A T A
Table 2.
S H E E T
Sector
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/ Kwords)
(x8)
Address Range
(x16)
Address Range
SA0
64/32
00000h0FFFFh
00000h07FFFh
SA1
64/32
10000h1FFFFh
08000h0FFFFh
SA2
64/32
20000h2FFFFh
10000h17FFFh
SA3
64/32
30000h3FFFFh
18000h1FFFFh
SA4
64/32
40000h4FFFFh
20000h27FFFh
SA5
64/32
50000h5FFFFh
28000h2FFFFh
SA6
64/32
60000h6FFFFh
30000h37FFFh
SA7
32/16
70000h77FFFh
38000h3BFFFh
SA8
8/4
78000h79FFFh
3C000h3CFFFh
SA9
8/4
7A000h7BFFFh
3D000h3DFFFh
SA10
16/8
7C000h7FFFFh
3E000h3FFFFh
Table 3.
Sector
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
SA0
16/8
00000h03FFFh
00000h01FFFh
SA1
8/4
04000h05FFFh
02000h02FFFh
SA2
8/4
06000h07FFFh
03000h03FFFh
SA3
32/16
08000h0FFFFh
04000h07FFFh
SA4
64/32
10000h1FFFFh
08000h0FFFFh
SA5
64/32
20000h2FFFFh
10000h17FFFh
SA6
64/32
30000h3FFFFh
18000h1FFFFh
SA7
64/32
40000h4FFFFh
20000h27FFFh
SA8
64/32
50000h5FFFFh
28000h2FFFFh
SA9
64/32
60000h6FFFFh
30000h37FFFh
SA10
64/32
70000h7FFFFh
38000h3FFFFh
Note:
Address range is A17:A-1 in byte mode and A17:A0 in word mode.See the Word/Byte Configuration section for more
information.
Autoselect Mode
The autoselect mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on DQ7DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Table 4. In addition, when verifying sector protection,
10
Am29F400B
D A T A
Table 4.
Description
Mode
CE#
OE#
Device ID:
Am29F400B
(Top Boot Block)
Word
Byte
Device ID:
Am29F400B
(Bottom Boot Block)
Word
A6
A5
to
A2
A1
A0
DQ8
to
DQ15
DQ7
to
DQ0
01h
22h
23h
23h
22h
ABh
ABh
01h
(protected)
00h
(unprotected)
VID
VID
VID
A9
A8
to
A7
X
Byte
S H E E T
SA
VID
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Dont care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Figure 1.
Am29F400B
11
D A T A
12
S H E E T
proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Am29F400B
D A T A
S H E E T
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 5 defines the valid register command
sequences. Writing incorrect address and data
values or writing them in the improper sequence
resets the device to reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
AC Characteristics section.
Reset Command
Am29F400B
13
D A T A
addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See The Erase Resume
command is valid only during the Erase Suspend
mode. for information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programmin g o pe ra ti on . T he B y te P ro gra m c om ma nd
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a 0 back to a 1. Attempting to do so may halt
the operation and set DQ5 to 1, or cause the Data#
Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the
data is still 0. Only erase operations can convert a 0
to a 1.
Write Program
Command Sequence
No
Last Address?
Yes
Programming
Completed
Note:
See Table 5 for program command sequence.
14
Yes
Figure 2.
Figure 3 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in AC
Characteristics for parameters, and to Figure 14 for
timing diagrams.
Data Poll
from System
Verify Data?
Increment Address
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See The
Erase Resume command is valid only during the Erase
Suspend mode. for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched.
START
Embedded
Program
algorithm
in progress
S H E E T
Program Operation
No
Am29F400B
D A T A
s, otherwise the last address and command might not
be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 s, the system need not monitor DQ3. Any
command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
rewrite the command sequence and any additional
sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the DQ3: Sector Erase
Timer section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
S H E E T
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, DQ2,
or RY/BY#. (Refer to The Erase Resume command is
valid only during the Erase Suspend mode. for information on these status bits.)
Figure 3 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in
the AC Characteristics section for parameters, and to
Figure 14 for timing diagrams.
Am29F400B
15
D A T A
S H E E T
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See Autoselect Command Sequence
for more information.
The system must write the Erase Resume command
(address bits are dont care) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the
device has resumed erasing.
START
Write Erase
Command Sequence
Data Poll
from System
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 5 for erase command sequence.
2. See DQ3: Sector Erase Timer for more information.
16
Embedded
Erase
algorithm
in progress
Am29F400B
Figure 3.
Erase Operation
D A T A
Cycles
Table 5.
Command
Sequence
(Note 1)
Read (Note 6)
Reset (Note 7)
Autoselect (Note 8)
Manufacturer ID
Word
Byte
Device ID,
Top Boot Block
Word
Device ID,
Bottom Boot Block
Word
Byte
Byte
Data
RD
XXX
F0
4
4
Chip Erase
Sector Erase
555
AAA
555
AAA
555
AAA
Byte
Word
Byte
Word
Byte
AA
AA
AA
555
4
Word
Second
RA
Byte
Program
Word
Sector Protect Verify
(Note 9)
6
6
Addr
2AA
555
2AA
555
2AA
555
AA
555
AAA
555
AAA
555
AAA
Third
Data
AAA
555
55
AAA
555
55
AAA
55
AA
AA
XXX
B0
XXX
30
2AA
555
2AA
555
2AA
555
Fourth
Data Addr
90
90
90
555
AAA
555
55
AAA
555
55
AAA
555
55
AAA
A0
80
80
Data
X00
01
X01
2223
X02
23
X01
22AB
X02
AB
(SA)
X02
XX00
(SA)
X04
00
PA
PD
90
555
AA
Addr
555
55
2AA
AAA
4
S H E E T
555
AAA
555
AAA
Fifth
Sixth
Addr Data
Addr
Data
XX01
01
AA
AA
2AA
555
2AA
555
55
55
555
AAA
SA
10
30
Legend:
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
X = Dont care
RA = Address of the memory location to be read.
Notes:
1. See Table 1 for description of bus operations.
11. The Erase Resume command is valid only during the Erase
Suspend mode.
Am29F400B
17
D A T A
S H E E T
START
Read DQ7DQ0
Addr = VA
DQ7 = Data?
No
No
18
DQ5 = 1?
Yes
Read DQ7DQ0
Addr = VA
Yes
DQ7 = Data?
Yes
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1 because
DQ7 may change simultaneously with DQ5.
Am29F400B
Figure 4.
D A T A
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied together in parallel
with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 6 shows the outputs for RY/BY#. Figures 10,
Figure 13 and Figure 14 shows RY/BY# for reset, program, and erase operations, respectively.
S H E E T
Table 6 shows the outputs for Toggle Bit I on DQ6.
Figure 5 shows the toggle bit algorithm. Figure 16 in the
AC Characteristics section shows the toggle bit timing
diagrams. Figure 17 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.
Am29F400B
19
D A T A
S H E E T
START
Read DQ7DQ0
No
20
Toggle Bit
= Toggle?
No
DQ5 = 1?
Yes
Read DQ7DQ0
Twice
(Note 1)
Yes
Read DQ7DQ0
Toggle Bit
= Toggle?
(Notes
1, 2)
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to 1. See text.
Figure 5.
Am29F400B
D A T A
S H E E T
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
RY/BY#
DQ7#
Toggle
N/A
No toggle
Toggle
Toggle
No toggle
N/A
Toggle
Data
Data
Data
Data
Data
Erase-Suspend-Program
DQ7#
Toggle
N/A
N/A
Operation
Standard
Mode
Erase
Suspend
Mode
Notes:
1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See DQ5: Exceeded Timing Limits for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
Am29F400B
21
D A T A
S H E E T
20 ns
20 ns
+0.8 V
0.5 V
2.0 V
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . 40C to +85C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . 55C to +125C
VCC Supply Voltages
VCC for 5% devices . . . . . . . . . . .+4.75 V to +5.25 V
VCC for 10% devices . . . . . . . . . . . .+4.5 V to +5.5 V
Note:Operating ranges define those limits between which the
functionality of the device is guaranteed.
22
Am29F400B
D A T A
S H E E T
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Description
Test Conditions
ILI
ILIT
ILO
ICC1
Min
Typ
Max
Unit
1.0
50
1.0
19
40
mA
19
50
mA
ICC2
36
60
mA
ICC3
0.4
mA
VIL
0.5
0.8
VIH
2.0
VCC
+0.5
VID
VCC = 5.0 V
11.5
12.5
VOL
0.45
VOH
VLKO
2.4
3.2
V
4.2
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH..
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Not 100% tested.
Am29F400B
23
D A T A
S H E E T
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
ILI
ILIT
ILO
ICC1
Min
Typ
20
Max
Unit
1.0
50
1.0
40
mA
28
50
ICC2
30
50
mA
ICC3
0.3
VIL
0.5
0.8
VIH
0.7 x
VCC
VCC+
0.3
VID
VCC = 5.0 V
11.5
12.5
VOL
0.45
VOH1
0.85
VCC
VCC0.
4
3.2
4.2
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Not 100% tested.
5. ICC3 = 20 A max at extended temperature (>+85 C).
24
Am29F400B
D A T A
S H E E T
TEST CONDITIONS
Table 7.
Test Specifications
5.0 V
-45,
-50, -55
Test Condition
2.7 k
Device
Under
Test
CL
Output Load
Unit
1 TTL gate
30
100
pF
20
ns
0.03.0
0.452.4
1.5
0.8, 2.0
1.5
0.8, 2.0
6.2 k
Input Pulse Levels
Note:
Diodes are IN3064 or equivalent.
Figure 8.
All
others
Test Setup
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Am29F400B
25
D A T A
S H E E T
AC CHARACTERISTICS
Read Operations
Parameter
Speed Options
JEDEC
Std
Description
tAVAV
tRC
tAVQV
tACC
tELQV
tCE
tGLQV
tOE
tEHQZ
tGHQZ
tAXQX
Test Setup
-45
-50
-55
-70
-90
Unit
Min
45
50
55
70
90
ns
CE# = VIL
OE# = VIL
Max
45
50
55
70
90
ns
OE# = VIL
Max
45
50
55
70
90
ns
Max
30
30
30
30
35
ns
tDF
Max
15
15
15
20
20
ns
tDF
Max
15
15
15
20
20
ns
Read
Min
ns
Toggle and
Data# Polling
Min
10
ns
Min
ns
tOEH
Output Enable
Hold Time
(Note 1)
tOH
Notes:
1. Not 100% tested.
2. See Figure 8 and Table 7 for test specifications.
tRC
Addresses Stable
Addresses
tACC
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0V
Figure 9.
26
Am29F400B
D A T A
S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Test Setup
Unit
tREADY
Max
20
tREADY
Max
500
ns
tRP
Min
500
ns
tRH
Min
50
ns
tRB
Min
ns
Note:
Not 100% tested.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 10.
RESET# Timings
Am29F400B
27
D A T A
S H E E T
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter
JEDEC
Std
Speed Options
Description
-45
-50
-55
-70
-90
Unit
tELFL/tELFH
Max
tFLQZ
Max
15
15
15
20
20
ns
tFHQV
Min
45
50
55
70
90
ns
ns
CE#
OE#
BYTE#
BYTE#
Switching
from word
to byte
mode
tELFL
Data Output
(DQ0DQ7)
Data Output
(DQ0DQ14)
DQ0DQ14
Address
Input
DQ15
Output
DQ15/A-1
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte
to word
mode
Data Output
(DQ0DQ7)
DQ0DQ14
Address
Input
DQ15/A-1
Data Output
(DQ0DQ14)
DQ15
Output
tFHQV
Figure 11.
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS)
tHOLD (tAH)
Note:
Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 12.
28
Am29F400B
D A T A
S H E E T
AC CHARACTERISTICS
Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
-45
-50
-55
-70
-90
Unit
tAVAV
tWC
Min
45
50
55
70
90
ns
tAVWL
tAS
Min
tWLAX
tAH
Min
45
45
45
45
45
ns
tDVWH
tDS
Min
25
25
25
30
45
ns
tWHDX
tDH
Min
ns
tOES
Min
ns
Min
ns
ns
tGHWL
tGHWL
tELWL
tCS
Min
ns
tWHEH
tCH
Min
ns
tWLWH
tWP
Min
tWHWL
tWPH
Min
20
Typ
tWHWH1
Byte
tWHWH1
Word
Typ
12
tWHWH2
tWHWH2
Typ
sec
tVCS
Min
50
tRB
Min
ns
Max
tBUSY
30
30
30
35
45
ns
ns
s
30
30
30
30
35
ns
Notes:
1. Not 100% tested.
2. See the Erase and Programming Performance section for more information.
Am29F400B
29
D A T A
S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
A0h
Data
PD
Status
tBUSY
DOUT
tRB
RY/BY#
tVCS
VCC
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 13.
30
Am29F400B
D A T A
S H E E T
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
SA
VA
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status).
2. Illustration shows device in word mode.
Figure 14.
Am29F400B
31
D A T A
S H E E T
AC CHARACTERISTICS
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ0DQ6
Status Data
Status Data
Valid Data
True
High Z
Valid Data
True
tBUSY
RY/BY#
Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 15.
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ6/DQ2
tBUSY
Valid Status
Valid Status
(first read)
(second read)
Valid Status
Valid Data
(stops toggling)
RY/BY#
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
Figure 16.
32
Am29F400B
D A T A
S H E E T
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Erase
WE#
Enter Erase
Suspend Program
Erase
Resume
Erase
Suspend
Program
Erase Suspend
Read
Erase
Complete
Erase
Erase Suspend
Read
DQ6
DQ2
Note:
The system may use either CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 17.
Std
Description
tVIDR
tRSP
Unit
Min
500
ns
Min
12 V
RESET#
0 or 5 V
0 or 5 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Am29F400B
33
D A T A
S H E E T
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
-45
-50
-55
-70
-90
Unit
tAVAV
tWC
Min
45
50
55
70
90
ns
tAVEL
tAS
Min
tELAX
tAH
Min
45
45
45
45
45
ns
tDVEH
tDS
Min
25
25
25
30
45
ns
tEHDX
tDH
Min
ns
tOES
Min
ns
tGHEL
tGHEL
Min
ns
tWLEL
tWS
Min
ns
tEHWH
tWH
Min
ns
tELEH
tCP
Min
tEHEL
tCPH
Min
20
Typ
tWHWH1
Programming Operation
(Note 2)
Byte
tWHWH1
Word
Typ
12
tWHWH2
tWHWH2
Typ
30
30
30
ns
35
45
ns
ns
s
sec
Notes:
1. Not 100% tested.
2. See the Erase and Programming Performance section for more information.
34
Am29F400B
D A T A
S H E E T
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tCP
CE#
tWS
tWHWH1 or 2
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.
Figure 19.
Am29F400B
35
D A T A
S H E E T
Typ (Note 1)
Max (Note 2)
Unit
1.0
11
300
12
500
Byte Mode
3.6
10.8
(Note 3)
Word Mode
3.1
9.3
Comments
Excludes 00h programming
prior to erasure
Notes:
1. Typical program and erase times assume the following conditions: 25 C, 5.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90C, VCC = 4.5 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
1.0 V
12.5 V
1.0 V
VCC + 1.0 V
100 mA
+100 mA
VCC Current
Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
7.5
pF
COUT
Output Capacitance
VOUT = 0
8.5
12
pF
CIN2
VIN = 0
7.5
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
Min
Unit
150 C
10
Years
125 C
20
Years
36
Am29F400B
D A T A
S H E E T
PHYSICAL DIMENSIONS
TS 04848-Pin Standard Thin Small Outline Package
Am29F400B
37
D A T A
S H E E T
PHYSICAL DIMENSIONS
SO 04444-Pin Small Outline Package
38
Am29F400B
D A T A
S H E E T
REVISION SUMMARY
Revision A (August 1997)
Initial release.
Global
Global
AC Characteristics
DC CharacteristicsTTL/NMOS Compatible
Deleted Note 4.
Distinctive Characteristics
High Performance: Changed Access times as fast as
55 ns to Access times as fast as 45 ns.
Am29F400B
39
D A T A
S H E E T
General Description
Global
Ordering Information
DC Characteristics
Removed VCC = VCC max test condition for ICC1 ICC3.
VCC max is only valid for max specs.
AC Characteristics
Deleted 150 ns speed option and reverse TSOP package from document.
AC Characteristics
Ordering Information
Added extended temperature combinations to the -55,
10% speed option.
Global
Distinctive Characteristics
Added:
Global
DC CharacteristicsCMOS Compatible
Global
40
Am29F400B
D A T A
S H E E T
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright 19972005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered
trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks
of their respective companies.
Copyright 2006-2009 Spansion Inc. All rights reserved. Spansion, the Spansion logo, MirrorBit, MirrorBit Eclipse, ORNAND,
EcoRAM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries.
Other names used are for informational purposes only and may be trademarks of their respective owners.
Am29F400B
41