Registration Fee*

REGISTRATION FORM
Name

Designation

Organization

Address for
Communication

Faculty / Industry Persons

Rs.2290/-

Students & Full Time

Research Scholars
Accommodation (2 days)

Rs.1718/Rs. 630/-

Two Day National Workshop

*inclusive of 14.5% GST

(Registration fee Includes working lunch and snacks)

Certificate will be issued to all the registered participants. DD in favour of VIT University payable at

Phone Number

E-mail ID

Accommodation

: Yes/No

Venue

Amount

Room No. 237, Technology Tower,

DD No. & Date

Bank Name/Branch

Vellore.

on

VLSI Design
Verification and Testing
18th and 19th March 2016

VIT University, Vellore

Important Dates
Last Date for Registration : 16th-March, 2016.

Place:
Date:

Workshop Dates
Signature of Participant

Participants can also register for the workshop by filling

up an online registration form:

http://goo.gl/forms/PO1h1zLOj1
Application will be accepted on a first come first serve
basis. Number of participants is limited to 50.

Address for Correspondence

Dr. S. Sivanantham
Associate Professor
Department of Micro and Nanoelectronics
School of Electronics Engineering
VIT University, Vellore-632 014
Tamilnadu, India

: March 18-19, 2016

Organizing Coordinators
Dr. Sivanantham S, Associate Professor
Email: ssivanantham@vit.ac.in

contact No: +91 9894432359

Prof. Prayline Rajabai C, Assistant Professor

Email: prayline.c@vit.ac.in

contact No: +91 7200577872

Organized by

Department of Micro and Nanoelectronics

School of Electronics Engineering
VIT University
Vellore 632 014
Tamilnadu, India

ABOUT VIT UNIVERSITY

VIT University was established with the aim of providing quality higher education on par with international
standards. It persistently seeks and adopts innovative
methods to improve the quality of higher education on a
consistent basis. The campus has a cosmopolitan atmosphere with students from all corners of the globe. Experienced and learned teachers are strongly encouraged to
nurture the students. The global standards set at VIT in
the field of teaching and research spur us on in our relentless pursuit of excellence. In fact, it has become a
way of life for us. The highly motivated youngsters on
the campus are a constant source of pride. Our MoU
with various international universities are our major
strength.
LAB FACILITIES
VLSI Laboratory is equipped with facilities to perform
digital, analog, mixed signal and RFIC design using
EDA tools like Cadence and Synopsys (Full custom
design and ASIC design with DFT) each with 65 user
licenses; Xilinx ISE Suite, Altera Design Suite (FPGA
based system design); Synopsys TCAD Tools for simulating device performance; Hardware platforms like Al-

ABOUT THE WORKSHOP

The program is intended for the Faculty, PG students,

Basics of VLSI Testing

R & D in the field of testing and verification of VLSI

Automatic Test Pattern and Fault simulation

Design. The main objective of the program is to provide

DFT Scan and BIST methodology

Hands-on session on the following opics:

basic fundamentals of different testing and verification

methods along with hands-on practice and advances.

Fault Simulation

RESOURCE PERSONS

ATPGA

Dr. S. Sivanantham,

Test Synthesis using Cadence RTL Compiler

Scan Insertion

VIT University, Vellore.

Dr.B.Ramkumar
DFT Engineer, Bangalore
Mr.Sravan Kumar
Sr Verification Engineer, Bangalore

Test generation using Cadence EncounterTest

Research Aspects in VLSI Testing

DAY 2 : VLSI DESIGN VERIFICATION

SystemVerilog - Overview for Design Verification

Functional Verification Approaches

Prof. Prayline Rajabai C

Object-Oriented Programming

VIT University, Vellore.

Assertions

Randomization

Functional Coverage

Hands-on Training on Functional Verification

Universal Verification methodology

TOOLS USED FOR WORKSHOP

FPGA Kit and Virtex-5 OpenSPARC Evaluation Plat-

Verification : Modelsim and Cadence ncsim

form. We have partners with various semiconductor

Testing

Belgium through Europractice.

DAY 1 : VLSI TESTING

research scholars, practicing engineers and people from

tera-DE3 and DE2 FPGA board, Xilinx Spartan 3E

foundries to access technology design kits with IMEC-

TOPICS TO BE COVERED

: Encounter RTL Compiler and

Encounter Test from Cadence