INTEGRATED CIRCUIT

LAYOUT
IL2222- Digital Circuit Design for Nanoscale CMOS

NASIM FARAHINI

OUTLINE
Introduction
Layout of a single transistor and the design metrics

Design rules
Manufacturability issues and related rules
Stick diagram

Standard-cell layout design methodology

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Summary

INTRODUCTION
System Specification

Architectural Design

Logic Design

Circuit Design

Physical Verification
and Signoff

Fabrication

The LAYOUT of an IC
defines the geometry of
the masks used in
fabrication.

Packaging and Testing

CELL-BASED DESIGN VS. FULL CUSTOM

Two prevalent methods for VLSI physical design:

Standard-cell based design:

Pre-physically designed commonly used

logic cells which are characterized and stored
in standard cell libraries.
Used in Electronic Design Automation
Routing of inter-cell connections

Full-custom design:
Design using MOSFETs at the lowest level
Manual placement of the transistors and wiring.
Advantages: Less area, Better performance, Less power
Disadvantages: High engineering effort, Long time-to-market, High
development cost
Mostly used when

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The same layout design is replicated like memory cells

High volume products like high-performance processors

LAYOUT
Layout designer should consider

manufacturability metrics
Performance constraints
Size of the IC
Parasitic elements

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CMOS PROCESS LAYERS AND MASKS

MASKS

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Layout (Mask) view of an inverter

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CMOS PROCESS LAYERS

SINGLE TRANSISTOR LAYOUT

A CMOS transistor is the crossing of two rectangles, polysilicon
and active area.

Make connections to the source and drain.

Connect the substrate of the NMOS to GND and that of the
PMOS to the VDD to keep the source, drain junctions
reversed biased with respect to the substrate.
L

Well Bias

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SINGLE TRANSISTOR LAYOUT

The key points to consider when drawing a transistor layout:
1) Parasitic resistance at source and drain must be kept
as low as possible
2) Parasitic capacitances should be minimized

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3) Matching between paired elements is very important

1) SOURCE AND DRAIN RESISTANCE

Multiple contacts or one big contact?

Voltage drop because of the sheet resistance of the drain/source

Manufacturers prefer contacts with fixed size
Less reliability using a big contact.

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2) PARASITIC CAPACITANCE IN TRANSISTOR

Analog transistors often have a large W/L ratio

Diffusion-substrate capacitance

Resistance of poly gate

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MULTI-FINGER TRANSISTORS

3) MATCHING TRANSISTORS
Regular (rectangular shape)

Parallel elements

The W and L matter!!

Silicon is unisotropic

The current flowing in the

same direction

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INTERDIGITATED DEVICES
Two matched transistors with one node in common

Split them in equal part of fingers ( for example 4)

Interdigitate the 8 elements: AABBAABB or ABBAABBA
Most likely both transistors experience the same fabrication
process variations

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DESIGN RULES
Design rules: The interface between the designer and
process engineer

Guidelines about the geometry constraints for constructing

process masks

Main objective: To build reliably functional circuits in as small

an area as possible.

A compromise between performance and yield

More conservative rules increase probability of correct circuit

function (yield)
More aggressive rules increase circuit performance ( area,
power, delay)

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DESIGN RULES
Design rules are described in two ways:

Lambda based rules:

Known as scalable rules as all of the rules are first order scaling
of a constant parameter ().
2 is equal to the minimum channel length
Moving from one process to another requires only a change in
with some modifications.
In general, process rarely shrinks uniformly.

Micron based rules:

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All minimum sizes and spacings specified in microns.

Rules dont have to be multiples of .
Can result in 50% reduction in area over based rules.

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DESIGN RULES
Different types of design rules:

Intra-layer rules

Width, spacing
Inter-layer rules

Enclosures, distances, extensions, overlaps

Specific rules
Antenna rules, density rules, minimum area

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INTRA-LAYER DESIGN RULES

Minimum spacing between the active area and the well

boundaries.

Gate overlap of the active area

Active area overlap of the gate

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INTER-LAYER: TRANSISTOR LAYOUT

INTER-LAYER: CONTACT AND VIA

Contact: Forms interconnection between metal and active or

polysilicon

VIA: Connects two metal layers

Undersize VIA has too much resistance
VIA may be too large and create short

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Antenna effect: When metal wire contacted to transistor gate is

etched, it can charge up to a sufficient voltage to break down
thin gate oxides.

Metal can be contacted to diffusion to provide a path for the

charge to bleed away.

Antenna rule: Specify maximum area of metal that can be

connected to a gate without a source or drain to act as a
discharge element

Violations can be fixed by using diffusion diodes or by

shortening the metal segments using additional VIAs.

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SPECIFIC RULES: 1) ANTENNA RULES

2) LAYER DENSITY RULES

For advanced processes, a minimum and maximum density

of a particular layer within a specific area should be
specified.

Required to achieve uniform etch rates when using the CMP

(Chemical-mechanical planarization) process

CMP is a process of smoothing surfaces

with the combination of chemical and

As an example a metal layer might have a 30% minimum

and 70% maximum fill with a 1mm by 1mm area.

Poly and metal fillers should be added when a design is

completed.

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mechanical forces

LITHO-FRIENDLY LAYOUT DESIGN

Electrical short and open

were caused by lithography
process variation

The foundry provides the designer with a Litho-Friendly

Design (LFD) kit for the process in the same manner as a DRC
kit.

The designer uses the feedback from the lithography simulation

tool to improve the layout.
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The lithography simulation tool identifies layout hotspots

(structures with a higher probability of failing due to lithography
process variations).

ELECTROMIGRATION
Electromigration is the movement of the lattice ions of the
interconnect material as the result of the momentum transfer
form electrons.

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High current density or irregular shapes for the interconnects

may cause the electromigration to happen in a short time.

VERIFYING THE LAYOUT

Ensure that none of the design rules are not violated.

Computer-Aided Design Rule Checker (DRC)

Online DRC for complicated designs

Some of the products in the DRC area of the EDA are:

Hercules

Assura
Design Rule
Checkers

Guardian

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Quartz

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Calibre

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CELL DESIGN

CHIP PLANNING: STICK DIAGRAM

Shows all
transistors

Does not show exact placement, transistor sizes, wire

lengths, wire widths, boundaries, etc. Shows relative
positioning.

Useful for interconnect visualization, preliminary layout,

power/ground routing or reordering the inputs.

and

relative

positions

of

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components

REORDERING INPUTS
Two versions of C.(A+B)

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Standard cells: layouts of library cells including logic

elements like gates, flip-flops, and ALU functions.

The height of the cells are constant.

Direction of the poly gates should be vertical with respect

to the power rails.

The wires of each metal layer can run either horizontally or

vertically.

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STANDARD-CELL LAYOUT METHODOLOGY

STANDARD CELLS

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Inverter

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STANDARD CELLS

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STANDARD CELLS

Draw MOS-transistor diagram.

What logic function does this circuit implement?

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DESIGN EXAMPLE

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DESIGN EXAMPLE

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DESIGN EXAMPLE

REFERENCES
1) Christopher Saint, Judy Saint, IC mask design: essential
layout techniques, McGraw-Hill, 2002.
2) Christopher Saint, Judy Saint , IC layout basics: A practical
guide, McGraw-Hill, 2002.

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3) R. Jacob Baker, CMOS: Circuit Design, Layout, and

Simulation, John Wiley & Sons, 2010.

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Laborations

Date

Time

Lab 1

2011-11-10

13.00-17.00

Lab 2

2011-11-24

13.00-17.00

Lab 3

2011-12-01

13.00-17.00

Lab 4

2011-12-08

13.00-17.00

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LABORATIONS

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Thank you for your attention!