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ISSN: 2231-5381
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International Journal of Engineering Trends and Technology (IJETT) - Volume4Issue4- April 2013
inverter is obtained by taking the repeating sequence(triangular wave)as the control signal and
comparing it with the reference wave(sinusoidal
wave).In order to detect or eliminate the zero sequence currents we use zero hold circuit and by comparing the with the help of greater than or equal to
blocks.
III.SIMULATION CIRCUIT FOR SINUSOIDAL
PWM
ISSN: 2231-5381
The SVPWM [4] can be implemented by using wither sector selection algorithm or by using a carrier
based space vector algorithm. The types of SVPWM
implementations are: a) Sector selection based space
vector modulation b) Reduced switching Space vector modulation c) Carrier based space vector modulation d) Reduced switching carrier based space vector
modulation.
VII. STEPS TO IMPLEMENT SVPWM, THE
CONVENTIONAL METHOD
1) The sector in which the tip of the reference sector
is situated is to be determined from the instantaneous
phase references Va *, Vb * and Vc*
Va *, Vb *, Vc * v,v = Tan-1(v /
v)
= - k(600) ; k such that < 60 0
Sector number = k + 1
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International Journal of Engineering Trends and Technology (IJETT) - Volume4Issue4- April 2013
Step-1: Sector identification
By comparing the stationary frame d-q components
of the reference voltage vector, the sector where the
reference voltage vector is located is identified.
Step-2: Calculating the effective times
T
T
T
Tas s va* ; Tbs s vb* ; Tcs s vc*
Vdc
Vdc
Vdc
The active vector switching times T1 and T2 in sector1 may be expressed as:
( Vdc sin600 ) * T2
( Vsr sin ) * Ts
T1
T
| v sr | T s sin( / 3 )
V dc sin( / 3 )
| v sr | T s sin
V dc sin( / 3 )
; T2
2Tsv
3Vdc
Substituting
3
2
*
a
Tmax Tmin
The offset time, Toffset required to distribute the
zero voltage symmetrically during one sampling period is given by:
T0
Tmin
2
3
( v b* v c* )
2
Ts (va* vb* )
Ts (vb* vc* )
T1
; T2
Vdc
Vdc
ISSN: 2231-5381
Toffset
T1
During (0<Wt<30)
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International Journal of Engineering Trends and Technology (IJETT) - Volume4Issue4- April 2013
VAO,avg
VBO,avg
Vdc / 2 T0
T
T1 T2 0
Ts 2
2
V /2 T
T
dc 0 T1 T2 0
Ts 2
2
VCO,avg
Vdc / 2 T0
T
T1 T2 0
Ts 2
2
V
2 3
Vph, peak,max * *Vdc dc 0.577*Vdc
3 2
3
During (30<Wt<90)
VAO,avg
Vdc / 2 T0
T
T1 T2 0
Ts 2
2
VBO,avg
Vdc / 2 T0
T
T1 T2 0
Ts 2
2
VCO,avg
Vdc / 2 T0
T
T1 T2 0
Ts 2
2
V /2 V
T
VAO,avg dc * sr * s 0 sin(600 ) sin
Ts
Vdc
sin60
t 30
t 30 0 simplifying
when
Noting that
t 30
when
30 0 t 90 0
simplifying
V AO , avg
Vsr
3
Sin ( t 30 0 )
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International Journal of Engineering Trends and Technology (IJETT) - Volume4Issue4- April 2013
Fig:5 fft analysis of spwm
XIII. CONCLUSION
Compared to SPWM the Total harmonic distortion
(THD) and lower order harmonics (LOH) contents
are decreased in SVPWM. It is known that the maximum value of the peak-phase voltage that can be
obtained from a 3-Ph inverter with Sinusoidal Pulse
Width Modulation (SPWM) technique is equal to
Vdc/2. It is therefore evident that SVPWM achieves a
better DC bus utilization compared to SPWM (by
about 15.4%).
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International Journal of Engineering Trends and Technology (IJETT) - Volume4Issue4- April 2013
ISSN: 2231-5381
BIOGRAPHIES
Kondapalli Mounika was
born in India in 1991. She is
pursuing B. Tech final year
in KL University in Electrical and Electronics Engineering. Her field of interest
is in FACTS devices and
Power
Electronics.
Email Id: mouni.kondapalli99@gmail.com
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