THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

ECNG 2004
LABORATORY & PROJECT DESIGN II
http://myelearning.sta.uwi.edu/course/view.php?id=1678
Semester I, 2009/2010

1. GENERAL INFORMATION
Lab #:
Name of the Lab:

DIGLAB2
Design of Hold Registers and Multiplexers

Lab Weighting:

5 % [TOTAL = 25 MARKS] Estimated total

study hours1:
Lecture
Online
; Lab
Other

Delivery mode:

Venue for the Lab:

Electronics Laboratory

Lab Dependencies2

The theoretical background to this lab is provided in ECNG 1014

Theoretical content link: http://myelearning.sta.uwi.edu/course/view.php?id=684
Pre-Requisites None
Students must be able to use Xilinx Schematic Editor to implement
simple digital circuits.

Recommended
prior knowledge
and skills3:

Course Staff

Position/Role

Marcus L George Instructor

E-mail
Phone
Office


Marcus.George@uwi.sta.edu ext3164 Electronics
Lab Office

Office
Hours
Friday
10am - 1pm

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

2. LAB LEARNING OUTCOMES

Upon successful completion of the lab assignment, students will be able to:
1. Implement of a 4-bit hold register with or without buses and bus taps
2. Implement of an 8-bit hold register using 4-bit hold registers (using

Cognitive
Level
C
C, Ap

structural approach)
3. Implement of a 1-bit 4 to1-line multiplexer using buses and bus taps
4. Implement of a 2-bit 4 to 1-line multiplexer using 1-bit 4 to1-line

C
C, Ap

multiplexers (using structural approach)

5. Understand the merits of using buses and bus taps in the implementation of

An

digital systems.
6. Use a structural approach to the implementation of simple and complex

Ap

digital systems.

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

3. PRE-LAB
Due Date:
Submission
Procedure:
Estimated time to
completion:

Students must have completed the pre-lab exercise in advance of the inlab exercise.
N/A
30 minutes

3.1. Required Reading Resources

Using suitable reading resources (ECNG1014 notes, recommended books, internet, etc) research
and understand the following topics.

D Flip Flop

Hold Register

Multiplexer

3-bit 4-line to 1-line Multiplexer

Bus (as applied to digital electronics)

Make sure to fully understand the implementation of these digital circuits using logic gates. Also
read through the laboratory manual for DIGLAB2 to understand how these circuits may have
been utilized.

DIGLAB2: Design of Hold Registers and Multiplexers

4. IN-LAB
Allotted Completion 3 hours
Time:
1 printed copy of the digital lab2 manual (students must bring to the lab)
Required lab
Equipment:
1 Computer

Hold registers can be implemented by simply cascading FDC-type D Flip-Flops. The

FDC-type D Flip-Flop has inputs C, CLR, and D. It has one output Q. If D
Flip-Flops are to be cascaded then they all must be connected with common load (for
C) and reset(for CLR) signals.
4.1. Implementation of a 4-bit hold register without buses and bus taps
4.1.1.

Use the Xilinx Schematic Editor to create a 4-bit hold register as shown in
Figure 1 below.

4.1.2.

Synthesize and implement the 4-bit hold register.

4.1.3.

Create a new test bench waveform and simulate both the functional and
timing behavior of the 4-bit hold register created.

4.1.4.

Create a macro for the 4-bit hold-register created.

DIGLAB2: Design of Hold Registers and Multiplexers

Figure 1: Schematic of the 4-bit hold register without buses and bus taps

DIGLAB2: Design of Hold Registers and Multiplexers

4.2. Implementation of a 4-bit hold register using buses and bus taps
4.2.1.

Use the Xilinx Schematic Editor to create a 4-bit hold register as shown in
Figure 2 below.
a. Place bus taps as shown in Figure 2 below.

Rotate or mirror the bus taps by placing the cursor over the bus
tap and clicking using the right mouse button. Select rotate or
mirror using the left mouse button.

b. Connect the bus taps using wires as shown in Figure 2 below.

c. Set the values for each bit of the 4-bit bus:

Right click on the wire connecting the top-most D-port to a bus

tap as shown in Figure 2 below.

Select Object Properties

Type in D(0) in the first row of the column labeled value.

Click Apply. This assigns the first bit of the 4-bit bus D to the
single bit D port of the flip flop.

Now repeat the first three steps of part(c) for all other bus taps
using values D(n) and Q(n) where n = 0,1,2,3.

4.2.2.

Synthesize and implement the 4-bit hold register.

4.2.3.

Create a new test bench waveform and simulate both the functional and
timing behavior of the 4-bit hold register created.

4.2.4.

Create a macro for the 4-bit hold-register created.

DIGLAB2: Design of Hold Registers and Multiplexers

Figure 2: Schematic of the 4-bit hold register with buses and bus taps

DIGLAB2: Design of Hold Registers and Multiplexers

4.3. Implementation of an 8-bit hold register using 4-bit hold registers

4.3.1.

Use the Xilinx Schematic Editor to create an 8-bit hold register as shown in
Figure 3 below.

4.3.2.

Synthesize and implement the 8-bit hold register.

4.3.3.

Create a new test bench waveform and simulate both the functional and
timing behavior of the 8-bit hold register created.

4.3.4.

Create a macro for the 8-bit hold-register created.

Q(3:0)

D(3:0)

D(7:4)
Q(7:4)

D(7:4)

Figure 3: Schematic of an 8-bit hold register implemented using 4-bit hold registers

DIGLAB2: Design of Hold Registers and Multiplexers

4.4. Implementation of a 1-bit 4 to1-line multiplexer

4.4.1.

Using the Xilinx Schematic editor, create the 1-bit 4 to1-line multiplexer of
Figure 4 using the schematic given in Figure 5.

4.4.2.

Synthesize and implement the 1-bit 4 to1-line multiplexer.

4.4.3.

Create a new test bench waveform and simulate both the functional and
timing behavior of this module.

4.4.4.

Create a macro for the 1-bit 4 to1-line multiplexer.

Figure 4: Overall block diagram of the 4x1bit multiplexer

Figure 5: The schematic of the 4x1bit multiplexer

4.5. Implementation of a 2-bit 4 to1-line multiplexer using 1-bit 4 to1-line

multiplexers

DIGLAB2: Design of Hold Registers and Multiplexers

This is where your understanding of multiplexers and creativity will become very
useful.
4.5.1.

Using the Xilinx Schematic editor, create the 2-bit 4 to1-line multiplexer
using the macro of the 1-bit 4 to1-line multiplexer created previously.

4.5.2.

Synthesize and implement the 2-bit 4 to1-line multiplexer.

4.5.3.

Create a new test bench waveform and simulate both the functional and
timing behavior of this module.

Proceed to post-lab exercise.

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DIGLAB2: Design of Hold Registers and Multiplexers

5. POST-LAB
A signed plagiarism declaration form must be submitted with your assignment.
Due Date:

The deadline for submission of report for this laboratory exercise is as

follows:
All Groups: Monday 5th October 2009 at 12 noon

Feedback on Lab

Feedback for this laboratory exercise will be given by Mr. Marcus

George on Friday 9th October 2009 in the Electronics Laboratory during
office hours. Students lab marks will be made available.

Submission
Procedure:

Submit reports to designated graduate assistant in the Electronics

laboratory. Students must also fill out a report submission receipt and
have it signed or stamped by the graduate assistant.

Deliverables:

Submit an informal report consisting of the responses to the post-lab

exercises in addition to a lab discussion and conclusion.
[1] Discussion of the lab should include: [3 mark]
a. Relate design to the results obtained.
b. If design was successful then explain why it works. If not
successful then explain why design did not work along with and
possible solutions.
c. Include and explain all observations made.
d. Design decisions made and justification for decisions made.
e. Problems faced and how were they dealt with.
[2] Conclusion of the lab should include: [1 mark]
State briefly, but clearly, what you have gained from this laboratory.
Outline aspects that you have noted within the experiment outside of the
questions asked. Make comments on the procedure of the lab - Is there
anything that you could have done differently? How did you split the
work between group members? Did you have a plan of action? What else
would you suggest that should be added to this lab session?

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DIGLAB2: Design of Hold Registers and Multiplexers

5.1. Assignment:
5.1.1.

Design and implement a 16-bit hold register. The hold register should have a
single 16-bit data input (D) port and a single 16-bit data output(Q) port. The
design should be thoroughly tested to ensure that functional and timing errors
do not exist.
Students must submit the following for this question:
i. Schematic [2 marks]
ii. functional simulation [1 mark]
iii. timing simulation [1 mark]

5.1.2.

Explain the operation of the 4-bit hold register created in this lab exercise. [2
marks]

5.1.3.

What is the significance of using buses and bus taps in digital system design?
[1 mark]

5.1.4.

Explain the operation of the 1-bit 4 to1-line multiplexer created in section

4.1.4. [2 mark]

5.1.5.

Explain how to implement a 4-bit 4 to1-line multiplexer using the 1-bit 4

to1-line multiplexer created in section 4.1.4. Implement the 4-bit 4 to1-line
multiplexer and perform functional and timing simulation on it. [total = 6
marks]
Students must submit the following for this question:
i. Schematic [2 marks]
ii. functional simulation [1 mark]
iii. timing simulation [1 mark]

5.1.6.

Explain how to implement a 16-bit 3 to1-line multiplexer. Implement the 16bit 3 to1-line multiplexer and perform functional and timing simulation on it.
[total = 6 marks]
Students must submit the following for this question:
i. Schematic [2 marks]
ii. functional simulation [1 mark]
iii. timing simulation [1 mark]
End of DIGLAB2: Design of Hold Registers and Multiplexers
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