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MICROPROCESSORS

10CS45

MICROPROCESSORS
(Common to CSE & ISE)

SYLLABUS
I.A. Marks: 25

Hours/Week: 05

Exam Hours: 03

Total Hours: 52

Exam Marks: 100

PART A
UNIT 1

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Subject Code: 10CS45

[7 Hours]

Introduction, Microprocessor Architecture 1: A Historical Background, the MicroprocessorBased Personal Computer Systems. The Microprocessor and its Architecture: Internal

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Microprocessor Architecture, Real Mode Memory Addressing.


UNIT 2

[7 Hours]

Microprocessor Architecture 2, Addressing Modes: Introduction to Protected Mode Memory


Addressing, Memory Paging, Flat Mode Memory Addressing Modes: Data Addressing Modes,
Program Memory Addressing Modes, Stack Memory Addressing Modes.

[6 Hours]

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UNIT 3

Programming 1: Data Movement Instructions: MOV Revisited, PUSH/POP, Load-Effective


Address, String Data Transfers, Miscellaneous Data Transfer Instructions, Segment Override
Prefix, Assembler Details. Arithmetic and Logic Instructions: Addition, Subtraction and

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Comparison, Multiplication and Division.

UNIT - 4

[ 6 Hours ]

Programming 2: Arithmetic and Logic Instructions (continued): BCD and ASCII Arithmetic,

Basic Logic Instructions, Shift and Rotate, String Comparisons. Program Control Instructions:
The Jump Group, Controlling the Flow of the Program, Procedures, Introduction to Interrupts,
Machine Control and Miscellaneous Instructions.

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PART B
UNIT - 5

[6 Hours ]

Programming 3: Combining Assembly Language with C/C++: Using Assembly Language

Using the Keyboard and Video Display, Data Conversions, Example Programs.

[7 Hours ]

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UNIT - 6

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with C/C++ for 16-Bit DOS Applications and 32-Bit Applications Modular Programming,

Hardware Specifications, Memory Interface 1: Pin-Outs and the Pin Functions, Clock
Generator, Bus Buffering and Latching, Bus Timings, Ready and Wait State, Minimum versus
Maximum Mode. Memory Interfacing: Memory Devices
UNIT 7

[ 6 Hours ]

Memory Interface 2, I/O Interface 1: Memory Interfacing (continued): Address Decoding,

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8088 Memory Interface, 8086 Memory Interface. Basic I/O Interface: Introduction to I/O
Interface, I/O Port Address Decoding.

UNIT 8

[7 Hours ]

I/O Interface 2, Interrupts, and DMA: I/O Interface (continued): The Programmable
Peripheral Interface 82C55, Programmable Interval Timer 8254. Interrupts: Basic Interrupt

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Processing, Hardware Interrupts: INTR and INTA/; Direct Memory Access: Basic DMA
Operation and Definition.

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TEXT BOOK:

1. Barry B Brey: The Intel Microprocessors, 8th Edition, Pearson Education, 2009. (Listed topics only

from the Chapters 1 to 13)

REFERENCE BOOKS:
1. Douglas V. Hall: Microprocessors and Interfacing, Revised Edition, TMH, 2006.

2. K. Udaya Kumar & B.S. Umashankar : Advanced Microprocessors & IBM-PC Assembly
Language Programming, TMH 2003.

3. James L. Antonakos: The Intel Microprocessor Family: Hardware and Software Principles and
Applications, Cengage Learning, 2007.

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TABLE OF CONTENTS
Introduction, Microprocessor

UNIT - 1

Introduction: A Historical Background


The Microprocessor-Based Personal Computer
Systems.
The Microprocessor and its Architecture

1.3
1.4

1.6

Real Mode Memory Addressing.

1.7

Introduction to
Protected Mode Memory Addressing

Memory Paging

2.2

Flat Mode Memory

2.3

Addressing Modes: Data Addressing Modes

2.4

Addressing Modes: continued

2.5

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Stack Memory Addressing Modes

2.7

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Practice of examples

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3.2
3.3

Programming 1

Data Movement Instructions: MOV Revisited, PUSH/POP


Load-Effective Address, String Data Transfers,
Miscellaneous Data Transfer Instructions

3.4

Segment Override Prefix, Assembler Details.

3.5

Arithmetic and Logic Instructions: Addition, Subtraction


and Comparison
Arithmetic and Logic Instructions: Multiplication and
Division.

3.6

33-58

Program Memory Addressing


Modes

2.6

UNIT-3
3.1

06-32

Microprocessor Architecture 2, Addressing Modes

UNIT - 2
2.1

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1.5

Internal Microprocessor
Architecture
Real Mode Memory Addressing.

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1.1
1.2

Page No.

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Architecture-I.

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Programming 2:

UNIT 4 :

4.1

Arithmetic and Logic Instructions (continued): BCD

4.2
4.3

Shift and Rotate, String Comparisons.

4.4

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4.6

UNIT 5

98-116

Program Control Instructions: The Jump Group,


Controlling the Flow of the Program
Procedures, Introduction to Interrupts

4.5

Machine Control and Miscellaneous Instructions.

Programming 3:
Combining Assembly Language with C/C++

5.2
5.3

Using Assembly Language with C/C++ for 16-Bit DOS


Applications
3 32-Bit Applications Modular Programming,

5.4

Using the Keyboard and Video Display,

5.5

Data Conversions, Example Programs

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5.1

5.6

Hardware Specifications, Memory Interface 1:

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6.1

Pin-Outs and the Pin Functions,

6.6

124-144

Ready and Wait State


Minimum versus Maximum Mode.
Memory Interfacing: Memory Devices

6.7

Clock Generator
Bus Buffering and Latching
Bus Timings

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6.5

117-123

Practice of simple examples

UNIT - 6

6.2
6.3
6.4

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ASCII Arithmetic, Basic Logic Instructions

UNIT - 7

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Memory Interface 2, I/O Interface 1:

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7.1

Memory Interfacing (continued): Address Decoding

7.2

8088 Memory Interface

7.3

8086 Memory Interface

7.4

Basic I/O Interface: Introduction to I/O Interface

7.5

I/O Port Address Decoding.

7.6

practice

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UNIT - 8

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145-159

I/O Interface 2, Interrupts, and DMA:

8.1

/O Interface (continued):

8.2

The Programmable Peripheral Interface 82C55

8.3

Programmable Interval Timer 8254.

8.4

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3 Interrupts: Basic Interrupt Processing.

8.5

160-175

Hardware Interrupts: INTR and INTA/.

Direct Memory Access: Basic DMA Operation and


Definition.

8.7

DMA , and practice

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8.6

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UNIT 1

INTRODUCTION, MICROPROCESSOR ARCHITECTURE 1


The internal arrangement of a microprocessor varies depending on the age of the design

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and the intended purposes of the processor. The complexity of an integrated circuit is bounded

by physical limitations of the number of transistors that can be put onto one chip, the number of

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package terminations that can connect the processor to other parts of the system, the number of
interconnections it is possible to make on the chip, and the heat that the chip can dissipate.
Advancing technology makes more complex and powerful chips feasible to manufacture.

A minimal hypothetical microprocessor might only include an arithmetic logic unit


(ALU) and a control logic section. The ALU performs operations such as addition, subtraction,
and operations such as AND or OR. Each operation of the ALU sets one or more flags in a

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status register, which indicate the results of the last operation (zero value, negative number,
overflow. or others). The logic section retrieves instruction operation codes from memory, and
initiates whatever sequence of operations of the ALU required to carry out the instruction. A
single operation code might affect many individual data paths, registers, and other elements of
the processor.

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As integrated circuit technology advanced, it was feasible to manufacture more and


more complex processors on a single chip. The size of data objects became larger; allowing
more transistors on a chip allowed word sizes to increase from 4- and 8-bit words up to today's
64-bit words. Additional features were added to the processor architecture; more on-chip

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registers speeded up programs, and complex instructions could be used to make more compact

programs. Floating-point arithmetic, for example, was often not available on 8-bit
microprocessors, but had to be carried out in software. Integration of the floating point unit first

as a separate integrated circuit and then as part of the same microprocessor chip, speeded up

floating point calculations.


Occasionally the physical limitations of integrated circuits made such practices as a bit

slice approach necessary. Instead of processing all of a long word on one integrated circuit,
multiple circuits in parallel processed subsets of each data word. While this required extra logic
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to handle, for example, carry and overflow within each slice, the result was a system that could
handle, say, 32-bit words using integrated circuits with a capacity for only 4 bits each.
With the ability to put large numbers of transistors on one chip, it becomes feasible to

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integrate memory on the same die as the processor. This CPU cache has the advantage of faster

access than off-chip memory, and increases the processing speed of the system for many
applications. Generally, processor speed has increased more rapidly than external memory

memory.

Microprocessor History and Background

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speed, so cache memory is necessary if the processor is not to be delayed by slower external

The CPU ("central processing unit," synonymous with "microprocessor," or even simply

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"processor") is often referred to as the "brain" of the computer.

Choosing the correct processor is vital to the success of your homebuilt computer project.
Here's a little background about the history of microprocessors.

1.1 A Historical Background

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In historical background, our aim is to study about the events that led to the
development of microprocessors especially the modern microprocessors, namely, 80x86,
Pentium, Pentium pro, Pentium 3 and the Pentium 4. The historical background can be studied
in three different accounts:

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1.The Mechanical Age

2. The Electrical Age

3. The Microprocessor Age

1.1.1 The Mechanical Age: The idea for a system that can compute (calculate) has been
around for a long time, even before the modern electrical and electronic devices came into
existence.

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ABACUS- the Babylonians invented the abacus sometime during 500 BC. The abacus is the
oldest known mechanical calculator. The working mechanism of abacus is quite simple, it used
strings of beads to perform calculations. The abacus was not improved until 1642 when a
mathematician named Blaise Pascal invented a calculator that was constructed of gears and
wheels. Each gear contained 10 teeth that after one complete revolution advanced a second gear

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one place. The first practical, geared mechanical machines that could automatically compute
information arrived in the 1800's. This was much before humans knew anything about

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electricity or light bulb.(Picture- Abacus).

ANALYTICAL

ENGINE-

In

1823

The

Royal

Astronomical

Society

of

Great Britain commissioned Charles Babbage to produce a programmable calculating machine.

This machine was supposed to generate navigational tables for the Royal Navy. Charles
Babbage was aided by Augusta Ada Byron , the countess of Lovelace. Charles Babbage named
this machine 'Analytical Engine'. The Analytical Engine which he conceived had the following
features- it could store 1000 20 digit decimal numbers and a variable program that could
modify the function of this engine. The input to the analytical engine was through punched
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cards, Charles Babbage borrowed the idea of punched cards from Joseph Jacquard, who used it
to program the weaving machine he invented in 1801. After many years of work, Charles
Babbage realised that it's not possible to make the analytical engine as the machinists of his era
where unable to produce the parts needed for his work. (Picture- Analytical Engine).

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1.1.2. The Electrical Age


The Electrical age began with the invention of electric motor by Michael Faraday. With
it came a multitude of motor driven adding machines all based on the mechanical calculator

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developed by Blaise Pascal. These electrically driven mechanical calculators where common
office equipment until the early 1970's when small handheld calculators began to appear, first

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introduced by Bomar.

In 1889 Herman Hollerith developed a punched card for storing data, he also made a
mechanical calculator driven by the electric motors. His machine counted, sorted and

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collated(to arrange in proper sequence) the data stored in the punched card. The United States
governmnet commissioned Herman Hollerith to use his punched card system to store and
tabulate information for the 1890 census. In 1896 Herman Hollerith started a company called

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the Tabulating Machine Company which developed machines that used punched cards for
tabulation. After a number of merges, this Tabulating Machine Company was formed into the

International Business Machines Corporations now known as the IBM. (Picture- Tabulating

machine developed by Herman Hollerith)

The first electronic calculating machine , something which did not require an electric

motor was developed by the German Inventor named Konrad Zuse. His Z3 calculating
computer where used in aircraft and missile design during World War 2.

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It has been recently discovered through declassification of British Military documents


that the first electronic computer was put into operation in the year 1943 to break secret

German Military codes. This electronic computer was invented by Allan Turing. It used
vacuum tubes to perform calculations. He called this electronic computer Colossus. Colossus
was successful in breaking down the secret German military codes generated by the Enigma
machine. The disadvantage with Colossus was that it was not programmable. Colossus was a
fixed program computer system ,which we call today as a special purpose computer. (Picture-

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Konrad Zuse with Z3 computer).

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The first general purpose, programmable electronic computer was developed in 1946 at

the University of Pennsylvania. This first modern computer was called the ENIAC (Electronic
Numerical Integrator and Calculator). The ENIAC was a huge machine weighing more than 30

tons and used 17000 vacuum tubes and 500 miles of wires. The ENIAC could perform only

100,000 operations per second. The ENIAC was programmed by rewiring it's circuits. The
ENIAC thrust us into the age of computers. (Picture- ENIAC).

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1.1.3. The Microprocessor Age


Bell labs developed the transistor in 1948, this was closely followed by the development
of Integrated circuits by Jack Kilby of Texas Instruments in 1958. The integrated circuits led to

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the development of digital integrated circuits in the 1960's and finally the development of

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microprocessor by Intel Corporation in 1971.

Microprocessor is a programmable controller on a chip. The world's first


microprocessor is the Intel 4004. It was a 4-bit microprocessor that could address only 4096 4-

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bit wide memory locations. (Bit is either a 0 or 1 , 4-bit wide memory location can also be
called a nibble). The Intel 4004 instruction set contained only 45 instructions. It was fabricated
with the then current state of the art P-channel MOSFET technology. Hence it could only

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execute 50 Kilo instructions per second.

The 4004 microprocessor was readily accepted by the people ,as a result applications

abounded for this device. It was mainly used in early video games and small microprocessor
based applications. The main problems with the early microprocessors where their speed, word

width and memory size. Intel later released the 4040 microprocessor, this was just an update to
the 4004 with improved speed but it did not have any improvement in word width or memory
size. Other companies, particularly Texas instruments also produced 4-bit microprocessors
(TMS 1000) at this time. The 4-bit microprocessors still survives today in low end applications
like microwave ovens and small control systems.
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In 1971, Intel developed the 8008 microprocessor, an extended 8-bit version of the 4004
microprocessor. This addressed an expanded memory size (16 K bytes) and also had additional
instructions (48 in total) which enabled it's use in more advanced systems. (byte is an 8-bit wide
binary number and K is 1024) .

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As engineers demanded more from 8008, it's slow speed , small memory size and
instruction set limited it's use. As an welcoming answer to these demands, Intel developed the

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8080 microprocessor, the first modern 8-bit microprocessor in 1973. The 8080 addressed an

expanded memory of 64 K bytes which is four times more than the 8008. The 8080 also could
execute instructions 10 times faster than the 8008. An addition instruction which took 20
microseconds(50,000 instructions per second) in 8008 took only 2 microseconds(500,000
instructions per second) in 8080. It also had additional instructions. The 8080 was compatible
with TTL (Transistor-Transistor logic) hence it made it's interfacing easier.

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1.2 The Microprocessor Based Personal Computer System

The introduction of microprocessors had a huge impact in the way we use computers.
Computers that once took large areas where reduced to the size of small desktops. Although
these desktop computers are small and compact, they possess computing power more than that
of

the

large

size

computers

of

the

previous

generation.

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Here, in this section, we are going to learn about the structure of a microprocessor based
personal computer system. The block diagram of a personal computer system is shown in the
figure.

This block diagram also applies to any computer system, from the early mainframe computers

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to the modern microprocessor based systems. The block diagram consists of three main blocks,

connected to each other with the help of buses.

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Figure 1.1 block diagram of a microprocessor--based computer system.


What is a bus? A bus is a series of common connections that carry the same kind of information.
Example- An address bus is a bus with 20 connections that carry the memory address to the memory.
1.2.1 The memory and the input/output system

The memory structure of all Intel 80x86 to Pentium 4 based personal computer systems are similar. This

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includes the first computers based on 8088 introduced in 1981 by IBM to the most modern computers
based on Pentium 4. The memory structure of microprocessor based computer systems can be divided
into three main regions. These are

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1. Transient program area (TPA)


2. System area

3. Extended memory system (XMS)

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Figure 1.2 The memory map of a personal computer.

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It should be noted that the Extended memory system is not available in those computers
based on 8086 or 8088. In these old computers the TPA and System area exists but not the
Extended memory system. The TPA is of size 640 Kb and System area is of size 384Kb. The

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TPA and System area together forms the real or conventional memory which is of size 1024Kb
or 1 Mb. It's called as real or conventional memory because each Intel microprocessor is

designed to function in this area using its real mode of operation.


Those computer systems that uses the any of the microprocessors, Intel 80286 through

Pentium 4, has the 640 Kb of TPA and 384 Kb of system area, In addition , these systems also
have an Extended memory. Hence IBM designates these systems as AT class machines (ATAdvanced class computer systems). These systems are also called as ISA (Industry standard
architecture)

or

EISA

(Extended

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ISA).

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The extended memory available in the computer systems using the 80286- 80386SX
microprocessors is 15Mb. While the amount of extended memory available in the computer
systems using 80386DX - Pentium microprocessors are 4095Mb, excluding the 1Mb real or
conventional memory. The Computer systems having Pentium pro - Pentium 4 microprocessors

on

Pentium

systems

have

an

extended

memory

more

than

180Gb.)

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based

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can have 1Mb less than 4Gb to 64GB extended memory. (Note- Modern day computer systems

Recently, a new bus known as the Peripheral Component Interconnect (PCI) bus has been
introduced in the Pentium- Pentium 4 based systems. The older computers based on 8086/8088
used an 8 bit peripheral bus to interface with 8 bit devices. The ISA machines or AT class
machines which used 80286 or above microprocessors used 16 bit peripheral bus for interface.
The EISA machines that used 80386DX and 80486 microprocessors used 32 bit peripheral bus
for interface. All the new buses were compatible with the

older devices. That is, an 8 bit

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interface card is compatible with an 8-bit bus , 16-bit bus or a 32 bit bus. Similarly a 16 bit
interface card is compatible with a 16 bit bus and 32 bit bus.

Another bus type found in the 80486 based computer systems is the VESA local bus or VT bus.
This local bus helps to interface disk and video to the microprocessor. Two new buses have
also been introduced, one is the USB or Universal Serial Bus and the other is the AGP (

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Advanced graphics port)- The Advanced graphics port transfers data between the video card
and the microprocessor at very high speeds.
The Transient Program area (TPA)

The transient program area or TPA holds the DOS operating system and other programs that control the

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computer system. The TPA also holds other active or inactive application programs. We know that the

TPA is 640Kb and since it holds DOS on it a part of this 640 Kb is used up by DOS operating system. The
size of the TPA available for other application programs is 628Kb if MS-DOS version 7.X is used as the

operating system. The older versions of DOS used to take up large spaces of TPA leaving only less than

530Kb for other applications. PC-DOS is another operating system that is found in computer systems.
Both PC-DOS and MS-DOS are compatible with each other, hence both functioned similarly with
application programs. Windows and OS/2 are other operating systems compatible with DOS and allows
DOS programs to execute.

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MICROPROCESSORS

Figure 1.3 The memory map of the TPA in a personal computer.


The memory map of the TPA is shown in the figure. The memory map shows how different

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areas of the TPA are allotted to the system programs, data and drivers. To the left of each area

is a hexadecimal number that shows the memory address that begin and end each data area.

1. Interrupt Vectors - The interrupt vectors which occupy the area between 00000 and 00400
is responsible for accessing various features of the DOS, BIOS and other application programs.

2. BIOS communication area and DOS communication area - BIOS is nothing but Basic
Input/Output System. BIOS is a collection of programs that is stored in the ROM or flash
memory that is used to control the Input/Output devices that is connected to the computer
system. The BIOS and DOS communication areas have transient data that can be used by
programs

to

access

the

I/O

devices

or

other

parts

of

the

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computer

system.
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3. IO.SYS - The IO.SYS is a program that loads into the TPA from the disk when the computer
system using MSDOS or PCDOS are switched ON. The programs in the IO.SYS enables the
DOS programs to use the keyboard, the display, printer and other I/O devices.
4. MSDOS - MSDOS occupies two parts of the TPA. One is at the top of TPA which is

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considerably small and 16 bytes in length. The other is at the bottom and is larger. The memory

size occupied by the DOS depends on the version of the DOS installed. Older versions usually
larger

areas

of

TPA

compared

to

the

newer

versions.

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needed

5. Device Drivers- Drivers are those files with an extension .SYS such as MOUSE.SYS.
Drivers are programs that control the installable devices like mouse, hand scanner and also
other installable application programs. The size of the driver and the number of drivers vary
from

one

computer

to

the

another.

6. COMMAND.COM- The COMMAND.COM helps to control the computer system using


the keyboard when operated in DOS mode. The COMMAND.COM program processes the
commands

as

they

are

typed

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DOS

from

the

keyboard.

7. Free TPA- The free TPA holds the active DOS application programs. These DOS
application programs can be exemplified as the word processor , spreadsheet and CAD
programs. In addition to these, free TPA also holds the TSR (Terminate and Stay Resident)
programs. These remain in the free TPA in an inactive state until initiated by a hot-key or an
interrupt. An example of TSR is the calculator program that is activated upon the ALT+C

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hotkey.

SYSTEM AREA

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The System area which is smaller than the TPA is considerably important. It contains programs
for data storage and these programs are stored in ROM or flash memory and also in some areas

of the RAM. The system area map is shown in the figure.

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Figure 1.4The system area of a typical personal computer.

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On the left side memory addresses of the particular regions are given in hexadecimal
format. The first area of the system space extends from A0000H to C7FFFH and has the video
display RAM and video control programs. The Video display RAM is stored in two parts, first

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from A0000H to A7FFFH and is for the graphical data, second from B0000H to B7FFFH and
stores the text data. The video BIOS contains programs that control the video display of the

computer and is located on ROM or falsh memory. It's area in system space is from C0000H to

C7FFFH. The size and amount of the memory used depends upon the type of video display
adapter used.

The area C8000H - DFFFFH is free system area and is called the open system area. It is mostly
used as the extended memory system in PC and XT machines ( PC and XT machines means
those computers based on 8086/8088 microprocessor) and as an upper memory system in AT
class machines (Computers using 80286 or above microprocessors).
Memory locations E0000H-EFFFFH contains the cassette BASIC language on ROM found in
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the older IBM based systems. In almost all the newer systems this particular area is kept open
or free and is also used as RAM to aid the faster operation of DOS application programs.
The system area F0000H to FFFFFH is used by the System BIOS ROM, but this System BIOS
ROM only operates the I/O devices and is not responsible for the controlling of the video

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display system which is done by the separate system BIOS ROM at the location C0000H. The

system BIOS at the top is divided into two parts, first part is in the area F0000H to F7FFFH and

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contains programs that set up the computer. The second part contains procedures that control
the I/O devices.

MICROPROCESSOR

Microprocessor can be called as the heart of the microprocessor based personal computer

system. The microprocessor is also known by the names CPU or Central Processing Unit and

I/O devices through the buses.

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controls the working of the computer system. The microprocessor connects to the memory and

The microprocessor follows three simple steps in its working1. Transfers data from memory to itself or to the I/O devices.
2. Performs arithmetic and logical calculations.

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3. Performs a program via simple decisions.

Even though these processes are simple, the microprocessor is able to solve all types of
problems using this approach. The strength of the microprocessor lies in its ability to execute

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millions of instructions per second from the software or programs. Software and programs are
nothing but a collection of instructions. These software or program is stored in the memory.

This stored program concept makes the microprocessor or in the main, a computer system itself
efficient.

very

The arithmetic and logical instructions executed by the microprocessor are

1.
2.
3.
4.
5.
6.

Addition
Subtraction
Multiplication
Division
AND
OR
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7. NOT
8. NEG
9. Shift
10. Rotate

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Data is stored in the memory or the internal registers. The width of the data is either a byte (8bits), word (16-bits) or a double word (32-bits). Only the 80386 and above versions are able to
execute all three. 8086 to 80286 could directly manipulate 8-bit and 16-bit data but not 32-bit
data.
A Co-processor called the numeric processor is with the 80486 to aid in arithmetic calculations
dealing with floating point arithmetic. This numerical processor was an additional component
in the older 8086- 80386 processors.

1.3 The Microprocessor and its Architecture: Internal


Microprocessor Architecture

The Microprocessor Called the CPU (central processing unit).The controlling element in a
computer system. The controlling element in a computer system. Controls memory and I/O

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through connections called buses.

* buses select an I/O or memory device, transfer data between I/O devices or memory and the
microprocessor control I/O and memory systems microprocessor, control I/O and memory
systems

* Memory and I/O controlled via instructions stored in memory, executed by the stored in
memory, executed by the microprocessor.

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Microprocessor performs three main tasks:

data transfer between itself and the memory or I/O systems


simple arithmetic and logic operations
program flow via simple decisions

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Power of the microprocessor is capability to execute billions of millions of instructions per

second from a program or instructions per second from a program or software (group of
instructions) stored in the memory system.

stored programs make the microprocessor and computer system very powerful devices.

Another powerful feature is the ability to make simple decisions based upon numerical
a microprocessor can decide if a number is zero, positive and so forth positive, and so forth
These decisions allow the microprocessor to modify the program flow so programs to modify
the program flow, so programs appear to think through these simple decisions.

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The block diagram of 8086 CPU architecture is shown in the figure.

Figure 1.5 8086 CPU Architecture

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Data registers- The registers AX, BX, CX and DX are called as the data registers. They are 16
bits wide and can store both the operands and the results. Each of the data registers can either
be accessed as a whole or the higher byte and the lower byte can be accessed separately.
Example- The whole 16 bits in the register AX can be used together or the higher byte and

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lower byte can be accessed separately as AH and AL. The registers BX, CX and DX also are

used in other functions in addition as being used as the arithmetic registers.


is

used

CX

is

used

BX

DX

is

used

as
as
to

hold

a
an
the

base
implied
I/O

register

in

counter
address

during

by

address

calculations.

some

instructions.

some

I/O

operations.

Pointer and Index registers- The pointer and index group include the SP, BP, SI, DI and IP.
The SP and IP are essentially the stack pointer and instruction pointer. The instruction pointer is
also called as the program counter. The complete stack and instruction address is formed by
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MICROPROCESSORS

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adding the contents of the SP and IP with the contents in CS and SS. BP or base pointer is used
to address the beginning of a stack. It is used in combination with other registers and/or with a
displacement. SI and DI are the index registers, they are used in combination with the BX or
BP and/or a displacement. The SP and BP can be used to store the operands but not the IP.

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Formation of Effective address (EA)- The data address formed by adding together, a

combination of ,BX or BP register contents, SI or DI register contents and a displacement is


as

an

effective

address

or

offset.

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called

Displacement- The word displacement is used to indicate any quantity that is added to the
register

contents

to

form

an

effective

address.

Segment registers- The segment registers are CS, SS, DS and ES. The registers that are used
for addressing, SP, BP, SI, DI and IP are 16-bits wide and hence the effective address or offset

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address is 20 bits wide.

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will be 16 bits wide but the address that is required on the address bus called the physical

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Figure 1.6 Formation of physical address

Formation of physical address- We have seen that the address required on the address bus is 20

bits wide but a problem persists as the effective address formed is only 16 bits wide. Hence the

formation of the physical address requires the addition of the contents of the effective address

with the contents of any of the segment registers. To generate the extra 4 bits , we have to
append four 0 bits to the right most digit of the number in the segment register. Example if CS
= 123A and IP = 341B , the physical address formed by the addition of these two will be
341B+

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10CS45

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Figure 1.7 overlapping segments

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MICROPROCESSORS

Overlapping segments- The use of segment registers divides the memory space into
overlapping segments with each segment being 64 Kb wide and beginning at a memory
that

is

divisible

by

16.

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location

Segment address- Contents of a segment register are called as 'segment address'.


Beginning segment address - Segment address multiplied by 16 is known as 'beginning segment
address'.

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Advantages of using segment registers.

1. It allows the memory capacity to be 1Mb even though the individual instructions are only 16
bits wide.

2. It allows the instruction, data and stack portion to be 64Kb wide by facilitating the use of more

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than one instruction, data and stack segment.

3. Facilitates the program, data and stack to have separate memory portions.
4. Allows the program and its data to be stored in separate parts of memory while execution of the

program is performed.
8086 PSW

The 8086 PSW is 16 bits, but only 9 of its bits are used. Each bit of 8086 PSW is called a flag.
The flags are divided into two groups, these are conditional flags and control flags. The
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MICROPROCESSORS

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conditional flags reflect the condition involving a previous instruction execution. The control
flags controls the functioning of certain instructions.

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Conditional Flags
1. SF (Sign flag)- It is equal to MSB of the result. In 2's compliment a 1 in the MSB shows that

the result is a negative number and a 0 in the MSB shows that the result is a non-negative

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number. Hence the sign flag is used to determine whether the result is positive or negative.

2. ZF (Zero flag) - 1 in the zero flag shows that the result is zero and a 0 in the zero flag shows
that the result is a non-zero number.

3. PF (Parity flag) - The PF will become 1 if there are even number of one's in the lower 8-bits of
the PSW.

4. CF (Carry flag) - There are two cases here involving addition and subtraction. In addition a

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carry out of the MSB causes this flag to be set. In subtraction if the MSB borrows then this flag
is set.

5. AF (Auxillary carry flag)- In addition the carry out of a bit 3 causes this flag to be set. In
subtraction a borrow by bit 3 causes this flah to be set.

6. OF (Overflow flag)- The overflow flag is set when the result is out of range. More specifically,
in addition, if there is a carry into the MSB and the MSB has no carry out and in addition, if the

Figure 1.8 8086 PSW

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MSB needs to borrow and there is no borrow from MSB.

Control flags-

1. DF (Direction flags)- Used by string manipulation instructions. If clear, the string is processed
from the beginning, starting with the first element with the lower address If set, the string is
processed from the higher address to the lower most address.

2. IF (Interrupt enable flag)- If enabled it helps the CPU to recognize the maskable interrupt else
these interrupts are ignored.
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MICROPROCESSORS

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3. TF (Trap flag)- If set a trap is executed after each instruction.

Buses

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A common group of wires that interconnect components in a computer, Transfer address, data,
& control information between microprocessor memory and I/O between microprocessor,
memory and I/O.

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Three buses exist for this transfer of information: address, data, and control.

Figure 110 shows how these buses interconnect various system components.

The address bus requests a memory location from the memory or an I/O location from the I/O
from the memory or an I/O location from the I/O devices

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if I/O is addressed, the address bus contains a 16-bit I/O address from 0000H through
FFFFH.

if memory is addressed the bus contains a memory if memory is addressed, the bus contains
a memory address, varying in width by type of microprocessor.
64-bit extensions to Pentium provide 40 address pins allowing up to 1T byte of memory to be
pins, allowing up to 1T byte of memory to be devices.

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accessed.

The data bus transfers information between the microprocessor and its memory and I/O address
microprocessor and its memory and I/O address space.
Data transfers vary in size, from 8 bits wide to 64 bits wide in various Intel microprocessors.

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8088 has an 8-bit data bus that transfers 8 bits of data at a time

8086 80286 80386SL 80386SX d 80386EX f 8086, 80286, 80386SL, 80386SX, and
80386EX transfer 16 bits of data 80386DX 80486SX d 80486DX 32 bit 80386DX, 80486SX,

and 80486DX, 32 bits

Pentium through Core2 microprocessors transfer 64 bits of data bits of data.


Advantage of a wider data bus is speed in applications using wide data.
In all Intel microprocessors family members, memory is numbered by byte. Pentium through
Core2 microprocessors contain a 64-bit-wide data bus.

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Control bus lines select and cause memory or I/O to perform a read or write operation to
perform a read or write operation. In most computer systems, there are four control bus
connections:
MRDC (memory read control)

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MWTC (memory write control)


IORC (I/O read control)( )

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IOWC (I/O write control).

Over bar indicates the control signal is active low; over bar indicates the control signal is
active-low;(active when logic zero appears on control line)

The microprocessor reads a memory location by sending the memory an address through the
sending the memory an address through the address bus.

Next, it sends a memory read control signal to cause the memory to read data.

Data read from memory are passed to the microprocessor through the data bus.

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Whenever a memory write, I/O write, or I/O read occurs, the same sequence ensues.

1.4 The Programming Model of 8086

8086 through Core2 considered program visible.

registers are used during programming and are specified by the instructions

Other registers considered to be program invisible.

not addressable directly during applications programming

80286 and above contain program-invisible registers to control and operate protected memory.

and other features of the microprocessor

80386 through Core2 microprocessors contain full 32-bit internal architectures.

8086 through the 80286 are fully upward-compatible to the 80386 through Core2.

Figure 21 illustrates the programming model 8086 through Core2 microprocessor.

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including the 64-bit extensions

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10CS45

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MICROPROCESSORS

Figure 111 The programming model of the 8086 through the Core2 microprocessor including

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the 64-bit extensions.

Multipurpose Registers

RAX - a 64-bit register (RAX), a 32-bit register (accumulator) (EAX), a 16-bit register (AX),

or as either of two 8-bit registers (AH and AL).


The accumulator is used for instructions such as multiplication, division, and some of the

adjustment instructions.
Intel plans to expand the address bus to 52 bits to address 4P (peta) bytes of memory.

RBX, addressable as RBX, EBX, BX, BH, BL.

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MICROPROCESSORS

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BX register (base index) sometimes holds offset address of a location in the memory system in
all versions of the microprocessor
RCX, as RCX, ECX, CX, CH, or CL.

a (count) general-purpose register that also holds the count for various instructions

RDX, as RDX, EDX, DX, DH, or DL.

a (data) general-purpose register

holds

part

of

the

result

or part of dividend before a division

RBP, as RBP, EBP, or BP.

points

to

from

multiplication

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memory

(base

for memory data transfers

pointer)

location

RDI addressable as RDI, EDI, or DI.

often addresses (destination index) string destination data for the string instructions

RSI used as RSI, ESI, or SI.

the (source index) register addresses source string data for the string instructions

like

RDI,

RSI

purpose register

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also

functions

as

R8 - R15 found in the Pentium 4 and Core2 if 64-bit extensions are enabled.

data

are

addressed

as

64-,

32-,

16-,

general-

or

8-bit

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sizes and are of general purpose

Most applications will not use these registers until 64-bit processors are common.

the 8-bit portion is the rightmost 8-bit only

bits

to

15

are

not

directly

addressable

as

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a byte

Special-Purpose Registers
Include RIP, RSP, and RFLAGS

segment registers include CS, DS, ES, SS, FS, and GS

RIP addresses the next instruction in a section of memory.

defined as (instruction pointer) a code segment

RSP

addresses

an

area

of

memory

called

the stack.

the (stack pointer) stores data through this pointer


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RFLAGS indicate the condition of the microprocessor and control its operation.

Figure 22 shows the flag registers of all versions of the microprocessor.

Flags are upward-compatible from the 8086/8088 through Core2 .

The rightmost five and the overflow flag are changed by most arithmetic and logic operations.

although data transfers do not affect them

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microprocessor family.

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Figure 1.12 The EFLAG and FLAG register counts for the entire 8086 and Pentium

Flags never change for any data transfer or program control operation.

Some of the flags are also used to control features found in the microprocessor.

Flag bits, with a brief description of function.

C (carry) holds the carry after addition or borrow after subtraction.

also indicates error conditions

P (parity) is the count of ones in a number expressed as even or odd. Logic 0 for odd parity;

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logic 1 for even parity.

if a number contains three binary one bits, it has odd parity

if a number contains no one bits, it has even parity

C (carry) holds the carry after addition or borrow after subtraction.

also indicates error conditions

P (parity) is the count of ones in a number expressed as even or odd. Logic 0 for odd parity;

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logic 1 for even parity.

if a number contains three binary one bits, it has odd parity; If a number contains no one bits, it
has even parity

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A (auxiliary carry) holds the carry (half-carry) after addition or the borrow after subtraction
between bit positions 3 and 4 of the result.

Z (zero)

S (sign) flag holds the arithmetic sign of the result after an arithmetic or logic instruction
executes.

T (trap)

I (interrupt) controls operation of the INTR (interrupt request) input pin.

D (direction)

selects increment or decrement mode for the DI and/or SI registers.

O (overflow)

occurs when signed numbers are added or subtracted.

an

overflow

indicates

the capacity of the machine

IOPL

used

in

to select the privilege level for I/O devices.


NT (nested task)

RF (resume)

protected

has

mode

exceeded

operation

flag indicates the current task is nested within another task in protected

mode operation.

result

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the

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The trap flag enables trapping through an on-chip debugging feature.

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shows that the result of an arithmetic or logic operation is zero.

used with debugging to control resumption of execution after the next

instruction.

VM (virtual mode) flag bit selects virtual mode operation in a protected mode system.

AC, (alignment check) flag bit activates if a word or doubleword is addressed on a non-word or

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non-doubleword boundary.

VIF is a copy of the interrupt flag bit available to the Pentium 4(virtual interrupt)

VIP (virtual) provides information about a virtual mode interrupt for (interrupt pending)

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Pentium.

used in multitasking environments to provide virtual interrupt flags

ID (identification)

flag indicates that the Pentium microprocessors support the CPUID

instruction.

CPUID instruction provides the system with information about the Pentium microprocessor

Segment Registers

Generate memory addresses when combined with other registers in the microprocessor.

Four or six segment registers in various versions of the microprocessor.

A segment register functions differently in real mode than in protected mode.

Following is a list of each segment register, along with its function in the system.
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CS (code) segment holds code (programs and procedures) used by the microprocessor.

DS (data) contains most data used by a program.

Data are accessed by an offset address or contents of other registers that hold the offset address

ES (extra) an additional data segment used by some instructions to hold destination data.

SS (stack) defines the area of memory used for the stack.

stack entry point is determined by the stack segment and stack pointer registers

the

register

also

the stack segment

allow

two

additional

access by programs

data

within

FS and GS segments are supplemental segment registers available in 80386Core2


microprocessors.

addresses

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memory

segments

for

Windows uses these segments for internal operations, but no definition of their usage

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is available.

1.4 REAL MODE MEMORY ADDRESSING


Two Real modes of addressing on 80x86

Pentium 4 comes up in the real-mode after it is reset. It will remain in this mode

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unless it is switched to protected-mode by software.

In real mode, the Pentium 4 operates as a very high performance 8086.


Pentium 4 can be used to execute the base instruction set of the 8086 MPU
(backward compatibility).

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In addition, a number of new instructions (called extended instruction set) have been

added to enhance its performance and functionality (such new instructions can be run in the
real-mode as well as the protected-mode). In real-mode, only the first 1 M bytes of memory

can be addressed with the typical segment:offset logical address. Each segment is 64K bytes

long.

Notice that the Pentium 4 microprocessor has 36 bit address bus, which means it can

support up to 236 = 64G bytes of total memory (which cannot be addressed in real-mode but
can be addressed in protected mode).

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Real mode flat model means

Strictly converting one address value into a physically meaningful location in the RAM.

Real mode segmented model means

strictly converting two address values into a physically meaningful memory location.

gives access to one megabyte (1,048,576 bytes) of directly addressable memory, known as real

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mode memory.

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a. Segment Registers

Segment registers are basically memory pointers located inside the CPU.
Segment registers point to a place in memory where one of the following things begin:

1. Data storage
2. Code execution.

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Example: code segment register CS points to a 64K region of memory:

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b. Real Mode Segmented Model


Segmented organization
16-bit wide segments
Two components
Base (16 bits)
Offset (16 bits)
Two-component specification is called logical address, also called effective address.

Logical address translates to a 20-bit physical address.

o
o

c. Real Mode Segmented Model, Cont.


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10CS45

Addresses are limited to 20 bits:


220=1,048,576 bytes.
Physical address is generated by adding a
16-bit segment register, shifted left four bits
plus a 16 bit-offset.

Generating 20-bit physical address in Real Mode:

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MICROPROCESSORS

d. Problems Related to Segmentation

o
o

Segmentation often caused grief for programmers who tried to access large data structures:
Since an offset cannot exceed 16 bits, you cannot increment beyond 64k.
Instead, program must watch out for a 64k boundary and then play games with the segment
register.
This nightmare was originally created to support CP/M-80 programs ported from 8080 chip to
8086.
Successful short-term thinking;
Catastrophically bad long-term thinking that resulted in never-ending Windows 9x problems!

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e. Address Space in Real Mode

Address space in real mode segmented model runs from

00000h to 0FFFFFh, within one megabyte of memory.


For compatibility reasons, Pentium CPU is capable of switching itself into real mode
segmented model, is effectively becoming a good old 8086 chip!

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UNIT-2
2.1 PROTECTED-MODE

the protected mode.


In addition, segments can be of variable size (below or above 64 KB).
Some system control instructions are only valid in the protected mode.

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In the protected-mode, memory larger than 1 MB can be accessed.Windows XP operates in

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In protected mode, the base:offset logical memory addressing scheme (which is used in real
mode) is changed.

The offset part of the logical memory address is still used. However, when in the protected
mode, the processor can work either with 16-bit offsets (the 16-bit instruction mode) or with 32bit offsets (the 32-bit instructionmode). A 32-bit offset allows segments of up to 4G bytes in
length. Notice that in real-mode the only available instruction mode is the 16-bit mode (during

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which accessing 32-bit registers requires the prefix 66h).

However, the segment base address calculation is different in protected mode. Instead of
appending a 0 at the end of the segment register contents to create a segment base address (which
gives a 20-bit physical address), the segment register contains a selector that selects a descriptor
from a descriptor table. The descriptor describes the memory segment's location,length, and
access rights. This is similar to selecting one card from a deck of cards in one's pocket.

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Because the segment register and offset address still create a logical memory address, protected
mode instructions are the same as real mode instructions. In fact, most programs written to
function in the real mode will function without change in the protected mode.
DESCRIPTORS:

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The selector, located in the segment register, selects one of 8192 descriptors from one of two

tables of descriptors (stored in memory): the global and local descriptor tables. The descriptor
describes the location, length and access rights of the memory segment.

Each descriptor is 8 bytes long and its format is shown below:


The 8192 descriptor table requires 8 * 8192 = 64K bytes of memory. The
main parts of a descriptor are:
Base (B31 B0): indicates the starting location (base address) of the memory segment. This
allows segments to begin at any location in the processor's 4G bytes of memory.
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Limit (L19 L0): contains the last offset address found in a segment. Since this field is 20 bits,
the segment size could be anywhere between 1 and 1M bytes. However, if the G bit
(granularity bit) is set, the value of the limit is multiplied by 4K bytes (i.e., appended with

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FFFH). In this case, the segment size could be anywhere between 4K and 4G bytes in steps of
4K bytes.

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Example,
Base = Start = 10000000h
Limit = 001FFh and G = 0

So, End = Base + Limit = 10000000h + 001FFh = 100001FFh


Segment Size = 512 bytes
Base = Start = 10000000h
Limit = 001FFh and G = 1

Segment Size = 2M bytes

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So, End = Base + Limit * 4K = 10000000h + 001FFFFFh = 101FFFFFh

AV bit: is used by some operating systems to indicate that the segment is available (AV = 1) or

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not available (AV = 0).

D bit: If D = 0, the instructions are 16-bit instructions, compatible with the 8086-80286
microprocessors. This means that the instructions use 16-bit offset addresses and 16-bit registers

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by default. This mode is the 16-bit instruction mode or DOS mode. If D = 1, the instructions are
32-bits by default (Windows XP works in this mode). By default, the 32-bit instruction mode

assumes that all offset addresses and all registers are 32 bits. Note that the default for register

size and offset address can be overridden in both the 16- and 32-bit instruction modes using the
66h and 67h prefixes. In 16-bit protected-mode, descriptors are still used but segments are

supposed to be a maximum of 64K bytes.


Access rights byte: allows complete control over the segment. If the segment is a data segment,

the direction of growth is specified. If the segment grows beyond its limit, the microprocessor's
operating system program is interrupted, indicating a general protection fault. You can specify
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MICROPROCESSORS

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whether a data segment can be written or is write-protected. The code segment can have reading
inhibited to protect software. This is why It is called protected mode. This kind of protection is

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unavailable in realmode.

.
SELECTORS:

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Descriptors are chosen from the descriptor table by the segment register.
There are two descriptor tables:

Global descriptors table: contains segment definitions that apply to all programs (also called
system descriptors).

Local descriptors table: usually unique to an application (also called application descriptors).
Each descriptor table contains 8192 descriptors, so a total of 16,384 descriptors are available to

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an application at any time. This allows up to 16,384 memory segments to be described for each
application. The Figure below shows the segment register in the protected mode. It contains:

13-bit selector field: chooses one of the 8192 descriptors from the descriptor table (213 = 8192).

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Table indicator (TI) bit: selects either the global descriptor table (TI = 0) or the local descriptor

table (TI = 1).

Requested privilege level (RPL) field: requests the access privilege level of a memory segment.

The highest privilege level is 00 and the lowest is 11.If the requested privilege level matches or

is higher in priority than the privilege level set by the access rights byte, access is granted.

Windows uses privilege level 00 (ring 0) for the kernel and driver programs and level 11 (ring 3)
for applications. Windows does not use levels 01 or 10. If privilege levels are violated, the
system normally indicates a privilege level violation.

Dept of CSE, SJBIT

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10CS45

gr
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c

om

MICROPROCESSORS

Example:

Real Mode: DS = 0008h, then the data segment begins at location 00080h and its length is 64K

ud
en
ts

bytes.

Protected Mode: DS = 0008h = 0000 0000 0000 1000, then the selector selects Descriptor 1 in
the global descriptor table using a requested privilege level of 00. The global descriptor table is

.c

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st

stored in memory as shown below.

Dept of CSE, SJBIT

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10CS45

.c

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st

ud
en
ts

gr
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c

om

MICROPROCESSORS

Descriptor number 1 contains a descriptor that defines the base address as 00100000h with a

segment limit of 000FFh. This refers to memory locations 00100000h 001000FFh for the data

segment.

2.2 PROGRAM-INVISIBLE REGISTERS:

The global and local descriptor tables are found in the memory system. In order to specify the
address of these tables, Pentium 4 contains program invisible registers LDTR and GDTR (these
registers are not directly addressed by software).
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MICROPROCESSORS

10CS45

The GDTR (global descriptor table register), LDTR (local descriptor table register) and IDTR
(interrupt descriptor table register) contain the base address of the descriptor table and its limit.

The limit of these descriptor tables is 16 bits because the maximum table length is 64K bytes

om

(but of course, the table could be smaller than 64K byte, hence the need for the limit).

Before using the protected mode, the interrupt descriptor table, global descriptor table along with

gr
ou
p.
c

the corresponding registers IDTR and GDTR must be initialized. This is why the Pentium 4

boots in the real mode not protected mode, and why the maximum descriptor table size is 64K

.c

ity
st

ud
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ts

bytes.

Each of the segment registers also contains a program-invisible portion used as a cache to store
the corresponding 8 byte descriptor to avoid repeatedly accessing memory every time the
segment register is referenced (hence the term cache).
These program-invisible registers are loaded with the base address, limit, and access rights each
Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

time the number in the segment register is changed.


The TR (task register) holds a selector, which accesses a descriptor that defines a task. A task is
most often a procedure or application program. The descriptor for the procedure or application
program is stored in the global descriptor table, so access can be controlled through the privilege

om

levels. The task register allows a context or task switch in multitasking systems in about 17s.
Notice: The memory system for the Pentium 4 is 4G bytes in size, but access to the area

gr
ou
p.
c

between 4G and 64G is enabled with bit position 4 of the control register CR4 and is accessible
only when 4M paging is enabled. When in this paging mode, address lines A35 A32 are
enabled with a special new addressing mode, controlled by other bits in CR4.

2.3 Memory Paging

Paging is enabled when the PG bit in control register CR0 is set. The paging mechanism can
function in both the real and protected modes.

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When paging is enabled, physical memory is divided into small blocks (typically 4K bytes or
4M bytes) in size, and each block is assigned a page number. The operating system keeps a list
of free pages in its memory. When a program makes a request for memory, the OS allocates a
number of pages to the program.

A key advantage to memory paging is that memory allocated to a program does not have to be

ity
st

contiguous, and because of that, there is very little internal fragmentation - thus little memory is
wasted.

THE PAGE DIRECTORY AND PAGE TABLE


To convert a 32-bit linear address into a 32-bit physical address, we need to understand that

.c

the most significant 20 bits of the linear address indicate the linear page number, while the

least significant 12 bits of the linear address indicate the offset within this page. The offset
should remain the same but the linear page number has to be converted into a physical page

number.

Dept of CSE, SJBIT

Page 40

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10CS45

gr
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c

om

MICROPROCESSORS

Each page directory entry is a physical address pointing to a page table, which contains page
table entries. Each page table contains 1024 page table entries, each of which is 4 bytes (32
bits). This means that each page table is 4 K bytes long.

Each page table entry points to the starting physical address of a page in memory (i.e., the
physical page number).

ud
en
ts

This means that if we have one page directory and 1024 page tables, then we have a total of 1M
table entries or 1 M pages. Since each page is 4K bytes long, this will cover a total of 4G bytes
of maximum physical memory.

The figure below Part (a) shows the linear address (generated by the software) and how it selects
one of the 1024 page directory entries from the page directory (using the left most 10 bits) and

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st

then selects one of the 1024 page table entries (using the next 10 bits). Part (b) of the figure
shows the page table entry, which contains the physical number that must be associated with the
offset.

For example, the linear addresses 00000000h-00000FFFh access the first page directory entry,

.c

and the first page table entry. Notice that one page is a 4K-byte address range. So, if that page

table entry contains 00100000h, then the physical address of this page is 00100000h-00100FFFh
for linear address 00000000h-00000FFFh. This means that when the program accesses a location

between 00100000h and 00100FFFh, the microprocessor physically addresses location

00100000h-00100FFFh.

Dept of CSE, SJBIT

Page 41

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MICROPROCESSORS

10CS45

For example, the linear addresses 00000000h-00000FFFh access the first page directory entry,
and the first page table entry. Notice that one page is a 4K-byte address range. So, if that page
table entry contains 00100000h, then the physical address of this page is 00100000h-00100FFFh

om

for linear address 00000000h-00000FFFh. This means that when the program accesses a location
between 00100000h and 00100FFFh, the microprocessor physically addresses location

gr
ou
p.
c

00100000h-00100FFFh.

2.4 8086 Addressing Modes for accessing data

.c

ity
st

ud
en
ts

The procedure for converting linear addresses into physical addresses:

Dept of CSE, SJBIT

Page 42

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MICROPROCESSORS

10CS45

Addressing modes provide convenience in accessing data needed in an instruction.

Immediate

Register addressing

Addressing mode
(for source

2.4.1 Immediate Addressing

Before

DX ABCDH

I/O port addressing

After

1234H

Before

After

4DH

23H

.c

ity
st

Ex1: MOV DX, 1234H

Memory addressing

ud
en
ts

operand only)

gr
ou
p.
c

om

8086 Addressing Modes for accessing data

CH

Ex2: MOV CH, 23H

Dept of CSE, SJBIT

Page 43

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MICROPROCESSORS

10CS45

2.4.2 Register Addressing

CX 1234H

5678H

SI 5678H

5678H

Dl

89H

BCH

AH

BCH

BCH

.c

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st

Ex2: MOV DL, AH

After

ud
en
ts

Before

gr
ou
p.
c

Ex1: MOV CX, SI

After

om

Before

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MICROPROCESSORS

10CS45

Memory Addressing

Indirect Addressing

om

Direct Addressing

Based Addressing Indexed

Indirect

with

Addressing with

displacement

displacement

Based

Based Indexed

Indexed

addressing with

addressing

displacement

.c

ity
st

ud
en
ts

Register

gr
ou
p.
c

Memory Indirect Addressing

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

2.4.3 Memory Direct Addressing

BX

ABCDH

DS:5634H

45H

DS:5635H

86H

CL

F2H

DS:5634H

45H

DS:5635H

86H

.c

ity
st

Ex2: MOV CL, DS:5634H

LS byte

MS byte

After

ud
en
ts

Before

8645H

Before

45H

After

Program

Ex3: MOV BH, LOC

om

Ex1: MOV BX, DS:5634H

After

gr
ou
p.
c

Before

BH

C5H

78H

.DATA
LOC

DB

78H

Dept of CSE, SJBIT

Page 46

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MICROPROCESSORS

10CS45

2.4.4.Register Indirect Addressing

CL

20H

SI

3456H

78H

ud
en
ts

DS:3456H

Before

DX

F232H

BX

A2B2H

After

3567H

DS:A2B2H

67H

LS byte

DS:A2B3H

35H

MS byte

.c

ity
st

Ex2: MOV DX, [BX]

78H

om

Ex1: MOV CL, [SI]

After

gr
ou
p.
c

Before

Dept of CSE, SJBIT

Page 47

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MICROPROCESSORS

10CS45

AH

30H

DI

3400H

DS:3400H

86H

86H

om

Ex3: MOV AH, [DI]

After

gr
ou
p.
c

Before

Only SI, DI and BX can be used inside [ ] from memory addressing point of view. From user

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ts

point of view [BP] is also possible. This scheme provides 3 ways of addressing an operand in

.c

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st

memory.

Dept of CSE, SJBIT

Page 48

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MICROPROCESSORS

10CS45

2.4.5 Based Addressing with displacement

DH

2345H is 16-bit displacement

BX

DS:6345H

67H

Before

AX 1000H

After

CDABH

.c

ity
st

Ex2: MOV AX, 45H[BP]

67H

4000H

ud
en
ts

4000 + 2345 = 6345H

45H

gr
ou
p.
c

Ex1: MOV DH, 2345H[BX]

After

om

Before

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Page 49

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MICROPROCESSORS

10CS45

BP

3000H

SS:3045H

ABH

LS byte

It is SS when BP is used

SS:3346H

CDH

MS byte

gr
ou
p.
c

3000 + 45 = 3045H

om

45H is 8-bit displacement

Base register can only be BX or BP. This scheme provides 4 ways of addressing an operand in
memory.

ud
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ts

2.4.6 Indexed Addressing with displacement

Before

ity
st

Ex1: MOV CL, 2345H[SI]

.c

2345H is 16-bit displacement

60H

85H

SI 6000H

DS:8345H

85H

6000 + 2345 = 8345H

CL

After

After

Before

Ex2: MOV DX, 37H[DI]

DX 7000H

B2A2H

Dept of CSE, SJBIT

Page 50

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MICROPROCESSORS

10CS45

5000H

DS:5037H

A2H

LS byte

DS:5038H

B2H

MS byte

om

5000H+ 37H = 5037H

DI

gr
ou
p.
c

37H is 8-bit displacement

Index register can only be SI or DI. This scheme provides 4 ways of addressing an operand in
memory.
2.4.7Based Indexed Addressing

Ex1: MOV CL, [SI][BX]

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Before

CL

40H

After

67H

BX

0300H

.c

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st

SI 2000H

DS:2300H

67H

2000H + 0300H = 2300H

Before

Ex2: MOV CX, [BP][DI]

CX

6000H

After

6385H

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

0020H

gr
ou
p.
c

DI

om

BP 3000H

2000H + 0300H = 2300H

SS:3020H

85H

LS byte

It is SS when BP is used

SS:3021H

63H

MS byte

This scheme provides 4 ways of addressing an operand in memory. One register must be a Base

ud
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register and the other must be an Index register.

For ex. MOV CX, [BX][BP] is an invalid instruction.

.c

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st

2.4.6 Based Indexed Addressing with Displacement

DL

40H

BX

2000H

DI

0050H

After

12H

Ex1: MOV DL, 37H[BX+DI]

Before

37H is 8-bit displacement

Dept of CSE, SJBIT

Page 52

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MICROPROCESSORS

10CS45

DS:2087H

12H

Before

BX

3000H

3665H

gr
ou
p.
c

Ex2: MOV BX, 1234H[SI+BP]

After

om

2000H + 0050H + 37H = 2300H

SI 4000H

ud
en
ts

BP 0020H

4000H + 0020H +1234 = 5254H

SS:5254H

65H

LS byte

It is SS when BP is used

SS:5255H

36H

MS byte

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st

This scheme provides 8 ways of addressing an operand in memory.


2.4.7 Memory modes as derivatives of Based Indexed Addressing with Displacement
Instruction

Base

Displace

Register

ment

No

No

Yes

Direct Addressing

No

Yes

No

Register Indirect

MOV DX, [BX]

Yes

No

No

MOV DH, 2345H[BX}

Yes

No

Yes

.c

Index

Register

MOV BX, DS:5634H

MOV CL, [SI]

Addressing mode

Based Addressing with

Dept of CSE, SJBIT

Page 53

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MICROPROCESSORS

10CS45

Displacement
MOV DX, 35H[DI]

No

Yes

Yes

Indexed Addressing with

om

displacement
MOV CL, 37H[SI+BX]

Yes

Yes

No

Based Indexed Addressing

MOV DL, 37H[BX+DI]

Yes

Yes

Yes

Based Indexed Addressing

2.4.8 I/O port Addressing

ud
en
ts

I/O port Addressing

gr
ou
p.
c

with displacement

Variable port addressing

Or Direct Port addressing

Or Indirect port addressing

ity
st

Fixed port addressing

IN AL, 83H

Before
AL 34H

After
78H

Input port no. 83H 78H

Ex. 1:

.c

Fixed Port Addressing

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

Before
IN AX, 83H

AX 5634H

F278H

om

Ex. 2:

After

Input port no. 84H F2H

gr
ou
p.
c

Input port no. 83H 78H

Before
OUT 83H, AL

AL 50H

ud
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ts

Ex. 3:

Output port no. 83H 65H

Before

OUT 83H, AX

After

Output port no. 83H 65H

50H

Output port no. 84H 40H

60H

.c

50H

AX 6050H

ity
st

Ex. 4:

After

IN and OUT instructions are allowed to use only AL or AX registers. Port address in the range

00 to FFH is provided in the instruction directly.


2.4.9.Variable Port Addressing

I/O port address is provided in DX register. Port address ranges from 0000 to FFFFH. Data
transfer with AL or AX only.

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

Before
IN AL, DX

AL 30H

60H

om

Ex. 1:

After

Input port no. 1234H 60H

Before
IN AX, DX

AX 3040H

After

7060H

ud
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ts

Ex. 2:

gr
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c

DX 1234H

DX 4000H

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st

Input port no. 4000H 60H

OUT DX, AL

Ex. 3:

.c

Input port no. 4001H 70H

Before

After

AL 65H

DX 5000H

Output port no. 5000H 80H

65H

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

Before
OUT DX, AX

AX 4567H

om

Ex. 4:

After

gr
ou
p.
c

DX 5000H

67H

Output port no. 5001H 36H

45H

.c

ity
st

ud
en
ts

Output port no. 5000H 25H

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

Unit - 3
3.1

8086 Instruction set

om

Abbreviations used

gr
ou
p.
c

R8= AL/BL/CL/DL/ AH/BH/CH/DH


R16=AX/BX/CX/DX/ SI/DI/BP/SP

R=R8/R16

SR=CS/DS/ES/SS

AR=SI/DI/BX/BP

d16=16-bit data

d8=8-bit data

a8=8-bit I/O port address

ud
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ts

M8=contents of byte memory


M16=contents of word memory

M=M8/M16

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st

Conventions used:

MOV

.c

R, M

and
MOV

M, R

POP

R16

R16

for PUSH

R16

and

PUSH/POP

for MOV

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MICROPROCESSORS

ROR R/M,

1/CL

for ROR R,1 ROR M,1

ROR R,CL ROR M, CL

8086 Instruction set types

om

3.1.1

10CS45

Data Transfer instructions Ex. MOV BX, CX


Arithmetic instructions Ex. ADD BX, CX
Logical group of instructions Ex. AND BX, CX

Branch group Ex. JNC LOCN


String instructions Ex. MOVS

I/O group Ex. IN AL, 30H

ud
en
ts

Stack group Ex. PUSH DX

gr
ou
p.
c

Instructions are normally discussed under:

Interrupt instructions Ex. INT 21H

ity
st

Data Transfer group, Arithmetic group, Logical group, Stack group, and I/O group of
instructions explained first. They occupy several chapters in books.
Here, I explain them under:

2-operand instructions Ex. ADD BX, CX

.c

1-operand instructions Ex. PUSH SI

0-operand instructions: Ex. DAA

Branch group, String instructions, and Interrupt instructions are explained later.

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

3.2Operand instructions

MOV/XCHG

Data transfer
R

Arithmetic

gr
ou
p.
c

ADD/ADC/SUB/SBB

om

3.2.1Operand instructions involving R and R/M

AND/OR/XOR/TEST/CMP

R/M

Logical

11 instructions x 210= 11264 opcodes

ud
en
ts

MOV instruction already discussed- see Instruction template


In data transfer instructions flags are not affected.
3.2.2 Exchange Instruction

ity
st

XCHG DX, [BX]

Before

After

DX

1234H

ABCDH

BX

1000H
1234H

DS:1002H

.c

DS:1000H ABCDH

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

3.2.3 Add instruction


Unlike in 8085, result of add/subtract can be in any register or memory location

1234H

BX

1000H

In 3234H, 34H has

DS:1000H

2000H

3234H

three 1s. So P flag =0

DS:1002H

Before

After

30H

81H

ADC DH ,[SI]

DH

Add with Carry

Carry flag

gr
ou
p.
c

DX

ud
en
ts

ADD [BX], DX

After

om

Before

SI 2000H

81H

50H

DS:2001H

60H

ity
st

1000 0001B(Two 1s)

DS:2000H

.c

New flag values: Ac=0, S=1, Z=0, V=1, P=1

After

DH

30H

0BH

CL

25H

SUB DH, CL

Before

Subtract (without borrow)

0BH =

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MICROPROCESSORS

10CS45

0000 1011B(Three 1s)

After

20H

FAH

DH

Subtract (with borrow)

Cy flag
CL

25H

FAH =1111 1010(Six 1s)

gr
ou
p.
c

SBB DH, CL

Before

om

New flag values: Ac=1, S=0, Z=0, V=0, P=0, Cy=0

2s complement of FAH=0000 0110 = +06 So, FAH = -06

ud
en
ts

New flag values: Ac=1, S=1, Z=0, V=0, P=1, Cy=1

Discussion about Overflow (V) flag V

23H (+ve)

43H (+ve)

+ 46H (+ve)

+ 54H (+ve)
= 97H (-ve)

V= 0, Cy = 0

ity
st

= 69H (+ve)

V = 1, Cy = 0
Wrong answer

.c

Correct answer

Overflow used with signed numbers only

Carry flag used with unsigned numbers only

83H (-ve)

F2H (-ve)

+ 94H (-ve)

+ F3H (-ve)

Dept of CSE, SJBIT

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10CS45

= 17H (+ve)

= E5H (-ve)

V= 1, Cy = 1

V = 0, Cy = 1

Wrong answer

Correct answer

F6H (-ve)

- 83H (-ve)

- 43H (+ve)

= 11H (+ve)

= B3H (-ve)

V= 0, Cy = 0

V = 0, Cy = 0

Correct answer

Correct answer

gr
ou
p.
c

94H (-ve)

= 71H (+ve)
V= 1, Cy = 0

- 83H (-ve)

= E3H (-ve)

V = 1, Cy = 1

Wrong answer

ity
st

Wrong answer

66H (+ve)

ud
en
ts

94H (-ve)
- 23H (+ve)

om

MICROPROCESSORS

.c

3.2.4 AND instruction

AND BH, CL

Subtract (with borrow)

AND
CL

After

56H

06H

0FH

0FH=0000 1111B

BH

Before

06H=0000 0110B

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

Use: Selectively reset to 0 some bits of the destination


Bits that are ANDed with 0s are reset to 0

3.2.5 OR instruction

OR BH, CL
56H=0101 0110B

BH

56H

CL

0FH

OR

0FH=0000 1111B

5FH

ud
en
ts

5FH=0101 1111B

After

gr
ou
p.
c

Before

om

Bits that are ANDed with 1s are not changed

Use: Selectively set to 1 some bits of the destination


Bits that are ORed with 1s are set to 1

ity
st

Bits that are ORed with 0s are not changed

3.2.6 Ex-OR instruction

XOR BH, CL

.c

56H=0101 0110B

After

56H

59H

BH

XOR
CL
0FH

0FH=0000 1111B

Before

59H=0101 1001B

Use: Selectively complement some bits of the destination.

Bits that are XORed with 1s are complemented


Bits that are XORed with 0s are not changed

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

3.2.7 TEST instruction

BH

56H

56H

56H=0101 0110B

AND

0FH=0000 1111B

CL

0FH

0FH

Temp

45H

06H=0000 0110B
Only flages are affected

gr
ou
p.
c

TEST BH, CL

After

om

Before

06H

TEST basically performs AND operation. Result of AND is not stored

in destination. It is stored in Temp register. Temp is not accessible to

3.2.8 Compare Instruction

CMP BH, CL

ud
en
ts

programmer. There is no instruction like MOV Temp, 67H

BH

ity
st

56H=0101 0110B
0FH=0000 1111B

Before

After

56H

56H

CL

0FH

Temp

45H

47H

.c

Only flags are affected

CMP basically performs Subtract operation. Result of CMP is not

stored in destination. It is stored in Temp register. Temp is not

accessible to programmer.

Dept of CSE, SJBIT

Page 65

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MICROPROCESSORS

10CS45

3.3 Operand Instructions involving immediate data

ADD/ADC/SUB/SBB

R/M, d8/d16

8 byte registers + 8 word registers+ 24 byte


memory + 24 word memory = 64 opcodes
10 instructions x 64 = 640 opcodes

gr
ou
p.
c

AND/OR/XOR/TEST/CMP

om

MOV

3.3.1 Move Immediate data to a Register/ Memory location

MOV DX, ABCDH

DX

BH

ity
st

MOV BH, 12H

ud
en
ts

Before

After

1234H

ABCDH

Before

After

56H

12H

.c

3.3.2 Add Immediate data to a Register/ Memory location

BX

1000H

DS:1000H

20H

After

ADD [BX], 12H

Before

32H

DS:1001H

Dept of CSE, SJBIT

Page 66

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MICROPROCESSORS

10CS45

Before
BX 1000H

3234H

DS:1002H

gr
ou
p.
c

DS:1000H 2000H

om

ADD [BX], 1234H

After

3.3.3 Add with Carry Immediate data to a Register/ Memory location

Before
DH

30H

ud
en
ts

ADC DH, 32H


Add with Carry

Carry flag

After
63H
0

63H= 0110 0011 It has four 1s

New flag values: Ac=0, S=0, Z=0, V=0, P=1

.c

ity
st

3.3.4 Subtract Immediate data from a Register/ Memory location

SUB DH, 40H

DH

Before

After

30H

F0H

Subtract (without borrow)

New flag values: Ac=0, S=1, Z=0, V=0, P=1, Cy=1

F0H=1111 0000 B(Four 1s)

3.3.5 Subtract with borrow Immediate data from a Register/ Memory location

Dept of CSE, SJBIT

Page 67

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MICROPROCESSORS

10CS45

SBB DH, 25H

DH

Subtract (with borrow)

Cy flag

Before

After

20H

06H

om

06H= 0000 0110B(Two 1s)

gr
ou
p.
c

New flag values: Ac=1, S=0, Z=0, V=0, P=1, Cy=1

3.3.6 AND Immediate data with a Register/ Memory location

Before
AND BH, 0FH

BH
AND

0FH = 0000 1111B

ud
en
ts

56H = 0101 0110B

56H

Cy flag

06H = 0000 0110B(Two 1s)

After
06H

Use: Selectively reset to 0 some bits of the destination

ity
st

Bits that are ANDed with 0s are reset to 0

.c

Bits that are ANDed with 1s are not changed

3.3.7 OR Immediate data with a Register/ Memory location

OR BH, 0FH
56H = 0101 0110B

BH

Before

After

56H

5FH

OR

Dept of CSE, SJBIT

Page 68

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MICROPROCESSORS

10CS45

0FH = 0000 1111B

CL

0FH

5FH = 0101 1111B


Use: Selectively set to 1 some bits of the destination

om

Bits that are ORed with 1s are set to 1

gr
ou
p.
c

Bits that are ORed with 0s are not changed

3.3.8 Ex-OR Immediate data with a Register/ Memory location

Before
XOR BH, 0FH

BH

0FH = 0000 1111B


59H = 0101 1001B

XOR

59H

ud
en
ts

56H = 0101 0110B

56H

After

CL

0FH

Use: Selectively complement some bits of the destn.


Bits that are XORed with 1s are complemented

ity
st

Bits that are XORed with 0s are not changed

.c

3.3.9 Test immediate data with a Register/ Memory location

TEST BH, 0FH

After

BH

56H

56H

Temp

45H

06H

AND

56H=0101 0110B

Before

0FH=0000 1111B

Dept of CSE, SJBIT

Page 69

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MICROPROCESSORS

10CS45

TEST basically performs AND operation. Result of AND is not stored in


destination. It is stored in Temp register. Temp is not accessible to
programmer. There is no instruction like MOV Temp, 67H. Only flags
are affected.

Before
CMP BH, 0FH

56H

Temp

45H

AND

After
56H

47H

ud
en
ts

56H=0101 0110B

BH

gr
ou
p.
c

3.4 Compare immediate data with a Register/ Memory location

om

06H=0000 0110B

CMP basically performs Subtract operation. Result of CMP is not stored in


destination. It is stored in Temp register. Temp is not accessible to
programmer. Only Flags are affected based result of subtraction.

ity
st

3.4.1 Operand Instructions involving SR and R16/M16

SR
R16/M16

.c

MOV

After

DS

1122H

2233H

CX

2233H

MOV DS, CX

Before

Dept of CSE, SJBIT

Page 70

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MICROPROCESSORS

10CS45

Note that there is no instruction to load an immediate data to a Segment


register.

MOV DS, [BX]

DS

1122H

BX

2000H

DS:2000H

2233H

After

gr
ou
p.
c

Before

om

No. of opcodes = 2 x 4 x (8+24) = 256

2233H

ud
en
ts

3.4.2 Operand Instructions to perform Input operation

IN AL/AX, a8/DX

4 opcodes

AL

ity
st

IN AL, DX

DX

Before

After

50H

45H

2111H

.c

Input port no. 2111H 45H

IN AL, 30H

Before
AL

After
45H

50H
Input port no. 30H
45H

Dept of CSE, SJBIT

Page 71

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MICROPROCESSORS

IN AX, DX

10CS45

Before

After

AX 3050H

4045H

45H

Input port no. 61H

40H

gr
ou
p.
c

Input port no. 60H

om

DX 1177H

3.4.3 Operand Instructions to perform Output operation

OUT a8/DX, AL/AX

4 opcodes

OUT 30H, AL

ud
en
ts

Before

After

AL

50H

ity
st

Out port no. 30H

50H

Before

After

AX

3050H

DX

2177H

Out port no. 2177H

45H

50H

Out port no. 2178H

40H

30H

Before

After

.c

OUT DX, AX

40H

OUT 60H, AX

AX

3050H

Dept of CSE, SJBIT

Page 72

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10CS45

Out port no. 60H

45H

50H

Out port no. 61H

40H

30H

3.4.4 Operand Instructions to perform Shift/Rotate operation

R/M, 1/CL

gr
ou
p.
c

ROR /ROL /RCR /RCL /SHR /SHL /SAR

om

MICROPROCESSORS

7 instructions x (16+48) x 2 = 896 opcodes

SHR and SHL: for shifting left / right unsigned numbers

ud
en
ts

SAR used Shifting right a signed number

SHL is also called as SAL, as method for shift left of signed or unsigned number is the same
ROR R/M, 1/CL

Used for division by power of 2

ity
st

CL has no. of times rotation is to be done

R/M

.c

ROR BH, 1

Rotate right without cy

Cy

BH

Cy

Before

After

0100 0010

0010 0001

RCR R/M, 1/CL


Dept of CSE, SJBIT

Page 73

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MICROPROCESSORS

10CS45

CL has no. of times rotation is to be done

Rotate right with cy

Before
0100 0010

Cy

R/M

ity
st

Cy

Before

After

BH

0010 0010

1000 1000

CL

02H

Cy

.c

Rotate left without cy

1010 0001

Used for multiplication by 2n

ROL R/M, 1/CL

ROL BH, CL

After

ud
en
ts

BH

Cy

om

R/M

gr
ou
p.
c

RCR BH, 1

Dept of CSE, SJBIT

Page 74

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MICROPROCESSORS

10CS45

RCL R/M, 1/CL

R/M

Before
BH

0010 0010

CL

02H

Cy

After

gr
ou
p.
c

Rotate left with cy

om

Cy

1000 0010

ud
en
ts

RCL BH, CL

Used for multiplication by 2n

SHL R/M, 1/CL

SHL BH, CL

Cy

R/M

ity
st

Shift left without cy

.c

BH

Before

After

0010 0010

1000 1000

CL

02H

Cy

Used for division by 2n of unsigned nos

SHR R/M, 1/CL


SHR BH, CL

R/M

Cy

Dept of CSE, SJBIT

Page 75

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MICROPROCESSORS

10CS45

After

BH

0100 0100

0001 0001

CL

02H

Cy

om

Before

gr
ou
p.
c

Shift right

Used for division by 2n of signed nos

SAR R/M, 1/CL

R/M

Shift right
BH

1111 0000 = -10H

CL

Before

After

1100 0000

1111 0000

02H

ity
st

1100 0000 = -40H

Cy

ud
en
ts

SAR BH, CL

.c

Cy

3.4.5 Operand instruction to load an Effective address into an Address Register

4 x 24 = 96 opcodes

LEA AR, a16

LEA BX, [SI]

BX

Before

After

1000H

2000H

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

LEA BX, [SI] functionally same as

SI

2000H

DS:2000H

3000H

LDS AR, M32

gr
ou
p.
c

3.4.6 Operand instruction to load DS and an Address Register from memory

om

MOV BX,SI

4 x 24 = 96 opcodes

Before
DS 2000H

ud
en
ts

LDS SI, 3000H

After

7000H

Loads DS and SI using single instruction

SI 1000H

DS:3000H

6000H

6000H

ity
st

DS:3002H

7000H

.c

3.4.7 Operand instruction to load ES and an Address Register from memory


4 x 24 = 96 opcodes

LES AR, M32

Dept of CSE, SJBIT

Page 77

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10CS45

Before

After
7000H

LES DI, 3000H

ES

2000H

Loads ES and DI using single

DI

1000H

2000:3000H

6000H

2000:3002H

7000H

.c

ity
st

ud
en
ts

instruction

gr
ou
p.
c

6000H

om

MICROPROCESSORS

Dept of CSE, SJBIT

Page 78

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MICROPROCESSORS

10CS45

3.5 Operand instruction types

INC/ DEC/ NOT/NEG R/M

PUSH/ POP

gr
ou
p.
c

4 x (16+48) = 256 opcodes

om

R16/M16/SR/F

2 x (8+24+4+1) = 74 opcodes

MUL/ IMUL/ DIV/ DIV R/M

ud
en
ts

4 x (16+48) = 256 opcodes

Increment R16

8 opcodes

Before

After

Ex. 1

BX

1234H

1235H

FFFFH

0000H

.c

Ex. 2

ity
st

INC BX

INC DH

Ex. 1

Increment R8

8 opcodes

Before

After

DH

12H

13H

DH

FFH

00H

Ex. 2

BX

Increment M8

Dept of CSE, SJBIT

Page 79

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MICROPROCESSORS

10CS45

INC byteptr [BX]

Before
BX 2000H
DS:2000H

FFH

00H

DS:2001H

12H

12H

om

24 opcodes

After

gr
ou
p.
c

NOTE:- In this instruction there is a single operand, [BX]. It is not clear whether it is byte or
word operand. Byteptr assembler directive announces to the assembler that it is a byte operation.

Increment M16

INC wordptr [BX]

BX 2000H

After

ud
en
ts

24 opcodes

Before

DS:2000H

FFH

00H

DS:2001H

12H

13H

.c

DEC BX

ity
st

NOTE:- In this instruction there is a single operand, [BX]. It is not clear whether it is byte or
word operand. wordptr assembler directive announces to the assembler that it is a word
operation.

8 opcodes

Before

After

Ex. 1

BX

1234H

1233H

Ex. 2

BX

0000H

FFFFH

Before

After

12H

11H

w
w
w

Decrement R16

Decrement R8
DEC DH
Ex. 1

8 opcodes
DH

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

Ex. 2

DH

00H

FFH

Before

24 opcodes

BX

After

2000H

DS:2000H

00H

DS:2001H

12H

FFH

gr
ou
p.
c

DEC byteptr [BX]

om

Decrement M8

12H

ud
en
ts

NOTE:-In this instruction there is a single operand, [BX]. It is not clear whether it is byte or
word operand. Byteptr assembler directive announces to the assembler that it is a byte operation.
Decrement M16
DEC wordptr [BX]
Before
After
24 opcodes

BX

2000H

DS:2000H

00H

FFH

DS:2001H

12H

11H

ity
st

NOTE:- In this instruction there is a single operand, [BX]. It is not clear whether it is byte or
word operand. wordptr assembler directive announces to the assembler that it is a word
operation.

.c

Perform 1s complement of R16

8 opcodes

Before

After

1234H

EDCBH

BX

NOT BX

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

NOT operation performs 1s complement.

3.5.1 Perform 1s complement of R8


8 opcodes
DH

NOT byteptr [BX]

Before

After

12H

EDH

Before

24 opcodes

BX

23H

ud
en
ts

DS:2000H

2000H

gr
ou
p.
c

NOT DH

DS:2001H

12H

om

Easy way: Subtract each hex digit from F

Perform 1s complement of M8
After

DCH
12H

ity
st

NOTE:- In this instruction there is a single operand, [BX]. It is not clear whether it is byte or
word operand. Byteptr assembler directive announces to the assembler that it is a byte operation.

NOT wordptr [BX]

BX

After

2000H

DS:2000H

34H

CBH

DS:2001H

12H

EDH

.c

24 opcodes

Before

Perform 1s complement of M16

NOTE:- In this instruction there is a single operand, [BX]. It is not clear whether it is byte or
word operand. wordptr assembler directive announces to the assembler that it is a word
operation.

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

NEG BX

8 opcodes

Before

After

1234H

EDCCH

BX

Easy way: Subtract each hex digit from F and add 1

Perform 2s complement of R8

8 opcodes

Before

DH

12H

ud
en
ts

NEG DH

gr
ou
p.
c

NEG operation performs 2s complement.

om

Perform 2s complement of R16

After
EEH

3.5.2 Perform 2s complement of M8

NEG byteptr [BX]

BX

After

2000H

DS:2000H

23H

DDH

DS:2001H

12H

12H

.c

ity
st

24 opcodes

Before

NOTE:- In this instruction there is a single operand, [BX]. It is not clear whether it is byte or
word operand. Byteptr assembler directive announces to the assembler that it is a byte operation.

3.5.3 Perform 2s complement of M16

NEG wordptr [BX]


24 opcodes

Before
BX

After

2000H

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

DS:2000H

34H

CBH

DS:2001H

12H

EDH

PUSH R16

Ex. PUSH CX

Before
1234H

SP

5678H

After

ud
en
ts

CX

gr
ou
p.
c

om

NOTE:- In this instruction there is a single operand, [BX]. It is not clear whether it is byte or
word operand. wordptr assembler directive announces to the assembler that it is a word
operation.

5676H

Empty

Empty
Full

SS: 5676H

1122H

SS:5678H

3344H

Full

1234H
3344H

.c

ity
st

Suppose SP content is 5678H. It means locations 5678, 567A, 567C in stack segment are full.
Locations 5676, 5674, are empty. Information pushed to location 5676 and SP value changes
to 5676H. Push operation is always on 16 bit data.

3.5.4 PUSH M16

Ex. PUSH [BX]

Before
BX

1234H

SP

3366H

DS:1234H

5678H

After

3364H

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

Empty
SP: 5676H

1122H

Full

SP: 5678H

3344H

Full

5678H
3344H

om

Empty

Ex. PUSH CS

Before
CS

1234H

SP

5678H

gr
ou
p.
c

PUSH SR

After

5676H

Empty

.c

Ex. PUSHF

1122H

SS: 5678H

3344H

Before

Flags

1234H

SP

5678H

1234H
3344H

PUSH Flags

After

5676H
Empty

Empty

SS: 5676H

1122H

Full

SS: 5678H

3344H

Full

Full

1234H
3344H

SS: 5676H

ity
st

Full

ud
en
ts

Empty

Ex. POP CX

POP R16

Before

After

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MICROPROCESSORS

10CS45

CX 1234H

1122H

SP 5678H

567AH

Full

SS: 5678H 1122H


3344H

1122H

Full

3344H

gr
ou
p.
c

SS: 567AH

Empty

om

Empty

NOTE:- Suppose SP content is 5678H. It means locations 5678, 567A, 567C in stack segment
are full. Locations 5676, 5674, are empty. Information poped from location 5678 and SP
value changes to 567AH. Pop operation is always on 16 bit data.

Ex. POP [BX]

ud
en
ts

POP M16

Before

After

BX 1234H

3368H

DS:1234H 5678H

1122H

ity
st

Empty

SP 3366H

Full

SS: 3366H 1122H

Full

3344H

.c

SS: 3368H 3344H

Empty 1122H

POP SR

Ex. POP CS

Before

After

CS

1234H

1122H

SP

5678H

567AH

Empty

Dept of CSE, SJBIT

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MICROPROCESSORS

Full

10CS45

SS: 5678H

1122H

Empty

1122H

SS: 567AH

3344H

Full

3344H

Before
Flags

1234H

SP

5678H

SS: 5678H

1122H

SS: 567AH

3344H

Empty

1122H

567AH

Empty

1122H

Full

3344H

ud
en
ts

Full

After

gr
ou
p.
c

Ex. POPF

om

POP Flags

Before

After

CH

FEH

FEH

AL

02H

FCH

AH

34H

01H

01FCH = 508

.c

MUL CH

ity
st

Unsigned Multiply R8 with AL and store product in AX

Unsigned Multiply R16 with AX and store product in DX AX

MUL CX

Before

After

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MICROPROCESSORS

10CS45

00FEH

AX

0002H

01FCH

DX

1234H

0000H

01FCH = 508

om

CX 00FEH

IMUL CH

Before

CH

FEH

AL

02H

After

FCH

FFFCH = -04

ud
en
ts

FEH = -02

gr
ou
p.
c

Signed Multiply R8 with AL and store product in AX

AH

34H

FFH

NOTE:- IMUL CH instruction multiplies AL and CH treating them as signed numbers. The 16bit product is stored in AX.

Before

After

CH

F0H

AL

25H

01H

Quotient

AH

01H

35H

Remainder

.c

DIV CH

ity
st

Unsigned Division of AX by R8 and store quotient in AL and remainder in AH

NOTE:- DIV CH instruction divides AX by CH treating them as unsigned numbers. The 8-bit
quotient is stored in AL and the 8-bit remainder stored in AH.

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

Unsigned Division of DX AX by R16 and store quotient in AX and remainder in DX

Before

After

CX 00F0H

om

DIV CX

0001H

Quotient

DX 0000H

0035H

Remainder

gr
ou
p.
c

AX 0125H

NOTE:- DIV CX instruction divides DX AX by CX treating them as unsigned numbers. The 16bit quotient is stored in AX and the 16-bit remainder stored in DX.
Signed Division of AX by R8 and store quotient in AL and remainder in AH

Before

After

ud
en
ts

IDIV CH

CH

F0H

EE = -12H

AL

25H

EEH

Quotient

AH

01H

05H

Remainder

ity
st

F0H = -10H

.c

NOTE:-IDIV CH instruction divides AX by CH treating them as signed numbers. The 8-bit


quotient is stored in AL and the 8-bit remainder stored in AH.

Dept of CSE, SJBIT

Page 89

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MICROPROCESSORS

10CS45

3.5.5 8086 Instruction Template


Need for Instruction Template
8085 has 246 opcodes. The opcodes can be printed on an A4 size paper.

3-bit r1 code

3-bit r2 code

Register

000

001

010

011

100

101

ity
st

ud
en
ts

3-bit Register code

gr
ou
p.
c

Concept of Template
In 8085, MOV r1, r2 (ex. MOV A, B) has the following template.

om

8086 has about 13000 opcodes. A book of about 60 pages is needed for printing the opcodes.

110

M
A

.c

111

MOV A,
01 11 1
7

is

000 = 78H
8

Ex. 1: Code for

Ex.2: Code for

MOV M,
01 11 0

is

010 = 72H

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

Using the template for MOV r1, r2 we can generate opcodes of 26 = 64 opcodes.

1 0 0 0

gr
ou
p.
c

3.5.6 8086 Template for data transfer between REG and R/M

om

MOD

REG

R/M

2 bits

3 bits

3 bits

REG = A register of 8086 (8-bit or 16-bits) (except Segment registers, IP, and Flags registers)

ud
en
ts

Thus REG = AL/ BL/ CL/ DL/ AH/ BH/ CH/ DH/ AX/ BX/ CX/ DX/ SI/ DI/ BP/ SP

R/ M = Register (as defined above) or Memory contents (8-bits or 16-bits)

ity
st

W = 1 means Word operation


W = 0 means Byte operation

.c

D = 1 means REG is Destination register

D = 0 means REG is source register

MOD = 00 means R/M specifies Memory with no displacement

MOD = 01 means R/M specifies Memory with 8-bit displacement


MOD = 10 means R/M specifies Memory with 16-bit displacement
MOD = 11 means R/M specifies a Register

Dept of CSE, SJBIT

Page 91

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MICROPROCESSORS

10CS45

Register name
When W = 0

000

AX

AL

001

CX

CL

010

DX

DL

011

BX

100

SP

101

BP

110

SI

111

DI

gr
ou
p.
c

When W = 1

om

3-bit Register
code

BL

AH
CH

DH

ud
en
ts

BH

Aid to remember:

ALl Children Drink Bournvita (AL, CL, DL, BL)


SPecial Beverages SIamese DrInk (SP, BP, SI, DI)

ity
st

Case of MOD = 11

.c

Example: Code for MOV AX, BX treated as Move from BX to destination register AX

MOD

REG

R/M

11

00 0

011

AX is
destination

BX

1 0 0 0

Word
operation
B

= 8B C3H

Example: Alternative code for MOV AX, BX treating it as Move from source register BX to
register AX
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1 0 0 0

10CS45

MOD

REG

R/M

11

01 1

000

BX is
source

AX

Word
operation
9

gr
ou
p.
c

= 89 D8H

om

MICROPROCESSORS

There are 2 possible opcodes for MOV AX, BX as we can choose either AX or BX as REG.
Example: Code for MOV AL, BH treated as Move from BL to destination register AL

MOD

11

Byte
operation

REG

R/M

00 0

111

ud
en
ts

1 0 0 0

AL is
destination

= 8A C7H

BH

ity
st

Example: Alternative code for MOV AL, BH treating it as Move from source register BH to
register AL

MOD

REG

R/M

11

11 1

000

BH is
source

AL

Byte
operation

= 88 F8H

.c

1 0 0 0

There are 2 possible opcodes for MOV AL, BH as we can choose either AL or BH as REG.

Dept of CSE, SJBIT

Page 93

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MICROPROCESSORS

10CS45

MOD = 01

MOD = 10

No
Displacement

8-bit signed
displacement d8

16-bit signed
displacement d16

000

[SI+BX]

[SI+BX+d8]

[SI+BX+d16]

001

[DI+BX]

[DI+BX+d8]

[DI+BX+d16]

010

[SI+BP]

[SI+BP+d8]

[SI+BP+d16]

011

[DI+BP]

[DI+BP+d8]

100

[SI]

[SI+d8]

101

[DI]

[DI+d8]

110

[BP] Direct
Addressing

[BP+d8]

111

[BX]

[BX+d8]

gr
ou
p.
c

MOD = 00

ud
en
ts

R/M

om

Case of MOD = 00, 01 or 10

[DI+BP+d16]
[SI+d16]

[DI+d16]

[BP+d16]

[BX+d16]

ity
st

The table shows 24 memory addressing modes i.e. 24 different ways of accessing data stored in
memory.
Aid to remember:

.c

SubInspector DIxit is a BoXer ( [SI+BX] and [DI]+[BX] )

SubInspector DIxit knows to control BP ( [SI+BP] and [DI]+[BP] )

He says SImple DIet DIRECTs a BoXer' ( [SI], [DI], Direct addressing, [BX] )

Dept of CSE, SJBIT

Page 94

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MICROPROCESSORS

10CS45

MOD

REG

R/M

00

00 1

100

Byte
operation

No
Disp.

CL is
destination

[SI]

= 8A 0CH

gr
ou
p.
c

1 0 0 0

om

Ex: Code for MOV CL, [SI]

ud
en
ts

Note that there is a unique opcode for MOV CL, [SI] as CL only can be REG.

Ex: Code for MOV 46H[BP], DX

D
0

MOD

REG

R/M

d8

01

01 0

110

46H

ity
st

1 0 0 0 1 0

Word
operation

DX is [BP+d8]
source
6

.c

8-bit
Disp.

= 89 56 46H

Note that there is a unique opcode for MOV 46H[BP], DX as DX only can be REG.

Ex: Code for MOV 0F246H[BP], DX

Dept of CSE, SJBIT

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MICROPROCESSORS

MOD

REG

R/M

d16

10

01 0

110

F2 46H

Word
operation

16-bit
Disp.

DX is
source

[BP+d16]

= 89 96 F2 46H
Stored as 89 96
46 F2H

om

in Little Endian

gr
ou
p.
c

10CS45

Note that there is a unique opcode for MOV 0F246H[BP], DX as DX only can be REG.
Ex: Code for MOV [BP], DX

MOD

REG

R/M

d8

01

01 0

110

00H

Word
operation
8

= 89 56 00H

ud
en
ts

1 0 0 0 1 0

8-bit
Disp.

DX is [BP+d8]
source

Note that MOV [BP], DX is treated as MOV 00H[BP], DX before coding.

.c

ity
st

Ex: Code for MOV BX, DS:1234H

MOD

REG

R/M

Direct
addr

00

01 1

110

12
34H

Word
operation

No
Disp.

BX is
Dest.

Direct
addr.

Stored as 8B 1E
34 12H

In Little Endian

1 0 0 0 1 0

= 8B 1E 12 34H

Note that when MOD = 00 and R/M = 110, it represents Direct Addressing.
Dept of CSE, SJBIT

Page 96

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MICROPROCESSORS

10CS45

Unit 4
4.1 Branch group of instructions

om

Branch instructions provide lot of convenience to the programmer to perform operations selectively,
repetitively etc.

Uncondi-tional
jump

Conditional Jump instructions

Iteration
instructions

CALL instructions

Return
instructions

ud
en
ts

Conditional
jumps

gr
ou
p.
c

Branch group of instructions

Conditional Jump instructions in 8086 are just 2 bytes long. 1-byte opcode followed by 1-byte signed
displacement (range of 128 to +127).

ity
st

Conditional Jump Instructions

Jumps based on more than one flag

.c

Jumps based on a single flag

Jumps Based on a single flag


JZ r8

JNZ r8
JS r8
JNS r8
JC r8
JNC r8
JP r8

;Jump if zero flag set (if result is 0). JE also means same.
;Jump if Not Zero. JNE also means same.
;Jump if Sign flag set to 1 (if result is negative)
;Jump if Not Sign (if result is positive)
;Jump if Carry flag set to 1. JB and JNAE also mean same.
;Jump if No Carry. JAE and JNB also mean same.
;Jump if Parity flag set to 1. JPE (Jump if Parity Even) also means same.

Dept of CSE, SJBIT

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MICROPROCESSORS

JO r8
JNO r8

;Jump if No Parity. JPO (Jump if Parity Odd) also means same.


;Jump if Overflow flag set to 1 (if result is wrong)
;Jump if No Overflow (if result is correct)

JE is abbreviation for Jump if Equal.

JNE is abbreviation for Jump if Not Equal.

JB is abbreviation for Jump if Below.

JNAE is for Jump if Not Above or Equal.

JZ, JNZ, JC and JNC used after arithmetic operation

om

JNP r8

gr
ou
p.
c

Exa
mpl
es
for
JE
or
JZ
inst
ruc
tion

10CS45

Ex.
JE, JNE, JB, JNAE, JAE and JNB are used after a compare operation.
for
forward jump

Only examples using JE instruction given for forward and backward jumps.

ud
en
ts

CMP SI, DI
JE SAME

ADD CX, DX

Should be<=127 bytes

;Executed if Z = 0
(if SI not equal to DI)

ity
st

SUB BX, AX

;Executed if Z = 1
(if SI = DI)

.c

SAME:

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

Ex. for backward jump


;Executed if Z = 1 (if SI=DI)

om

BACK: SUB BX,AX


:
Should be <=127
bytes

CMP SI, DI
JE BACK
ADD CX,DX

;Executed if Z = 0 (if SI <> DI)

ud
en
ts

Jumping beyond -128 to +127?

gr
ou
p.
c

Requirement

What if

.c

>127 bytes

ity
st

CMP SI, DI

CMP SI, DI

JE SAME

JNE NEXT

ADD CX, DX

JMP SAME

NEXT:

ADD CX, DX

SUB BX, AX

SAME:

Then do this!

SAME:

SUB BX, AX

15

Range for JMP (unconditional jump) can be +2 = + 32K. JMP instruction discussed in detail later

Dept of CSE, SJBIT

Page 99

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MICROPROCESSORS

10CS45

4.2 Terms used in comparison

gr
ou
p.
c

Accordingly, all the following statements are true.

om

Above and Below used for comparing Unsigned numbers. Greater than and less than used when
comparing signed numbers. All Intel microprocessors use this convention.

95H is above 65H

Unsigned comparison - True

95H is less than 65H

Signed comparison True (as 95H is negative, 65H is positive)

65H is below 95H

Unsigned comparison - True

65H is greater than 95H

Signed comparison - True

ud
en
ts

4.2.1 Jump based on multiple flags

Conditional Jumps based on multiple flags are used after a CMP (compare) instruction.

JBE / JNA instruction

Jump if

.c

Cy = 1 OR Z= 1

ity
st

Jump if Below or Equal or Jump if Not Above

Ex.

Cy = 0 AND Z = 0

CMP BX, CX

Surely Above

JBE BX_BE

Below OR Equal

No Jump if

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

4.2.2 BX_BE (BX is Below or Equal) is a symbolic location

Jump if Not (Below or Equal) or Jump if Above

No Jump if

Cy = 0 AND Z= 0

Cy = 1 OR Z = 1

Surely Above

Below OR Equal

Ex.

gr
ou
p.
c

Jump if

om

4.2.3 JNBE / JA instruction

CMP BX, CX

JBE BX_BE

ud
en
ts

4.2.4 JLE / JNG instruction

Jump if Less than OR Equal or Jump if Not Greater than

Jump if

No Jump if

[(S=0 AND V=0) OR (S=1 AND V=1)] AND


Z=0

[(surely negative) or (wrong answer positive!)]


or Equal

[(surely positive) or (wrong answer negative!)]


and not equal

.c

ity
st

[(S=1 AND V=0) OR (S=0 AND V=0)] OR


Z=1

i.e.[S XOR V=0] AND Z=0

i.e. [S XOR V=1] OR Z=1

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

JNLE / JG instruction

No Jump if

gr
ou
p.
c

Jump if

om

Jump if Not (Less than OR Equal) or Jump if Greater than

[(S=1 AND V=0) OR (S=0 AND V=1)] OR


Z=1

[(surely positive) or (wrong answer negative!)]


and not equal

[(surely negative) or (wrong answer positive!)]


or equal

i.e. S XOR V=0 AND Z=0

i.e.S XOR V=1 OR Z=1

ud
en
ts

[(S=0 AND V=0) OR (S=1 AND V=1)] AND


Z=0

4.2.4 JL / JNGE instruction

Jump if Less than or Jump if NOT (Greater than or Equal)

ity
st

Jump if

No Jump if

[S=0 AND V=0] OR [S=1 AND V=1]

(surely negative)or (wrong answer


positive!)

(surely positive) or (wrong answer


negative!)

.c

[S=1 AND V=0] OR [S=0 AND V=1]

i.e. S XOR V=1

i.e.S XOR V=0

Note: When S=1, result cannot be 0

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

4.2.5 JNL / JGE instruction

om

Jump if Not Less than or Jump if Greater than OR Equal

No Jump if

[S=0 AND V=0] OR (S=1 AND V=1)

[S=1 AND V=0] OR (S=1 AND V=1)

(surely positive) or (wrong answer negative!)

(surely negative) or (wrong answer positive!)

i.e. S XOR V=0

i.e.S XOR V=1

gr
ou
p.
c

Jump if

Note: When S=0, result can be >= 0

ud
en
ts

Unconditional Jump instruction

Unconditional Jump Instruction

Far Jump or Inter segment Jump

ity
st

Near Jump or Intra segment Jump


(Jump within the segment)

.c

Near Unconditional Jump instruction

w
w
w

(Jump to a different segment)

Near Jump

Direct Jump (common)

2-bytes Short Jump (EB r8)

3-bytes Long Jump (E9 r16)

Indirect Jump (uncommon)

2 or more bytes

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

15

Range: + 2

Starting with FFH

Range: +2

Range: complete segment

4.2.5 Short Jump Instruction


2 byte (EB r8) instruction with Range: -128 to +127 bytes

gr
ou
p.
c

om

Three Near Jump and two Far Jump instructions have the same mnemonic JMP, but they have
different opcodes

ud
en
ts

For Backward jump: Assembler knows the quantum of jump. Generates Short Jump code if
<=128 bytes is the required jump. Generates code for Long Jump if >128 bytes is the required
jump.

.c

ity
st

For Forward jump: Assembler doesnt know jump quantum in pass 1. Assembler reserves 3
bytes for the forward jump instruction. If jump distance turns out to be >128 bytes, the instruction
is coded as E9 r16 (E9H = Long jump code). If jump distance becomes <=128 bytes, the
instruction is coded as EB r8 followed by code for NOP (E8H = Short jump code).

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

4.2.5 SHORT Assembler Directive

JMP SHORT

SAME

gr
ou
p.
c

Programmer should ensure that


the Jump distance is <=127 bytes

om

Assembler generates only 2 byte Short Jump code for forward jump, if the SHORT assembler
directive is used.

SAME:

MOV CX, DX

Long Jump instruction

ud
en
ts

3-byte (E9 r16) instruction with Range: -32768 to +32767 bytes

Long Jump can cover entire 64K bytes of Code segment

ity
st

CS:0000H

CS:8000H

.c

:
JMP FRWD
:

Long Jump can handle it as jump


quantum is <=32767

:
FRWD = CS:FFFFH

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

Long Jump can handle it as jump


quantum is <=32767

BKWD= CS:0000H

:
:
JMP BKWD
:

4.2.6 Long Jump or Short Jump?


Can be treated as a
small (20H) Backward

CS:0000H

Branch!

gr
ou
p.
c

FRWD = CS:FFFFH

om

CS:8000H

ud
en
ts

CS:0010H JMP FRWD

Jump distance =FFE0H.


Too very long forward
jump.

FRWD = CS:FFF0H

ity
st

CS:FFFFH

CS:0000H

.c

Can be treated as a small


(20H)

:
:

Forward Branch!

BKWD = CS:0010H

Jump distance =FFE0H.


Too very long

:
backward jump
:

CS:FFF0H

JMP BKWD
:

CS:FFFFH

Dept of CSE, SJBIT

Page 106

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MICROPROCESSORS

10CS45

4.2.7 Intra segment indirect Jump


It is also called Near Indirect Jump. It is not commonly used.

Ex.1: JMP DX

gr
ou
p.
c

If DX = 1234H, branches to CS:1234H. 1234H is not signed relative displacement.

om

Instruction length: 2 or more bytes Range: complete segment

Ex. 2: JMP wordptr 2000H[BX]

DS:3234H 5678H

Branches to CS:5678H

DS:3236H AB22H

ud
en
ts

If BX contents is 1234H

Far Jump instruction

4.2.8 Far Jump

Indirect Jump (uncommon)

5 bytes, opcode EA, 2 byte offset,

2 or more bytes,

2 byte segment value

starting with opcode FFH

.c

ity
st

Direct Jump (common)

Range: anywhere in memory

Range: anywhere in memory

As stated earlier, three Near Jump and two Far Jump instructions have the same mnemonic
JMP but different opcodes.

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

4.2.9 Inter segment Direct Jump instruction

It is a 5 byte instruction. 1 byte opcode (EAH), 2 byte offset value, 2 byte segment value

4.2.10 Inter segment Indirect Jump instruction

gr
ou
p.
c

Ex. JMP Far ptr LOC

om

Also called Far Direct Jump. It is the common inter segment jump scheme

Also called Far Indirect Jump. It is not commonly used. Instruction length depends on the way
jump location is specified. It can be a minimum of 2 bytes.

ud
en
ts

Ex. JMP DWORD PTR 2000H[BX]

If BX contents is 1234H branch takes place to location ABCDH:5678H. It is a 4-byte instruction.

DS:3234H 5678H

ity
st

DS:3236H ABCDH

.c

Iteration Instructions

Iteration instructions provide a convenient way to implement loops in a program

Iteration instructions

LOOP

LOOPZ or LOOPE

LOOPNZ or LOOPNE

Dept of CSE, SJBIT

JCXZ

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MICROPROCESSORS

10CS45

Let us say, we want to repeat a set of instructions 5 times.

For 8086processor

gr
ou
p.
c

For 8085 processor

MVI C, 05H

MOV CX, 0005H

AGAIN: MOV B, D

AGAIN: MOV BX, DX

LOOP AGAIN

ud
en
ts

DCR C
JNZ AGAIN

om

4.3 LOOP Instruction

General format: LOOP r8; r8 is 8-bit signed value. It is a 2 byte instruction.


Used for backward jump only. Maximum distance for backward jump is only 128 bytes.
DEC CX

ity
st

LOOP AGAIN is almost same as:

JNZ AGAIN

LOOP instruction does not affect any flags.

.c

If CX value before entering the iterative loop is:

0005, then the loop is executed 5 times till CX becomes 0

0001, then the loop is executed 1 time till CX becomes 0

0000, then the loop is executed FFFF+1 = 10000H times!

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

4.3.1 JCXZ Instruction

Ex.

MOV CX, SI
JCXZ SKIP
AGAIN: MOV BX, DX
:

ud
en
ts

gr
ou
p.
c

om

Jump if CX is Zero is useful for terminating the loop immediately if CX value is 0000H It is a 2
byte instruction. It is used for forward jump only. Maximum distance for forward jump is only
127 bytes.

LOOP AGAIN

; Executed after JCXZ if CX = 0

.c

ity
st

SKIP: ADD SI, DI

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

4.3.2 LOOPZ instruction

MOV CX, 04H

gr
ou
p.
c

Ex.

om

LOOP while Zero is a 2-byte instruction. It is used for backward jump only. Backward jump
takes place if after decrement of CX it is still not zero AND Z flag = 1. LOOPE is same as
LOOPZ. LOOPE is abbreviation for LOOP while Equal. LOOPE is normally used after a
compare instruction.

BACK: SUB BX, AX


MOV BX, DX
:
:

LOOPZ BACK

4.3.3 CALL Instructions

ud
en
ts

ADD SI, DI

; if SI+DI = 0 and CX not equal to 0, branch to BACK

ity
st

CALL instruction is used to branch to a subroutine. There are no conditional Call instructions in
8086.

.c

CALL instructions

Far CALL or Inter segment CALL

Near CALL or Intra segment CALL

Near Direct CALL

Near Indirect CALL

Far Direct CALL

Far Indirect CALL

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MICROPROCESSORS

10CS45

4.3.4 Near Direct CALL instruction

Covers the entire Code segment. It is the most common CALL instruction.

Ex. CALL Compute

ud
en
ts

4.3.5 Near Indirect CALL instruction

gr
ou
p.
c

It is functionally same as the combination of the instructions PUSH IP and ADD IP, r16.

om

It is a 3-byte instruction. It has the format CALL r16 and has the range + 32K bytes.

Not commonly used. Instruction length depends on the way the called location is specified.

Ex.1: CALL AX

; If (AX) = 1234H, branches to procedure at CS: 1234H.

ity
st

1234H is not relative displacement.

Ex. 2: CALL word ptr 2000H[BX]

.c

If BX contents is1234H Branches to subroutine at CS:5678H

DS:3236H ABCDH

Far Direct CALL instruction

DS:3234H 5678H

It is a 5-byte instruction. 1-byte opcode, 2-byte offset, 2-byte segment value.


Far direct CALL is functionally same as:
PUSH CS
Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

PUSH IP
IP = 2-byte offset value provided in CALL

om

CS = 2-byte segment value provided in CALL

4.3.6 Far Indirect CALL instruction

gr
ou
p.
c

Ex. CALL far ptr Compute

Not commonly used. Instruction length depends on the way the called location is specified.
Ex. CALL dword ptr 2000H[BX]

ud
en
ts

If BX contents is1234H bBranches to subroutine at ABCDH:5678H

DS:3234H

5678H

DS:3236H

ABCDH

ity
st

4.3.7 Conditional CALL?

What if we want to branch to subroutine COMPUTE only if Cy flag = 0?

.c

Solution:

CALL COMPUTE

; execute only if Cy = 0

NEXT:

JC NEXT

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MICROPROCESSORS

10CS45

4.3.8 RETURN instructions


RET is abbreviation for Return from subroutine

RET

RET d16

4.3.9 Near RET instruction

Far RET or Inter segment RET

gr
ou
p.
c

Near RET or Intra segment RET

om

RET instructions

RET

RET d16

Ex:
Compute

ud
en
ts

It is 1-byte instruction. Opcode is C3H. It is functionally same as : POP IP

Proc Near

; indicates it is a NEAR procedure

:
:

ity
st

RET

Compute

ENDP

; end of procedure Compute

.c

In fact, default procedure type is NEAR

Dept of CSE, SJBIT

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MICROPROCESSORS

10CS45

4.3.10 Near RET d16 instruction


It is a 3-byte instruction. 1-byte opcode (C2H) and 2-byte data. It is functionally same as:
POP IP

om

SP = SP + d16

gr
ou
p.
c

Ex. RET 0004H

RET d16 is useful for flushing out the parameters that were passed to the subroutine using the
stack

Main Program
:
:

ud
en
ts

4.3.11 Use of RET d16 instruction

SP after CALL Compute

PUSH Var1
PUSH Var2

ity
st

CALL Compute

IP
Var2
Var1

SP before PUSH Var1

.c

COMPUTE

Subroutine
PROC
:

IP
SP if RET is executed

Var2
Var1

RET 0004H
COMPUTE

Near

SP if RET 0004H is executed

ENDP

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MICROPROCESSORS

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It is 1-byte instruction. Opcode is CBH. It is functionally same as: POP IP + POP CS

SINX

Proc Far
:
:
RET

Default procedure type is NEAR

; end of procedure SINX

ud
en
ts

SINX ENDP

; indicates it is a FAR procedure

gr
ou
p.
c

Ex.

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Far RET instruction

4.3.12 Far RET d16 instruction

It is a 3-byte instruction. 1-byte opcode (CAH) and 2-byte data.

Ex. RET 0006H

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st

It is functionally same as: POP IP + POP CS + ADD SP, d16

.c

RET d16 is useful for flushing out the parameters that were passed to the subroutine using the
stack.

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Unit -5

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5.1 Mixing Assembly and C

Often it is a good idea to link assembly language programs or routines with high-level programs

gr
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c

which may contain resources unavailable to you through direct assembly programming--such as

using C's built in graphics library functions or string-processing functions. Conversely, it is often
necessary to include short assembly routines in a compiled high-level program to take advantage
of the speed of machine language.

All high-level languages have specific calling conventions which allow one language to
communicate to the other; i.e., to send variables, values, etc. The assembly-language program

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that is written in conjunction with the high-level language must also reflect these conventions if
the two are to be successfully integrated. Usually high-level languages pass parameters to
subroutines by utilizing the stack. This is also the case for C.
5.2 Using Assembly Procedures in C Functions

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5.2 .1 Procedure Setup

In order to ensure that the assembly language procedure and the C program will combine and be
compatible, the following steps should be followed:
Declare the procedure label global by using the GLOBAL directive. In addition, also

.c

declare global any data that will be used.


Use the EXTERN directive to declare global data and procedures as external. It is best to

place the EXTERN statement outside the segment definitions and to place near data inside
the data segment.

Follow the C naming conventions--i.e., precede all names (both procedures and data)
with underscores.

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5.2 .2 Stack Setup


Whenever entering a procedure, it is necessary to set up a stack frame on which to pass

push

ebp

mov

ebp, esp

gr
ou
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c

accomplish the stack setup, include the following code in the procedure:

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parameters. Of course, if the procedure doesn't use the stack, then it is not necessary. To

EBP allows us to use this pointer as an index into the stack, and should not be altered throughout
the procedure unless caution is taken. Each parameter passed to the procedure can now be
accessed as an offset from EBP. This is commonly known as a "standard stack frame."

ud
en
ts

5.2 .3 Preserving Registers

It is necessary that the procedure preserve the contents of the registers ESI, EDI, EBP, and all
segment registers. If these registers are corrupted, it is possible that the computer will produce
errors when returning to the calling C program.

5.2 .4 Passing Parameters in C to the Procedure

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C passes arguments to procedures on the stack. For example, consider the following statements
from a C main program:
|

.c

extern int Sum();

int a1, a2, x;


|

x = Sum(a1, a2);
When C executes the function call to Sum, it pushes the input arguments onto the stack in
reverse order, then executes a call to Sum. Upon entering Sum, the stack would contain the
following:
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MICROPROCESSORS

Since a1 and a2 are declared as int variables, each takes up one word on the stack. The above

method of passing input arguments is called passing by value. The code for Sum, which outputs

_Sum

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c

the sum of the input arguments via register EAX, might look like the following:

ebp

mov

ebp, esp

mov

eax, [ebp+8]

; grab the first argument

mov

ecx, [ebp+12]

; grab the second argument

add

eax, ecx

; sum the arguments

pop

ebp

ret

; create stack frame

ud
en
ts

push

; restore the base pointer

It is interesting to note several things. First, the assembly code returns the value of the result to
the C program through EAX implicitly. Second, a simple RET statement is all that is necessary

ity
st

when returning from the procedure. This is due to the fact that C takes care of removing the
passed parameters from the stack.

Unfortunately, passing by value has the drawback that we can only return one output value.

.c

What if Sum must output several values, or if Sum must modify one of the input variables? To
accomplish this, we must pass arguments by reference. In this method of argument transmission,

the addresses of the arguments are passed, not their values. The address may be just an offset, or

both an offset and a segment. For example, suppose Sum wishes to modify a2 directly--perhaps

storing the result in a2 such that a2 = a1 + a2. The following function call from C could be used:

Sum(a1, &a2);
The first argument is still passed by value (i.e., only its value is placed on the stack), but the
second argument is passed by reference (its address is placed on the stack). The "&" prefix
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MICROPROCESSORS

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means "address of." We say that &a2 is a "pointer" to the variable a2. Using the above statement,

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the stack would contain the following upon entering Sum:

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c

Note that the address of a2 is pushed on the stack, not its value. With this information, Sum can

access the variable a2 directly. (Hint: use an index register to hold the offset, then use a memory
access to access the variable).
5.2 .5 Returning a Value from the Procedure

Assembly can return values to the C calling program using only the EAX register. If the returned

ud
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value is only four bytes or less, the result is returned in register EAX. If the item is larger than
four bytes, a pointer is returned in EAX which points to the item. Here is a short table of the C
variable types and how they are returned by the assembly code:
Register

char

AL

ity
st

Data Type

AX

short

int, long, pointer

.c

(*)

EAX

5.2 .6 Allocating Local Data Space on the Stack

Temporary storage space for local variables or data can be created by decreasing the contents of

ESP just after setting up a stack frame at the beginning of the procedure. It is important to restore
the stack space at the end of the procedure. The following code fragment illustrates the basic
idea:
push

ebp

; Save caller's stack frame

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mov

ebp, esp

; Establish new stack frame

sub

esp, 4

; Allocate local data space of


;

esi

push

edi

; Save critical registers

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push

4 bytes

...
edi

; Restore critical registers

pop

esi

mov

esp, ebp

; Restore the stack

pop

ebp

; Restore the frame

ret

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c

pop

; Return to caller

5.2 .7 Using C Functions in Assembly Procedures

ud
en
ts

In most cases, calling C library routines or functions from an assembly program is more complex
than calling assembly programs from C. An example of how to call the printf library function
from within an assembly program is shown next, followed by comments on how it actually
works.
_main

extern

_printf

ity
st

global

db

text

.c

section .data

"%s", 0

strformat db

"291 is the best!", 10, 0

section .code

_main
push

dword text

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push

dword strformat

call

_printf

add

esp, 8

om

ret
Notice that the procedure is declared global, and its name must be _main, which is the starting

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point of all C code.

Since C pushes its arguments onto the stack in reverse order, the offset of the string is pushed
first, followed by the offset of the format string. The C function can then be called, but care must
be taken to restore the stack once it has completed.

When linking the assembly code, include the standard C library (or the library containing the
functions you use) in the link. For a more detailed (and perhaps more accurate) description of the

.c

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st

ud
en
ts

procedures involved in calling C functions, refer to another text on the subject.

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Unit-6

40
39
38
37

10
11
12
13
14

8086

15
16

36
35
34
33
32
31
30
29
28
27
26

Vcc
AD15
A16/S3
A17/S4
A18/S5
A19/S6
BHE/S7
MN/MX
RD
RG/GT0 (HOLD)
RQ/GT1 (HLDA)
LOCK (WR)
S2 (M/I0)
S1 (DT/R)
S0 (DEN)
QS0 (ALE)
QS1 (INTA)
TEST
READY
RESET

gr
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c

1
2
3
4
5
6
7
8
9

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ts

GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND

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6.1 Pin Configuration

17
18
19
20

25
24
23
22
21

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Fig. .1 Pin Configuration

The following pin function descriptions are for the microprocessor 8086 in either minimum or
maximum mode. The 8086 pins signals are TTL compatible.

.c

6.1 AD0 - AD15 (I/O): Address Data Bus


These lines constitute the time multiplexed memory/IO address during the first clock cycle

(T1) and data during T2, T3 and T4 clock cycles. A0 is analogous to BHE for the lower byte of

the data bus, pins D0-D7. A0 bit is Low during T1 state when a byte is to be transferred on the
lower portion of the bus in memory or I/O operations. 8-bit oriented devices tied to the lower
half would normally use A0 to condition chip select functions. These lines are active high and

float to tri-state during interrupt acknowledge and local bus "Hold acknowledge". Fig. 2 shows
the timing of AD0 AD15 lines to access data and address.
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MICROPROCESSORS

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AD0 - AD15

T1

Address

T2

T3

T4

Data

Fig. .2

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c

6.1.1 A19/S6, A18/S5, A17/S4, A16/S3 (0): Address/Status

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T4

During T1 state these lines are the four most significant address lines for memory
operations. During I/O operations these lines are low. During memory and I/O operations, status
information is available on these lines during T2, T3, and T4 states.

S5: The status of the interrupt enable flag bit is updated at the beginning of each cycle.

ud
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The status of the flag is indicated through this bus.

S6: When Low, it indicates that 8086 is in control of the bus. During a "Hold
acknowledge" clock period, the 8086 tri-states the S6 pin and thus allows another bus master to
take control of the status bus.

S3 & S4: Lines are decoded as follows:

A16/S3

.c

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A17/S4

Function

Extra segment access

Stack segment access

Code segment access

Data segment access

Table 1

After the first clock cycle of an instruction execution, the A17/S4 and A16/S3 pins specify which

segment register generates the segment portion of the 8086 address. Thus by decoding these lines and
using the decoder outputs as chip selects for memory chips, up to 4 Megabytes (one Mega per segment)
of memory can be accesses. This feature also provides a degree of protection by preventing write

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MICROPROCESSORS

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operations to one segment from erroneously overlapping into another segment and destroying information
in that segment.

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6.1.2 BHE /S7 (O): Bus High Enable/Status

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During T1 state the BHE should be used to enable data onto the most significant half of the data
bus, pins D15 - D8. Eight-bit oriented devices tied to the upper half of the bus would normally use BHE
to control chip select functions. BHE is Low during T1 state of read, write and interrupt acknowledge
cycles when a byte is to be transferred on the high portion of the bus.

The S7 status information is available during T2, T3 and T4 states. The signal is active Low and

cycle.

6.1.3 RD (O): READ

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floats to 3-state during "hold" state. This pin is Low during T1 state for the first interrupt acknowledge

The Read strobe indicates that the processor is performing a memory or I/O read cycle. This signal is
active low during T2 and T3 states and the Tw states of any read cycle.

TEST (I)

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This signal floats to tri-state in "hold acknowledge cycle".

TEST pin is examined by the "WAIT" instruction. If the TEST pin is Low, execution

.c

continues. Otherwise the processor waits in an "idle" state. This input is

synchronized internally during each clock cycle on the leading edge of CLK.

6.1 .4 INTR (I): Interrupt Request


It is a level triggered input which is sampled during the last clock cycle of each instruction to

determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored
to via an interrupt vector look up table located in system memory. It can be internally masked by software
resetting the interrupt enable bit
INTR is internally synchronized. This signal is active HIGH.

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6.1 .5 NMI (I): Non-Muskable Interrupt


An edge triggered input, causes a type-2 interrupt. A subroutine is vectored to via the interrupt
vector look up table located in system memory. NMI is not maskable internally by software. A

interrupt at the end of the current instruction. This input is internally synchronized.

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6.1 .6 Reset (I)

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transition from a LOW to HIGH on this pin initiates the

Reset causes the processor to immediately terminate its present activity. To be recognised, the
signal must be active high for at least four clock cycles, except after power-on which requires a 50 Micro
Sec. pulse. It causes the 8086 to initialize registers DS, SS, ES, IP and flags to all zeros. It also initializes
CS to FFFF H. Upon removal of the RESET signal from the RESET pin, the 8086 will fetch its next
instruction from the 20 bit physical address FFFF0H. The reset signal to 8086 can be generated by the
8284. (Clock generation chip). To guarantee reset from power-up, the reset input must remain below 1.5

ud
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volts for 50 Micro sec. after Vcc has reached the minimum supply voltage of 4.5V. The RES input of the
8284 can be driven by a simple RC circuit as shown in fig.3.
X1
X2

F/C

R
+5V

CLK

CLK

8284

RES

8086 p

RESET

RESET

.c

ity
st

Normal
Reset Key

SYSTEM RESET

Fig. .3

The value of R and C can be selected as follows:

Vc (t) = V (1 - e -t /RC)
V = 4.5 volts,

t = 50 Micro sec.
Vc = 1.05V and RC = 188 Micro sec.

C = 0.1 Micro F;

R = 1.88 K ohms.

CPU component
Flags

Contents
Cleared

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10CS45

0000H

CS register

FFFFH

DS register

0000H

SS register

0000H

ES register

0000H

Queue

Empty

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Instruction Pointer

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MICROPROCESSORS

Table .2 System Registers after Reset

8086/88 RESET line provide an orderly way to start an executing system. When the processor detects the
positive-going edge of a pulse on RESET, it terminates all activities until the signal goes low, at which
time it initializes the system as shown in

6.1 .7 Ready (I)

ud
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ts

table .2.

Ready is the acknowledgement from the addressed memory or I/O device that it will complete the
data transfer. The READY signal from memory or I/O is synchronized by the 8284 clock generator to
form READY. This signal is active HIGH. The 8086 READY input is not synchronized. Correct

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operation is not guaranteed if the setup and hold times are not met.

6.1 .8 CLK (I): Clock

.c

Clock provides the basic timing for the processor and bus controller. It is asymmetric with 33%
duty cycle to provide optimized internal timing. Minimum frequency of 2 MHz is required, since the

design of 8086 processors incorporates dynamic cells. The maximum clock frequencies of the 8086-4,

8086 and 8086-2 are

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X1
X2

CLK

F/C

READY

8086 p

Csync
RESET
RDY1

AEN2

PCLK
SYSTEM RESET

RDY2
OSC

Fig..4

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Vcc

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AEN1

4MHz, 5MHz and 8MHz respectively. Since the 8086 does not have on-chip clock generation circuitry,
and 8284 clock generator chip must be connected to the 8086 clock pin. The crystal connected to 8284
must have a frequency 3 times the 8086 internal frequency. The 8284 clock generation chip is used to

CLK. It is as shown in fig..4

ud
en
ts

generate READY, RESET and

6.1 .9 MN/ MX (I): Maximum / Minimum

This pin indicates what mode the processor is to operate in. In minimum mode, the 8086 itself
generates all bus control signals. In maximum mode the three status

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signals are to be decoded to generate all the bus control signals.

6.1 .10 Minimum Mode Pins

The following 8 pins function descriptions are for the 8086 in minimum mode; MN/ MX = 1.

.c

The corresponding 8 pins function descriptions for maximum mode is


explained later.

6.1 .11 M/ IO (O): Status line

This pin is used to distinguish a memory access or an I/O accesses. When this pin is Low, it

accesses I/O and when high it access memory. M / IO becomes valid in the T4 state preceding a bus
cycle and remains valid until the final T4 of the cycle. M/ IO
floats to 3 - state OFF during local bus "hold acknowledge".

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6.1 .12 WR (O): Write


Indicates that the processor is performing a write memory or write IO cycle, depending on the
state of the M / IO signal. WR is active for T2, T3 and Tw of any write cycle. It is active LOW,

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and floats to 3-state OFF during local bus "hold

6.1 .13 INTA (O): Interrupt Acknowledge

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acknowledge ".

It is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2,
T3, and T4 of each interrupt acknowledge cycle.

6.1 .14 ALE (O): Address Latch Enable

ALE is provided by the processor to latch the address into the 8282/8283 address

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ts

latch. It is an active high pulse during T1 of any bus cycle. ALE signal is never floated.

6.1 .15 DT/ R (O): DATA Transmit/Receive

In minimum mode, 8286/8287 transceiver is used for the data bus. DT/ R is used to control the
direction of data flow through the transceiver. This signal floats to tri-state off during local bus "hold
acknowledge".

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6.1 .16 DEN (O): Data Enable

It is provided as an output enable for the 8286/8287 in a minimum system which uses the
transceiver. DEN is active LOW during each memory and IO access. It will be low beginning with T2

.c

until the middle of T4, while for a write cycle, it is active from the beginning of T2 until the middle of T4.

It floats to tri-state off during local bus "hold acknowledge".

6.1 .17 HOLD & HLDA (I/O): Hold and Hold Acknowledge
Hold indicates that another master is requesting a local bus "HOLD". To be acknowledged,

HOLD must be active HIGH. The processor receiving the "HOLD " request will issue HLDA (HIGH) as
an acknowledgement in the middle of the T1-clock cycle. Simultaneous with the issue of HLDA, the
processor will float the local bus and control lines. After "HOLD" is detected as being Low, the processor
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MICROPROCESSORS

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will lower the HLDA and when the processor needs to run another cycle, it will again drive the local bus
and control lines.

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6.2 Maximum Mode

The following pins function descriptions are for the 8086/8088 systems in maximum mode (i.e..

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MN/ MX = 0). Only the pins which are unique to maximum mode are described below.
.
6.2 .1 S2, S1, S0 (O): Status Pins

These pins are active during T4, T1 and T2 states and is returned to passive state (1,1,1 during T3
or Tw (when ready is inactive). These are used by the 8288 bus controller to generate all memory and I/O
operation) access control signals. Any change by S2, S1, S0 during T4 is used to indicate the beginning

S1

S0

Characteristics

Interrupt acknowledge

Read I/O port

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st

S2

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ts

of a bus cycle. These status lines are encoded as shown in table 3.

Write I/O port

Halt

Code access

Read memory

Write memory

Passive State

.c

Table 3

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6.2 .2 QS0, QS1 (O): Queue Status


Queue Status is valid during the clock cycle after which the queue operation is performed. QS0,
QS1 provide status to allow external tracking of the internal 8086

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instruction queue. The condition of queue status is shown in table 4.


Queue status allows external devices like In-circuit Emulators or special instruction set extension coprocessors to track the CPU instruction execution. Since instructions are executed from the 8086 internal

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queue, the queue status is presented each


CPU clock cycle and is not related to the bus cycle activity. This mechanism allows

(1) A processor to detect execution of a ESCAPE instruction which directs the co-processor to
perform a specific task and

(2) An in-circuit Emulator to trap execution of a specific memory location.


QS1

Characteristics
No operation

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ts

QS1

First byte of opcode from queue


Empty the queue

Subsequent byte from queue

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Table 4

6.2 .2 LOCK (O)

.c

It indicates to another system bus master, not to gain control of the system bus while LOCK is
active Low. The LOCK signal is activated by the "LOCK" prefix instruction and remains active until the

completion of the instruction. This signal is active

Low and floats to tri-state OFF during 'hold acknowledge".

Example:
LOCK XCHG reg., Memory

; Register is any register and memory GT0


; is the address of the semaphore.

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6.2 .3 RQ / GT0 and RQ / GT1 (I/O): Request/Grant


These pins are used by other processors in a multi processor organization. Local bus masters of
other processors force the processor to release the local bus at the end of the processors current bus cycle.

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Each pin is bi-directional and has an internal pull up


resistors. Hence they may be left un-connected.

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6. 2 . 4 8086 Memory Addressing

The 8086 memory address space can be viewed as a sequence of one million bytes in which any
byte may contain an 8-bit data element and any two consecutive bytes may contain a 16-bit data element.
There is no constraint on byte or word address boundaries. The address space is physically connected to a
16-bit data bus by dividing the address space into two 8-bit banks of up to 512K bytes each.

One bank is connected to the lower half of the 16-bit data bus (D0 D7) and contains even address

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bytes. i.e., when A0 bit is low, the bank is selected. The other bank is connected to the upper half of the
data bus (D8 - D15) and contains odd address bytes. i.e., when A0 is high and BHE (Bus High Enable)
is low, the odd bank is selected. A specific byte within each bank is selected by address lines A1-A19.

Lower
Address
Bank
(512K x 8)
EVEN

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st

Higher
Address
Bank
(512K x 8)
ODD

A1-A19
Address Bus

BHE

A0

D0-D7

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D8-D15

Fig. 5

Data Bus (D0 - D15)

Data can be accessed from the memory in four different ways. They are:
8 - bit data from Lower (Even) address Bank.
8 - bit data from Higher (Odd) address Bank.
16 - bit data starting from Even Address.
16 - bit data starting from Odd Address.

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6.2 .5 8-bit data from Even address Bank


Even Bank

Odd Bank

x + 3

x + 2

x + 5

x + 4

BHE = 1

D0-D15

A0 = 0
D0-D7

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D8-D15

A1-A19

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x + 1

Fig. 6 8-bit Data Access from Even Address

To access memory bytes from Even address, information is transferred over the lower half of the
data bus (D0 - D7). The A0 is output LOW and BHE is output HIGH enabling only the even address

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ts

bank. It is illustrated in fig. 6.

Example: Consider loading a byte of data into CH register (higher order 8-bits of CX register)
from the memory location with an even address. The data will be accessed from the even bank via the (D0
- D7) DATA BUS. Although this data is transferred into the 8086 over the lower 8-bit lines, the 8086
automatically redirects the data to the higher 8-bits of its internal 16-bit data path and hence to the CH-

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register. This capability allows bytes input - output transfer via the AL register to access

I/O device

connected to either

the upper half of the data bus or the lower half of the 16-bit data bus.

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6.2 .6 8-bit Data from Odd Address Bank

To access memory byte from an odd address information, is transferred over the higher half of the

data bus (D8 - D15). The BHE output low enables the upper memory bank. A0 is output high to disable

the lower memory bank. It is illustrated in fig. 7

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Even Bank

Odd Bank

BHE =0

A0 = 1

A1-A19
D0-D7
D8-D15

Fig. 7
6.2 .6 16-bit Data Access starting from Even - Address

Even Bank

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Odd Bank

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D0-D15

x
x+2

x+1
x+3

A1-A19

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x
x + 2

x + 1
x + 3

D8-D15

A0 = 0

BHE =0

D0-D7

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D0-D15

Fig. 8

16-bit data from an even address is accessed in a single bus cycle. Address lines A1 - A19 select
the appropriate byte within each bank. A0 low and BHE low enables both banks simultaneously. This is

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illustrated in fig. 8.

A 16-bits word located at an odd address (two consecutive bytes with the least significant

6.2 .7 16-bit Data Access starting from Odd Address

byte at an odd byte address) is accessed using two bus cycles. During the first bus cycle the lower byte

(with the odd address 0005 as shown in fig. 9 (a)) is accessed.

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Odd Bank

Even Bank

0004
0006
0008

0005
0007
0009

0004
0006
0008

0005
0007
0009

A1-A19

Even Bank

A1-A19
A1-A9

A1-A9
D0-D7
D8-D15

(a) First Access from Odd Address

D0-D7

(b) Next Access from Even Address

Fig. 9

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D8-D15

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Odd Bank

During the second bus cycle, the upper byte (with the even address 0006H as in fig.

9 (b)) is

accessed. During the first bus cycle, A1 - A19 address bus specifies the address and A0 as 1 and BHE is
low. Therefore the even memory bank is disabled and odd memory bank is enabled. During the second
bus cycle, the address is incremented. Therefore A0 is zero and BHE is made high. The even memory

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bank is enabled and the odd memory bank is disabled.

6.2 .8 8086 Basic System Concepts

8086 can be used either in a minimum mode system or a maximum mode system. The fig. 10
and fig. 11 shows minimum and maximum modes with groups of ICs to generate address bus, data bus

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and control bus signals. Using these buses, the CPU can be connected to ROM, RAM, PORTS and other
devices to form a complete system.

6.2 .9 BASIC 8086 Minimum mode System

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8282 I/O ports are used to latch the addresses from the 8086 Microprocessor Data/Address bus.
By using three 8282, A0-A15, BHE , A16-A19 lines are latched during T1 state. OE (Output Enable)

input of the 8288 I/O ports are grounded; the bus will therefore, never be floated. ALE signal from 8286

is used to strobe the addresses into the 8282 I/O latches.

Since the Data Bus is bi-directional, 8286 bi-directional bus transceivers are used, in

order to create a separate Data Bus from the 8086 Address/data Bus. The DT/ R and DEN
outputs from 8086 are used for 8286 "T" signal and OE inputs respectively.

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6.2 .9 Maximum Mode Configuration


When MN/ MX pin is strapped to GND, the 8086 treats pin 24 through 31 to be in maximum
mode. An 8288 bus controller interprets status information coded into S0, S1 and S2 to generate bus

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timing and control signals compatible. DEN, DT/ R and ALE control outputs, are now generated by the

8288 bus controller. The DEN from 8288 is inverted and given to 8286 transceiver to enable the output.
The output enable of 8282 latch is grounded. As in minimum mode the address-data lines are latched

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through 8282 latch. The ALE signal from the 8288 bus controller latches the address during the T1 state

of the microprocessor. The DEN signal is used to enable the transceiver either to transmit or receive data
from I/O devices and memory. The DT/ R signal is used to transmit or receive the data as the need may
be.

PCLK

+5V

AEN2
AEN1
F/C

Wait-State
Generator

M/IO
INTA
RD
WR

Control
Bus

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RES

CLK
READY
RESET

Clock
generator

MN/MX

ALE

+5V

STB

A0 - A19

OE

AD0-AD15
A16-A19

Address Bus
8282
Latch

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BHE

DT/R
DEN

BHE

D0 - D15
8286

16

T
OE

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Fig. 10 8086 Minimum Mode System

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+5V
MN/MX
S0
S1
S2

CLK
READY

Gnd

CLK

MRDC

S0

MWTC

S1

AMWC

S2

RESET

IORC

Wait-State
Generator

DEN

IOW C

DT/R

AIOWC

ALE

INTA

STB

A0 - A19

OE

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Address Bus

AD0-AD15
A16-A19

8282
Latch

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RES

Clock
generator

OE

BHE

DATA

8286
Transceiver

Fig. 11 8086 Maximum Mode Configuration

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6.2 .10 5 Bus Read Machine Cycle

Fig- 12 shows the timing diagram of 8086 read machine cycle with WAIT state. The clock
(CLK) signal is obtained from the clock-generator 8284. Each cycle of the clock is referred to as a state.
Minimum number of states to access a data is four. They are T1, T2, T3, and T4 states.
During T1 state of a read machine cycle an 8086 first asserts the M/ IO signal. It will assert this

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signal high if it is going to read from memory during memory read cycle and it will assert M/ IO low if it
is going to do a read from an Input port during its read cycle. The timing diagram in fig. 12 shows two
lines for the M/ IO signal, because the signal may be going LOW or going HIGH for a read cycle. The

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point where the two lines cross indicate the time at which the signal becomes valid for this machine cycle.

After asserting M/ IO , the 8086 sends out a high on the address latch enable signal, ALE. The
microprocessor sends out on AD0-AD15, A16 through A19 and BHE lines, the address of the memory

location that it wants to read. Since the latches are enabled by ALE being high, this address information

passes through the latches to their outputs. The 8086 then makes the ALE output low. This disables the
latches (8282) and holds the address information latched on the latch outputs. The address information
latched on the latch outputs can now be used to select the desired memory or port location.
In the timing diagram, the first point at which the two (AD0 AD15) cross represents the time at
which the 8086 has put a valid address on these lines. Two lines DO NOT indicate that all 16 lines are
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going high or going low at this point. The crossed lines indicate the time at which a valid address is on
the bus.

T2

T3

Twait

T4

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T1
CLK

AD0-AD15

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BHE

ALE

S2-S0

M/IO
RD

READY
DT/R

WR

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DEN

Fig. 12 Read Timing Diagram

Since the address information is now held on the latch, the 8086 does not need to send it out any
more. As shown in fig. 12 the 8086 floats the AD0 - AD15 lines so that they can be used to input data

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from memory or from a port. At about the same time the 8086 also remove the BHE and A16-A19
information from the upper lines and sends out some status information on these lines.
The 8086 is now ready to read data from the addressed memory locations or port. During T2-

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state the 8086 asserts its RD signal low. This signal is used to enable the addressed memory device or

port device.

At the end of T3 state the microprocessor makes the RD signal high and reads the data available

on the data bus, provided the READY input signal is high. It is the duty of the external circuit to see that

valid data is made available on the data bus.


If the READY input pin is not high at the sampled time in a machine cycle, the 8086 will insert

one or more WAIT states between T3 and T4 states in that machine cycle. An external hardware device
is set up to pulse READY low before the rising edge of the clock in T2 state. After the 8086 finishes T3
of the machine cycle, it enters a WAIT state.
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If the READY input is still low at the end of a WAIT state, then the 8086 will insert another
WAIT state. The 8086 will continue inserting WAIT states until the READY input is sampled high
again.

If the READY input is sampled high again during T3 or during the WAIT state, the

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microprocessor comes out of the WAIT state and will initiate T4 of the machine cycle.
The DEN signal is used to enable bi-directional buffers on the data bus. The data enable signal,

DEN, from the 8086 will enable the data buffer when it is asserted LOW. The data transmit / receive

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signal DT/ R from the 8086 is used to specify the direction in which the buffers are enabled. When DT/

R is asserted high, the buffers will, if enabled by DEN, transmit data from the 8086 to Memory or I/O
ports. When DT/ R is asserted low, the buffers, if enabled by DEN, will allow data to be received from
Memory or I/O ports of the 8086. DT/ R is asserted during T1 of the machine cycle. The DEN is

6.3 BUS Write Machine Cycle

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asserted after the 8086 finishes using the data bus to send the lower 16 address bits.

The 8086 write operation is very similar to the read cycle. During T1 of a write machine cycle the
8086 asserts M/ IO low if the write is going to a port and it asserts M/ IO high if the write is going to
memory. At about the same time the 8086 raises ALE

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high to enable the address latches. The 8086 then assert BHE and on the lines AD0 - AD19, it output the
address that it will be writing to. When writing to a port, line A16 - A19 will always be low, because the
8086 only sends out 16-bits port addresses. The 8086 brings ALE low again to latch the address on the
outputs of the latches. In addition to holding the address, the latches also function as buffers for the

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address lines. After the address information is latched, the 8086 remove the address information from

AD0 - AD15 and outputs the desired data on these lines.

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Fig 13 Write Timing Diagram

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If the READY input is sampled LOW by the 8086 before or during T2 of the machine cycle, the
8086 will insert a WAIT state after T3. If the READY input is sampled high before the end of the WAIT
state, the 8086 will go on with state T4 as soon as it completes the WAIT state. The 8086 will continue to
insect wait states for as long

as the READY is sampled low just before the end of each WAIT state.
6.3.1 Comparison of 8086 with the 8088 Microprocessor

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The 8088 CPU is an 8-bit processor designed around the 8086 internal structure. Most internal
functions of the 8088 are identical to the equivalent 8086 functions. The 8088 handles the external bus
the same way the 8086 does, one difference being hat the

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8088 handles only 8-bits at a time.

16-bit operands are fetched or written in two

+5V
Gnd(2)
NMI
INTR
Clk

SSo (High)
MN/MX
RD

AD0-AD7(8)

HOLD (RG/GT0)
HLDA (RQ/GT1)

A8-A15(8)

8088

A16/S3(4)
A19/S6
Test

WR (LOCK)
IO/M (S2)
DT/R(S1)

Ready
Reset

DEN (S0)
ALE (QS0)
INTA (QS1)

Fig . 14 Pin Configuration of 8088 Microprocessor


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consecutive bus cycles. To an assembly language programmer both processors will appear identical with
the exception of execution times. The internal register structure is identical and all instructions produce
the same end result. The pin configuration of 8088 is illustrated in fig. 14.

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The major differences between 8088 and 8086 are outlined below:
The queue length is 4 bytes in the 8088, where as the 8086 queue comprises of 6 bytes.

The 8088 BIU will fetch a new instruction to load into the queue as soon as it finds a byte

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hole (space available) in the queue. The 8086 waits until a 2 byte space is available.

The internal execution time of the instruction set is affected by the 8-bit interface. All 16-bit
fetches and writes from / to memory take an additional four clock cycles. The CPU is also
limited by the speed of instruction fetch. When the more sophisticated instructions of the 8088
are being used, the queue has time to fill and the execution proceeds as fast as the execution
unit

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will allow.

The hardware interface of the 8088 has some major differences as compared to the 8086. The pin
assignments are nearly identical, however, with the following functional changes.
A8-A15: These pins are only address outputs on the 8088. These address lines are latched
internally and remain valid throughout a bus cycle in a manner similar to the 8085 upper
address lines.

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SS0 provides the S0 status information in the minimum mode. This output occurs on pin 34
in minimum mode only. DT/ R , IO/ M and SS0 provide the complete bus status in

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minimum mode. This is shown in table 5

IO/M

DT/R

SSO

CHARACTERISTICS

Code Access

Read Memory

Write Memory

Passive

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Interrupt Acknowledge

Read I/O port

Write I/O port

Halt

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Table 5

BHE has no meaning on the 8088 and has been eliminated.

IO/ M has been inverted. i.e., (In 8086, this pin as IO /M)

ALE is delayed by one clock cycle in the minimum mode when entering
HALT to allow the status to be latched with ALE.

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Fig 15 illustrates the 8088 microprocessor system configuration. The Address-Data lines AD0AD7 are connected to the 74LS373 latch. The address from the multiplexed bus is latched into the
74LS373 when an ALE (Address latch enable) is active during T1 state of the microprocessor. The
address A0-A7 is available on the output of 74LS373 and can be used for memory (along with A16-A19),
and I/O devices. The address lines A8-A15 are not multiplexed with data lines or status lines, hence there
is no need to latch these address lines. The data bus is connected to the 74LS245 transceiver. The

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74LS245 is controlled by DT/ R and DEN to transmit and receive and Data respectively.
Since 74LS373 and 74LS245 are also buffered chips, it is not required to add buffers to these
chips. The address lines A8-A15 need to be buffered and hence the 74LS 244 buffer is used for these

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lines. The output of 74LS244 is always enabled.

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OE

A19/S6 - A16/S3

A19 - A16

74LS373
ALE

G
74LS
244

A15 - A8

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OE

8088

OE
G

AD0 - AD7

A0 - A7

74LS373

D0 - D7

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DEN

DT/R

74LS244

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Fig. 15

D/R

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UNIT -7

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Unit-8
8.1 Interrupt Driver I/O

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A disadvantage of conditional programmed I/O is that the microcomputer needs to check the status bit
(BUSY signal for the A/D converter) by waiting in a loop. This type of I/O transfer is dependent on the
speed of the external device. For a slow device, this waiting may slow down the capability of the
microprocessor to process other data. The interrupt I/O technique is efficient in this type of situation.

Interrupt I/O is a device-initiated I/O transfer. The external device is connected to a pin called the
interrupt (INT) pin on the processor chip. When the device needs an I/O transfer with the microcomputer,
it activates the interrupt pin of the processor chip. The microcomputer usually completes the current
instruction and saves at least the contents of the current program counter on the stack.

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8.1.1 Interrupt Types:

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The microcomputer then automatically loads an address into the program counter to branch to a
subroutine like program called the interrupt service routine. This program is written by the user. The
external device wants the microcomputer to execute this program to transfer data. The last instruction of
the service routine is a RETURN, which is typically the same instruction used at the end of a subroutine.
This instruction normally loads the address (saved in the stack before going to the service routine) in the
program counter. Then, the microcomputer continues executing the main program.

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There are typically three types of interrupts : external interrupts, traps or internal interrupts, and
software interrupts.

External interrupts are initiated through the microcomputers interrupt pins by external devices such as
A/D converters. A simple example of an external interrupt was given in the previous section.

External interrupts can further be divided into two types: maskable and nonmaskable. A maskable
interrupt is enabled or disabled by executing instructions such as EI or DI. If the microcomputers
interrupt is disabled, the microcomputer ignores the maskable interrupt. Some processors, such as the
Intel 8086, have an interrupt flag bit in the processor status register. When the interrupt is disabled, the
interrupt flat bit is 1, so no maskable interrupts are recognized by the processor. The interrupt flag bit
resets to zero when the interrupt is enabled.
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The nonmaskable interrupt has higher priority than the maskable interrupt. If both maskable and
nonmaskable interrupts are activated at the same time, the processor will service the nonmaskable
interrupt first.

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Internal interrupts, or traps, are activated internally by exceptional conditions such as overflow, division
by zero, or execution of an illegal op-code. Traps are handled the
same way as external interrupts. The user writes a service routine to take corrective measures and provide
an indication to inform the user that an exceptional condition has occurred.

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Many processors include software interrupts, or system calls. When one of these instructions is executed,
the processor is interrupted and serviced similarly to external or internal interrupts. Software interrupt
instructions are normally used to call the operating system. Software interrupt instructions allow the user
to switch from user to supervisor mode.

8.1.2 Interrupt Address Vector:

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The technique used to find the starting address of the service routine (commonly known as the interrupt
address vector) varies from one processor to another. With some processors, the manufacturers define the
fixed starting address for each interrupt. Other manufacturers use an indirect approach by defining fixed
locations where the interrupt address vector is stored.

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8.1.3 Saving the Microprocessor Registers:

When a processor is interrupted, it saves at least the program counter on the stack so tae processor can
return to the main program after executing the service routine. Some processors save only one or two
registers, such as the program counter and status register. Other processors save all microprocessor
registers before going to the service routine. The user should know the specific registers the processor
saves prior to executing the service routine. This will enable the user to use the appropriate return
instruction at the end of the service routine to restore the original conditions upon return to the main
program.

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8.1.4 Interrupt Priorities:

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A processor is typically provided with one or more interrupt pins on the chip. Therefore, a special
mechanism is necessary to handle interrupts from several devices that share on of these interrupt lines.
There are two ways of servicing multiple interrupts: polled and daisy chain techniques.

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Polled interrupts are handled by software and therefore are slower when compared with daisy chaining.
The processor responds to an interrupt by executing one general service routine for all devices. The
priorities of devices are determined by the order in which the routine polls each device. The processor
checks the status of each device in the general service routine, starting with the highest priority device to
service an interrupt. Once the processor determines the source of the interrupt, it branches to the service
routine for the device.

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In a daisy chain priority system, devices are connected in a daisy chain fashion to set up a priority system.
Suppose one or more devices interrupt the processor. In response, the
processor pushes at lease the PC and generates an interrupt acknowledge (INTA) signal to the highest
priority device. If this device has generated the interrupt, it will accept the INTA. Otherwise, it will pass
the INTA onto the next device until INTA is accepted. Once accepted, the device provides a means for
the processor to find an interrupt address vector by using external hardware. The daisy chain priority
scheme is based on mostly hardware and is therefore faster than the polled interrupt.

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8.1.5 Direct Memory Access (DMA)

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Direct Memory Access (DMA) is a technique that transfers data between a microcomputers memory and
I/O device without involving the microprocessor. DMA is widely used in transferring large blocks of
data between a peripheral device and the microcomputers memory. The DMA technique uses a DMA
controller chip for the data transfer operation. The main functions of a typical DMA controller are
summarized as follows:

The I/O devices request DMA operation via the DMA request line of the controller chip.

The controller chip activates the microprocessor HOLD pin, requesting the CPU to release
the bus.

The processor sends HLDA (hold acknowledge) back to the DMA controller, indicating that
the bus is disabled. The DMA controller places the current value of its internal registers,

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MICROPROCESSORS

10CS45

such as the address register and counter, on the system bus and sends a DMA acknowledge to
the peripheral device. The DMA controller completes the DMA transfer.

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There are three basic types of DMA: block transfer, cycle stealing, and interleaved DMA.

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For block transfer DMA, the DMA controller chip takes the bus from the microcomputer to transfer data
between the memory and I/O device. The microprocessor has no access to the bus until the transfer is
completed. During this time, the microprocessor can perform internal operations that do not need the bus.
This method is popular with microprocessors. Using this technique, blocks of data can be transferred.

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Data transfer between the microcomputer memory and an I/O device occurs on a word-by-word basis
with cycle stealing. Typically, the microprocessor clock is enabled by ANDing an INHIBIT signal with
the system clock. The system clock has the same frequency as the microprocessor clock. The DMA
controller controls the INHIBIT line. During normal operation, the INHIBIT line is HIGH, providing the
microprocessor clock. When DMA operation is desired, the controller makes the INHIBIT line LOW for
one clock cycle. The microprocessor is then stopped completely for the cycle. Data transfer between the
memory and I/O takes place during this cycle. This method is called cycle
stealing because the DMA controller takes away or steals a cycle without microprocessor recognition.
Data transfer takes place over a period of time.

.c

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With interleaved DMA, the DMA controller chip takes over the system bus when the microprocessor is
not using it. For example, the microprocessor does not use the bus while incrementing the program
counter or performing an ALU operation. The DMA controller chip identifies these cycles and allows
transfer of data between the memory and I/O device. Data transfer takes place over a period for time for
this method.

8.2 Types of data transfer

Simple I/O used when timings of I/O device is known

(Ex. Collect newspaper leisurely any time after 8 a.m.)

Status check I/O Data transfer done anytime after I/O device says it is ready

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(Ex. Check newspaper box and collect newspaper if it is in the box)

(Ex. Collect newspaper when the door bell rings indicating delivery of newspaper)

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In this section only Interrupt driven I/O is discussed.

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Interrupt driven I/O data transfer done immediately after I/O device interrupts

Interrupt driven I/O

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Interrupt types

Hardware interrupts
Ex. NMI and INTR pins

Software interrupts

Exceptions or Traps

Ex. INT n, INT 3, INTO


instructions

Ex. Divide by zero error,


Single step interrupt

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Interrupt type numbers

ITN

Interrupt type

Divide by 0 error

Out of bound(80286)

Single step interrupt

Invalid opcode

NMI

No Coprocessor

Break point interrupt

Double fault (during an

Overflow error

w
w

Interrupt type

ITN

.c

Every interrupt type in 8086 has an 8-bit Interrupt type number (ITN) as shown below.

instruction 2 interrupts)

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Reserved by Intel.

20-FF

13H for Disk services

Available for user.


INT 21H for DOS services.

Action when NMI is activated

1. Complete the instruction in progress


2. Push Flags on the stack
3. Reset IE flag (to ensure no further interrupts)

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NMI is positive edge triggered input

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5 -1F

10CS45

4. Reset T flag (so that interrupt service subroutine, ISS, is not executed in single step)

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5. PUSH CS
6. PUSH IP

7. IP loaded from word location 2 x 4 = 8 (2 is ITN)


8. CS loaded from next word location (0000AH)

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Processor makes a branch to the subroutine!

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8.2.1 Interrupt Vector table (IVT)

RAM locations 0 to 003FFH are used to store IVT. It contains 256 Interrupt
Vectors (IV) each of 4 bytes.

1234H

00002H

5678H

00004H

3344H

00000H

5678:1234H is IV number 0

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MICROPROCESSORS

5566H

003FCH

6677H

003FEH

7788H

5566:3344H is IV number 1
:

7788:6677H is IV number FF

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00006H

10CS45

1. Push Flags on the stack


2. Reset IE flag (to ensure no further interrupts)
3. Reset T flag (so that ISS is not executed in single step)
4. PUSH CS

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5. PUSH IP

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8.2.2 Execution of INT n (n=0 to FF)

6. IP loaded from word location n x 4 = say, W


7. CS loaded from next word location W+2

In INT n, which is a 2-byte instruction, n is the ITN. INT n has the opcode CDH

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Action when INT 3 is executed

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1. Push Flags on the stack

2. Reset IE flag (to ensure no further interrupts)

3. Reset T flag (so that ISS is not executed in single step)

4. PUSH CS

5. PUSH IP
6. IP loaded from word location 3 x 4 = 0000CH
7. CS loaded from next word location 0000EH

INT 3 is a 1-byte instruction with opcode of CCH

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8.2.3 What is divide by 0 error?

AH

After
00H

40H

AL

60H

BL

02H

This is an example for divide by 0 error. It only


means quotient is too large for the register!

2030H

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Before

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Ex. DIV BL

Action for divide by 0 error

1. Push Flags on the stack

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For divide by 0 error the ITN is 0

2. Reset IE flag (to ensure no further interrupts)

3. Reset T flag (so that ISS is not executed in single step)

5. PUSH IP

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4. PUSH CS

6. IP loaded from word location 0 x 4 = 00000H

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7. CS loaded from next word location 00002H

Processor makes a branch to the subroutine at location 5678:1234H if the contents of IVT is as
shown in the table above.

Action for Single step interrupt

For divide by 0 error the ITN is 1


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1. Push Flags on the stack


2. Reset IE flag (to ensure no further interrupts)

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3. Reset T flag (so that ISS is not executed in single step)


4. PUSH CS

6. IP loaded from word location1 x 4 = 00004H


7. CS loaded from next word location 00006H

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5. PUSH IP

Processor makes a branch to the subroutine at location 5566:3344H as per the IVT

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8.2.4 Action for INTO instruction

INTO is a 1-byte instruction. For interrupt on overflow the ITN is 4.

1. Do steps 2 to 7 only if Overflow flag is set

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2. Push Flags on the stack

3. Reset IE flag and T flag


4. PUSH CS

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5. PUSH IP

6. IP loaded from word location 4 x 4 = 00010H

7. CS loaded from next word location 00012H

INTO is equivalent to:

JNO Next
INT 4
Next: .

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Action when INTR is activated

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INTR is level triggered input.

1. Complete the instruction in progress

3. Push Flags on the stack. Reset IE and T flags


4. PUSH CS
5. PUSH IP
6. IP loaded from word location n x 4 = say, W

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7. CS loaded from next word location W+2

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2. Activate INTA o/p twice. In response 8086 receives ITN n instruction from an external device
like 8259 PIC

Processor makes a branch to the subroutine!

8.2.5 IRET (Return from Interrupt) instruction

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An ISS ends with the IRET instruction.

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IRET is same as POP IP + POP CS + POPF

SP before branch to ISS

SP after branch to ISS


IP
CS

FLAGS

Make sure ISS does not end with RET!

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8.2.6 Priority of 8086 Interrupts

NMI
INTR

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Divide by 0 error, INT n Highest priority

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If several interrupts occur during the execution of an instruction, in which order interrupts will be
serviced? There will be priorities as indicated below.

Single step interrupt Lowest priority

.c

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In reality NMI has highest priority! If NMI occurs during the servicing of INT n, processor
branches to NMI routine as IE flag has no effect on NMI.

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8.2.7 Intel 8255 PPI

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PPI is abbreviation for Programmable Peripheral Interface. It is an I/O port chip used for interfacing I/O
devices with microprocessor. It is a very commonly used peripheral chip.

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Knowledge of 8255 essential for students in the Microprocessors lab for interfacing experiments.

8255
Vcc
A7

Gnd

A6

Port A

D7-0

A5

A4

PA7-0

Port C

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RD*

40 pin DIP

Con trol Port


Port B

PC7-4
PC3-0

A1

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There are 3 ports in 8255 from users point of view - Port A, Port B and Port C.
Port C is composed of two independent 4-bit ports : PC7-4 (PC Upper) and PC3-0 (PC Lower)

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Selection of Ports

A1

A0

Selected port

Port A

Port B

Port C

Control port

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There is also a Control port from the Processor point of view. Its contents decides the working of 8255.
When CS (Chip select) is 0, 8255 is selected for communication by the processor. The chip select circuit
connected to the CS pin assigns addresses to the ports of 8255.

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There are 3 modes of operation for the ports of 8255. Mode 0, Mode 1, and Mode 2.

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For the chip select circuit shown, the chip is selected when A7=0, A6=1, A5=1, A4=1, A3=1, A2=1, and
M/IO*= 0. Port A, Port B, Port C and Control port will have the addresses as 7CH, 7DH, 7EH, and 7FH
respectively.

Mode 0 Operation
It is Basic or Simple I/O. It does not use any handshake signals. It is used for interfacing an i/p device or
an o/p device. It is used when timing characteristics of I/O devices is well known.

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Mode 1 Operation
It uses handshake I/O. 3 lines are used for handshaking. It is used for interfacing an i/p device or an o/p
device. Mode 1 operation is used when timing characteristics of I/O devices is not well known, or used
when I/O devices supply or receive data at irregular intervals.

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Handshake signals of the port inform the processor that the data is available, data transfer complete etc.
More details about mode 1 operation is provided later.

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Mode 2 Operation
It is bi-directional handshake I/O. Mode 2 operation uses 5 lines for handshaking. It is used with an I/O
device that receives data some times and sends data sometimes. Ex. Hard disk drive. Mode 2 operation is
useful when timing characteristics of I/O devices is not well known, or when I/O devices supply or
receive data at irregular intervals.

Port A can work in Mode 0, Mode 1, or Mode 2

Port B can work in Mode 0, or Mode 1


Port C can work in Mode 0 only, if at all

Port A, Port B and Port C can work in Mode 0


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Port A and Port B can work in Mode 1


Only Port A can work in Mode 2

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8.2.8 Where are the Handshake signals?

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We have already listed all the 40 pins of 8255. Port C pins act as handshake signals, when Port A and Port
B are configured for other than Mode 0. Port A in Mode 2 and Port B in Mode 1 is possible, as it needs
only 5+3 = 8 handshake signals. After Reset of 8255, Port A, Port B, and Port C are configured for Mode
0 operation as input ports.

PC2-0 are used as handshake signals by Port B when configured in Mode 1. This is immaterial whether
Port B is configured as input or output port.
PC5-3 are used as handshake signals by Port A when configured as input port in Mode 1.

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PC7, 6, 3 are used as handshake signals by Port A when configured as output port in Mode 1.
PC7-3 are used as handshake signals by Port A when configured in Mode 2.

There are 2 control words in 8255

Mode Definition (MD) Control word and

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Port C Bit Set / Reset (PCBSR) Control Word

8255 Mode Definition Control word

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Mode definition control word is used to configure the ports of 8255 as input or output in Mode 0, Mode 1,
or Mode 2.

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10CS45

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MICROPROCESSORS

M2A

M1A

I/P A

I/P CU

Means Mode Definition


control word
1 - PCU as input

1 - PA as input

M2A M1A

M1B

0 - PA as output

I/P B

I/P CL

1 -PCL as input

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0 - PCU as output

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Control port having Mode Definition (MD) control word

0 -PCL as output

1 - PB as input
0 - PB as output

Port A in Mode 0

Port A in Mode 1

0/1

Port A in Mode 2

1 - PB in Mode 1

0 - PB in Mode 0

.c

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Required MD control word:

MD control word

98H

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PA in Mode 0

PA as input

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PC Lower as output

PB as output

PB in Mode 0

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PC Upper as input

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10CS45

Assignment Questions
UNIT- 1

om

1. Define Microprocessor, Microcontroller, Reprogrammable System, and an Embedded System.


2. What do you mean by the power of a Microprocessor? Mention the Architectural Parameters
to distinguish between Microprocessors.

4.Distinguish between
Microprocessors.

Accumulator-Based

and

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3. Draw and explain the block diagram of microprocessor based system and also explain the
general sequence it follows to execute the instructions.
General

Purpose

Register

Based

5. Mention the Architectural features of 8086 Microprocessor.

6. Explain the architecture of 8086 microprocessor with a neat block diagram.

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7. Describe a scheme to demultiplex the multiplexed AD0-AD7 bus of 8086CPU.


8. Differentiate I/O mapped I/O and memory mapped I/O interfacing techniques.
9. Explain the different methods of data transfer possible between MPU and I/O.
10. Mention the differences between 8085 and 8086 Microprocessors.
11. What do you mean by pipelined architecture of CPU?

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12. Describe the Minimum Mode Configuration System of 8086 with a neat block schematic.
UNIT 2

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1. Describe the different instruction formats of 8086.

2. Draw the register organization of 8086 and explain typical applications of each
register.

3. With a neat block diagram explain the Internal Architecture of 8086/8088.

4. Explain conditional and control flags of 8086.


5. Explain why memory is divided into segments in 8086? What are its advantages?
6. Explain the Min. & Max. Mode of operation of 8086 with details of each pin.

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7. State the function of the following signals of 8086:


i) RQ/GT ii) LOCK iii) DT/R. iv) MN / MX v) QS0, QS1
vi) TEST vii) BHE viii) RESET ix) IO / M x) READY

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UNIT 3
1. What is bus cycle? Draw memory-read bus cycle in min. mode of operation of 8086.
2. What signals are activated when an I / O port at address ABCD Hex is read by an

3. State and explain the instruction formats of 8086.

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8086? Indicate the action using the timing diagram for these signals.

4. What is addressing mode? Explain different addressing schemes used in 8086 with examples
of each.

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5. Which instruction of 8086 can be used for look up table manipulations? Justify your answer
with an example.
6. Examine the overall result of the following 8086 ALP blocks and give single 8086
instructions that can do the same job as the blocks.
i) JNC DOWN
ii) PUSH AX
iii) PUSH AX
INC AX PUSH BX PUSH BX
DOWN: NOP POP AX POP BX
BX POP CX

POP

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7. Explain the functions of the following instructions in 8086:


(i) XLAT
(ii) DAA
(iii) XCHG AX, BX (iv) MOVSB

UNIT - 4

.c

8. Consider the following pairs of partial programs:


i) MOV AX, 4000H ii) MOV AX, 4000H
ADD AX, AX ADD AX, AX
ADC AX, AX RCL AX, 1
JZ DOWN JZ DOWN
For each of these cases i) and ii), what will be the data in AX after executing instruction 3 and
from where will the instruction be fetched after executing instruction 4?

1. What is the difference between the NEAR and FAR procedure? Explain.
2. Bring out difference between MACRO and PROCEDURE.
3. Write an assembly language program in 8086 to count the number of positive & negative
numbers present in a series of 10signed 8 bit numbers stored from address ARRAY. Store the
results at locations PNOS & NNOS respectively.

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4. Explain briefly the instruction used to handle look up tables in 8086.


5. Write en assembly language program in 8086 to arrange the ten 8bit numbers stored in a
memory starting with address ARRAY in ascending order.

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6. Write an 8086 to find the GCD and the LCM of two 16 bit numbers. Explain your program
ONLY through proper comments.

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7. Write an 8086 ALP subroutine for doing bubble sort of a word array in the ascending order,
returning all registers intact. Explain your program ONLY through comments

8. Write an 8086 ALP to find factorial of a number using recursive algorithm. Write comments
to make the program clear.
9. Write an 8086 ALP to convert set of BCD bytes to binary. Use main program and sub routine
BCD-BIN for conversion. Write comments.

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10. Write a non-recursive ALP subroutine of 8086, to evaluate the number Fn = Fn-1 + Fn-2 for
any given n > 1. Starting from the definition; F0 = 0 and F1 = 1. Consider the number. Consider
the number n to be such that Fn is not more than a 16 bit unsigned number.
UNIT - 5

1. What are assembler directives? Explain any 6 such directives used in MASM assembler for
8086 programming
2. How does main program and sub routine communicates? Explain with an example.

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3. With suitable example, explain the following instructions by stating the addressing mode they
belong to:
i) LDS ii) XLAT iii) CWD iv) SCAS

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4. Find out the machine code for the following instructions:


i) LEA SI, [BX = 500H] ii) CALL [5000h] iii) NEG 50 [BP] iv) IN DX, AX

5. Write the flow chart and the 8086 ALP to convert the BCD numbers 0 to 9 to their equivalent
seven segment codes using the look-up table technique. Assume the CODELIST at the relative
addresses from 0 to 9. The BCD number (CHAR) is taken in AL.

UNIT - 6

1. Describe the interrupt sequence of 8086.


2. What do mean by interrupt priorities? List out interrupt priorities in 8086.
3. Write ALPs to generate the following delays, using microprocessor system that runs at 5 MHz.

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UNIT - 7
1. Explain how a software delay program can be written for 100msec delay for an 8086 system
connected with 10MHz crystal.

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3. Bring out the differences between static and a dynamic RAM.

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2. Explain clearly the process of reading a WORD from an odd address in an 8086 system,
bringing out the necessity of performing two memory read operations in this case, as compared
to reading a WORD from an even address that requires only one memory read operation.

4. Interface eight 8K chips of RAM and four 8K EPROM with 8086. Interface the RAM bank at
a segment address 0B00h and the EPROM bank at a physical address F8000H. Do not allow any
fold bank space.
UNIT - 8

1. Discuss modes of operation of 8255 programmable peripheral interfaces.

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2. Draw and explain a typical Stepper Motor Interface. Further, write an ALP to rotate a shaft of
a 4-phase stepper motor in clockwise by 5 rotations.
3. Write short notes on the following:
i) MACROS ii) Control of High Power devices using 8255.

4. What are the criteria to be considered before interfacing memory to the processor?

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5.Interface a DAC 0800 to 8086 and write a program to generate a triangular waveform.

***********************

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6. Interface a set of 8 simple switches and 8 simple LEDS to 8086 using a 8255 PPI chip. The
8255 should be selected for the following addresses. Write a program to indicate the status of the
switches on LEDs
port A:0740 H, port B:0742H, port C:0744H CWR:0746H.

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10CS45

VTU-Question Bank
Unit-1
1.a. Draw the physical memory system diagram for Intel Pentium microprocessors.

om

July/July 13 [8 marks]

1.c. What is pipe lining? how is it achived in 8086?

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1.b. Discuss the functions of segment registers of 8086 with examples. Give some advantages of
memory segmentation.
July/July 13 [6 marks]
July/July 13 [6 marks]

2.a. Explain the memory structure of intel personal computer in detail with neat schematic.

Dec 13/Jan 14 [8marks]

2.b. Briefly explain various multipurpose registers in 8086

Dec 13/Jan 14 [6marks]

2.c. What is real mode addressing? Explain default segment and offset registers.

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Dec 13/Jan 14 [06 Marks]

3.a. With a neat diagram explain the architecture along with function of each block and register.
Dec 2012 [10 Marks]
3.b. How many address lines does an 8086 have?

Dec 2012 [05 Marks]

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a. How many memory address does this number of address lines allow the 8086 to
access directly?
b. At any given time the 8086 works with 4 segments in this address space. How
many bytes are contained in each segment?
c. Describe the difference between the instructions MOV AX,2347H and MOV
AX,[2347H]

.c

3.c. Write 8086 assembly instruction which will perform the following operations:

Dec 2012 [05 marks]

i)

Multiply AL times BL.

ii)

Load the number F3H into AL register.

iii)

Copy BP register contents to SP register.

iv)

Divide the AL register contents by 2 bu using a shift instruction.

v)

Multiply the AL register contents by 4 using shift instruction.

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10CS45

4.a. Define microprocessor. With a neat block diagram

Jan 2015 [6 Marks]

4.b. What is flag register? Explain the flag register format, in detail.

Jan 2015 [6 Marks]

4.c. List and explain the addressing modes supported by 8086.

Jan 2015 [6 Marks]

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5.a Define a microprocessor. Explain the programming model of the 8086 through the CORE-2
microprocessor including the 64-bit extensions.
June 2014[06 marks]
5.b Explain in detail with a neat figure the worning of the internal architecture of the 8086 MP

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June 2014[08 marks]

June 2014[06 marks]

5.c Explain in detail the various bits of a flag register for 8086 MP

Unit-2

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1.a. Explain how virtual address is translated into physical address with a neat diagram.

June/July 13 [08 marks]

1.b. Identify the addressing modes of the following instructions and explain them briefly.

a) mov word ptr[si],20h


b) move s:[1000h],10h
c) mov cx,num[bx+di]

June/July 13 [06 marks]

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1.c. briefly explain the flat mode memory model with a neat diagram.
June/July 13 [06 marks]

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2.a. Illustrate the memory paging mechanism in the 80386 mp with suitable schematic.
Dec 13/Jan 14 [06 marks]

2.b. briefly explain various addressing modes of 8086 with suitable examples.
Dec 13/Jan 14 [10 mark]

2.c. what do the following MOV instructions accomplish?

Dec 13/Jan 14 [04 marks]

MOV RAX,RCX
MOV ESP,[BSP]
MOV AX,2341H
MOV CS,AX

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10CS45

3.a. State and explain instruction formats of 8086. Also generate the opcode for
following
instructions.
Dec 2012 [10 marks]
3.b. Explain the following assembler directive with example.

Dec 2012 [10 marks]

i) PROC & ENDP ii) PUBLIC & EXTRN iii) MACRO & ENDM

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3.c. Write the assembly language development tools along with algorithm. Dec 2012 [12 Marks]
iv) ASSUME

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v) SEGMENT, ENDS vi) PROC & ENDP

4.a. Write and explain instruction template for MOV instruction. Also generate opcode for
following instructions: the opcode for MOV is
Jan 2015 [15 Marks]

i)

MOV CL,[BX]

ii)

MOV CS,[BX],DL

iii)

MOV 43H[SI[,DH

iv)

MOV CX,[437A]H

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1 0 0 0 1 0

4.b. What is an assembler directive? Explain the following assembler directive with example:
Jan 2015 [10 Marks]

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5.a Explain with an example why and how a 20 bit address is generated in 8086

June 2014[05 marks]


June 2014[10 marks]

5.c Explain the concept of protected mode of memory addressing

June 2014[05 marks]

Unit-3

.c

5.b Explain any five addressing modes in detail with examples in 8086

1. a. Write an ALP using 8086 instructions to search a number placed in location NUM,in an
array of ten numbers placed at location ARRAY.
June/July 13 [8 marks]
1.b. describe the following instructions with an example:

June/July 13 [8 marks]

a) LEA
b) XCHG
c) DAA

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10CS45

d) MUL
1.c. Give the state of all the status flags bits after the addition of 30a2 with f01ch.
June/July 13 [8 marks]

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2.a. Write and explain machine code for instruction MOV DL,[BX]
Dec 13/Jan 14 [10 marks]

PUSHF MOVS

LAHF DIV

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2.b. Describe the operation of each of the following instruction in brief.


XCHG

Dec 13/Jan 14 [5 marks]

2.c. what is segment override prefix? Illustrate the same with an example.

Dec 13/Jan 14 [5 marks]

3.a. Write an ALP to find factorial of a number using recursion.

Dec 2012 [10 marks]

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3.b. Explain the types of program execution transfer instruction (Branch instructions) with
examples.
Dec 2012 [10 marks]
4.a. What is the need for unconditional jump instructions, explain different conditional jump
supported by 8086.
Jan 2015 [10 marks]
4.b. Write a delay loop, which produces a delay of 5 clock.

Jan 2015 [10 Marks]

5.a Write 8086 ALP to add 10 non-negative data items using string instructions.

June 2014[06 marks]

CMP

LAMF

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5.b Explain the following instruction with examples


XCHG

LEA

PUSH AX

LDS DI,[3000h] June 2014[06 marks]

5.c Explain with example the following assembler directives(any four)


DQ

June 2014[08 marks]

PROC ENDP TYPE EVEN

.c

ORG

Unit-4

1.a. Explain the following assembler directives with examples.

i) DB

ii)EXTRN iii) PROC

June/July 13[8 marks]

iv) SEGMENT

1.b. Differentiate between macros and procedures.

June/July 13[4 mark]

1.c. Write an ALP using 8086 instructions to reverse a four digit number
June/July 13[8 marks]

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2.a. Explain with an example how multiple if then else statement can be implemented using ALP
Dec 13/Jan 14[10 marks]
2.b. Differentiate between short, near and far jump instructions with two examples of each

om

Dec 13/Jan 14 [10 marks]


Dec 2012 [5 Marks]

3.b. Explain REP MOVSB instruction with example.

Dec 2012 [5 Marks]

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3.a. Differentiate between macros and procedures.

3.c. Explain the sequence of operation that takes place when a procedure is called and returned
form procedure base to calling program with block diagram.
Dec 2010 [10 Marks]
4.a. Write an assembly level program to cheek a given string is palindrome or not.

Jan 2015 [12 Marks]

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4.b. Define and differentiate between reentrant and recursive procedures.

Jan 2015 [8 Marks]

5.a Explain the various string manipulation instructions with example

June 2014[06 marks]

5.b Explain the the following instruction with examples any four

June 2014[08 marks]

DAA MUL

ADC SHR

RCL

June 2014[06 marks]

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5.c Explain the different types of jump and cell instructions of 8086

Unit-5
June/July 13 [6 marks]

.c

1.a. What is inline assembly? Explain its need.

1.b. State the C language elements that can be used in the arm block.
June/July 13 [6 marks]

1.c. Explain the basic rules for using assembly language with C/C++ for 16 bit DOS applications
with the help of examples
June/July 13 [8 marks]
2.a. Illustrate a simple program that uses a character string defined with and display on a separate
line.
Dec 13/Jan 14 [10 marks]
2.b. Differentiate between :

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10CS45

i) assembler and linker ii) public and extern iii) macros and procedure
2.c. Write an ALP to compute factorial of single digit positive number using recursive procedure
Dec 13/Jan 14 [4 marks]

3.b. Explain the following instructions with an example:


DAA
AAM
LOOP
SUB
XLAT

Dec 2012 [10 marks]

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i)
ii)
iii)
iv)
v)

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3.a. Write an ALP to find NCR using recursive procedure. Assume N & R are non-Negative
numbers.
Dec 2012 [10 marks]

4a. Explain the following instructions or directives in 8086 programming: i) global ii) call iii)
LAHE iv) TYPE v) NEG viii) TEST ix) GROUP x) XLAT
Jan 2015 [10marks]

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5.a Write a ALP using C/C++ to perform the operation X+Y=Z with proper comments

June 2014[10 marks]

5.b Define modular programming. Using the concepts of public and extra directives writ a program which
reads data in a program in one module which is then used by another module
June 2014[06 marks]

June 2014[04 marks]

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5.c Differentiate between macros and procedures

Unit-6

1.a. Explain the functions of following pins of 8086 mp


iii)HOLD

.c

i) ALE ii)INTR

iv)RESET

June/July 13 [5 Marks]

v)BHE

1.b. Explain how address de-multiplexing is done in 8086 processor based systems.
June/July 13 [7 Marks]
June/July 13 [8 Marks]

1.c. With a neat timing diagram,explain memory read cycle.

2.a. Explain the minimum mode pins of 8086 and maximum mode configuration of 8086 with
neat diagram.
Dec 13/Jan 14 [10 Marks]
2.b. Describe internal block diagram of 8288 bus controller with explanation of each pins
Dec 13/Jan 14 [6 Marks]

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10CS45

Dec 13/Jan 14 [4 Marks]

3.a. differentiate between memory mapped I/O and direct I/O.

Dec 2012 [5 Marks]

3.b. write the timing diagram for a memory read machine cycle.

Dec 2012 [5 Marks]

3.c. With a neat diagram, explain the pin configuration of 8086.

Dec 2012 [10marks]

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2.c. with neat diagram explain I/O read operation.

4.a. Write signal activities on 8086 buses, during a simple read operation.

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Jan 2015 [10 Marks]

4.b. What is need of memory banking? With a neat block diagram, explain the memory banking
in 8086.
Jan 2015 [10 Marks]
5.a Describe in details the uses of the following signals
ACE

RESET

NMI

HOLD

June 2014[06 marks]

MN/MX

QSI and

QSQ

5.b Explain in detail with a neat figure demultiplexing of address and data lines in 8086

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June 2014[06 marks]

5.c Explain with a neat figure the working of 8086 in MIN mode configuration

June 2014[08 marks]

Unit-7

1.a. List various memory devices.

June/July 13 [2 Marks]

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1.b. What is memory address decoding? Design a memory system for 8086 for the following
specifications
June/July 13 [10marks]
i)
ii)

32 kbytes EPROM using 16 Kbytes devices


64 kbytes SRAM using 16 Kbytes devices

.c

Draw memory map.

1.c. what are the sources of interrupts? Briefly explain the steps taken by a processor to execute
an interrupt instruction.
June/July 13 [8marks]

2.a. with a neat diagram, explain simple NAND gate address decoding logic.
Dec 13/Jan 14 [10 marks]

2.b. differentiate between memory mapped I/O and direct I/O

Dec 13/Jan 14 [5 marks]

2.c. Briefly explain handshaking or polling with necessary diagrams


Dec 13/Jan 14 [5 marks]

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10CS45

3.a. Briefly explain the structure of 8086 interrupt response and interrupt vector table with a neat
diagram.
Dec 2012 [10 Marks]
3.b. explain with block diagram, the working of 8259 and also explain ICWs format.

om

Dec 2012 [10 Marks]


4.a. List and explain the hardware interrupt applications.

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Jan 2015 [8 Marks]


4.b. With a neat block diagram, explain the 8259A system connections.

Jan 2015 [9 Marks]

4.c. List the differences between 8086 and 8088.

Jan 2015 [3 Marks]

June 2014[04 marks]

5.a Differentiate between memory mapped I/O and I/O mapped I/O

5.b i)64 kbytes EPROM ii)64 kbytes RAM . assume Ram is connected at 30000h and EPROM at

June 2014[08 marks]

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F00000h.

5.c Explain how a 3-8 line decoder could be used to interfaced eight 8K memory chips.

June 2014[08 marks]

Unit-8

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1.a. briefly explain the control word format of 8255 in I/O mode and BSR mode. Give the
control word format to program port A and port C lower as input and port B and port C upper as
output parts in mode 0.
June/July 13 [10 Marks]

.c

1.b.write an ALP using 8086 instructions to read a byte of data from port A and display its parity
status as 00h or ffh for odd and even parity respectively on port B June/July 13 [5 Marks]
June/July 13 [5 Marks]

1.c. list the features of 8254 PIT (programmable interval timer)

2.a. Explain pin out of 8255 along with different operational modes.
Dec 13/Jan 14 [10 marks]

2.b explain the structure of IVT with the neat diagram.

Dec 13/Jan 14 [10 marks]

3.a. explain the different methods of parallel data transfer with figure in a programmable
peripheral interface.
Dec 2012 [10 Marks]

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10CS45

3.b. Explain with the internal block diagram of 8255, the different operational modes and the
control word formats.
Dec 2012 [10 Marks]
4.a. With a neat block diagram, explain the internal block diagram of 8255A.

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Jan 2015 [8 Marks]


4.b. Design a control word for interfacing keyboard.

Jan 2015 [2 Marks]

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4.c. Write on assembly level program to interface logic controller for multiplication of two 8-bit
numbers.
Jan 2015 [10 Marks]
5.a Explain different signals of 8255 PP and control words.

June 2014[08 marks]

5.b Explain with a neat diagram the interfacing of stepper motor to 8086 using 8255 in detail

June 2014[06 marks]

.c

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5.c Explain the working of different blocks of 8254 PIT with a neat figure June 2014[06 marks]

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10CS45

VTU-Question paper Solution


Unit-1

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1.a. Draw the physical memory system diagram for Intel Pentium microprocessors.

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June/July 13 [8 marks]

.c

Protected mode memory addressing (80286 and above) allows access to data and programs
located above the first 1M byte of memory as well as within the first 1M byte of memory.

Addressing this extended section n of the memory system requires a change to the segment plus

offset addressing scheme used with real mode memory addressing. When data and programs are

addressed in extended memory, the offset address is still used to access information located
within the memory segment. The difference is that the segment address, as discussed with real
mode memory addressing, is no longer present in the protected mode. In place of the segment
address, the segment register contains a selector that selects a descriptor from a descriptor table.
The descriptor describes the memory segment's location, length, and access rights. Because the

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10CS45

segment register and offset address still access memory, protected mode instructions are identical
to real mode instructions. In fact, most programs written to function in the real mode will
function without change in the protected mode. The difference between modes is in the way that

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the segment register is interpreted by the microprocessor to access the memory segment

.c

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1.b. Discuss the functions of segment registers of 8086 with examples. Give some
advantages of memory segmentation
June/July 13 [6 marks]

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A combination of a segment address and an offset address access a memory location in the real
ode. All real mode memory addresses consist of a segment address plus an offset address. The
segment address, located within one of the segment registers, defines the beginning address of

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ny 64K-byte memory segment. The offset address selects any location within the 64K-byte
memory segment. The microprocessor has a set of rules that apply to segments whenever

memory is addressed. These rules, which apply in either the real or protected mode, define the

1.c. what is pipe lining? How is it achieved in 8086?

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segment register and offset register combination used by certain addressing modes.

June/July 13 [6 marks]

In 8086, to speed up the execution of program, the instructions fetching and execution of
instructions are overlapped each other. This technique is known as pipelining. In pipelining,
when the n th instruction is executed, the n+1 th instruction is fetched and thus the processing

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speed is increased
Instruction 1

Instruction 2

Instruction 4

Instruction 3

X
X
Four sample instructions, executed linearly

ID

EX

IF

ID

EX

ID

EX

IF

ID

EX

IF

1
W

1
1
W

Four Pipelined Instructions

.c

IF

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10CS45

2.a. Explain the memory structure of Intel personal computer in detail with neat schematic.

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om

Dec 13/Jan 14 [8 marks]

The transient program area (TPA) holds the operating system and other programs that control the
computer system. The TPA also stores any currently active or inactive application. The length of

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the TPA is bytes. As mentioned, this area of memory holds the system, which requires portion of
the TPA. In practice, the amount of memory for application software is bytes if MSDOSII
version 6.X is used as an operating system. Earlier versions of MSDOS required more of the
TPA and often left only 530K bytes or less for application programs. The memory map shows

.c

how the many areas of the TPA are used for system programs, data, and drivers. It also shows a

large area of memory available for application programs. To the left of each area is a

hexadecimal number that represents the memory addresses that begin and end each data area.
The BIOS and DOS communications areas containtransient data used by programs to access

119de\lices and the internal features of the computer system. These are stored in the TPA so they
echanged as the system operates. Note that the TPA contains read/write memory (called RAM or
random access memory) so it can change as a program executes.

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2.b. Briefly explain various multipurpose registers in 8086


Dec 13/Jan 14 [6 marks]

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AX (accumulator)register: The AX is always involved in multiplication and division as the


default operand and also for I/O operation .we can access AX register as 16-bit register (or) two
8-bit registers AH and AL.(AH-higher 8-bit and AL lower 8-bit)

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BX (base) register : It is used as a pointer to a memory location .It holds offset address relative
to data segment. BX register can be treated as two 8-bit register BH and BL.
CX (counter)register: CX register holds count value for loop an repeat instruction.CX Register
can be treated as two 8-bit register CH and CL.
DX (data) register: The DX is only register used as an I/O address pointer in the IN and OUT
instructions. It also involved in multiplication and division operation. DX register can be treated
as two 8 bit register DH and DL.

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iv) Pointer and index registers: The 8086 processor has two 16 bit pointer, Stack Pointer (SP)
and Base Pointer (BP) and two 16 bit index registers, Source Index (SI) and Destination Index
(DI).
Stack Pointer (SP) Register: The SP register holds the offset address and always points to the top
of the stack relative to stack segment.
Base Pointer (BP) Register: The BP register holds the offset address relative to stack segment.
The physical address=SS*10h+SP (or BP).

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Source Index (SI) Register: This register holds the offset address of the data relative to data
segment. In string instructions, SI is used as a pointer to source string element.

.c

Destination Index (DI) Register: This register also holds the offset address of the data relative to
data segment. In string instructions, DI is used as a pointer to destination string element.

The physical address=DS*10h+ SI (or BX or DI)


Relative to extra segment, we have to use DI to access the data. In this case

The physical address=ES*10h+DI

v) Flag Register: The 16 bit flag register of the 8086 processor stores information about the
status of the processor and the status of the instruction executed most recently.

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2.c. what is real mode addressing? Explain default segment and offset registers.

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Dec 13/Jan 14 [6 marks]

The 80286 and above operate in either the real or protected mode. Only the 8086 and 8088
operate exclusively in the real mode. This section of the text details the operation of the

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microprocessor in the real mode. Real mode operation allows the microprocessor to address only
the first 1M byte of memory space-even the Pentium microprocessor. Note that the first 1M byte
of memory is called either the real memory or conventional memory system. Both the MSDOS
or PCDOS operating systems assume that the microprocessor is operated in the real mode at all,
times. Real mode operation allows applicationsoftware written for the 8086/8088, which

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contains only 1Mbyte of memory, to function in the 80286 and above without changing the
software. At present, 95 percent of all software in use is designed to operate in the real mode.
This will most likely change as Windows 95 becomes the new 32-bit operating platform. The
upward compatibility of software is partially responsible for the continuing success of the Intel

.c

family of Microprocessors. In all cases, each of these microprocessors begins operation in the

real mode by default whenever power is applied or the microprocessor is reset. Note that the
DOS environment is a real mode environment.

Segments and Offsets

A combination of a segment address and an offset address access a memory location in the real
mode. All real mode memory addresses consist of a segment address plus an offset address. The
segment address, located within one of the segment registers, defines the beginning address of
any 64K-byte memory segment. The offset address selects any location within the 64K-byte
memory segment.

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10CS45

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3.a. With a neat diagram, explain the architecture of 8086 microprocessor along with
functions of each block and registers.
Dec 2012 [10 Marks]

The 8086 processor is divided into two independent functional units


1) Bus Interface Unit(BIU)
2) Execution Unit(EU)

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Bus Interface Unit: The BIU sends out addresses, fetches instructions from memory, reads data
from ports and memory and writes data to ports and memory.
The functional parts of the BIU are:

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i) Instruction Queue(IQ)

ii) Segment Register

iii) Instruction Pointer

i) Instruction Queue: The Instruction Queue is of six bytes in length and is used to send up the
execution of programs by pre-fetching six instruction bytes in advance from memory.
The BIU and EU works parallely. The BIU fetches the instruction bytes while the EU is
executing an instruction.

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The process of pre-fetching the instruction in advance while EU is executing the current
instruction is known as pipelining.
ii)Segment Register: The BIIU contains 4 16 bit segment registers. They are:

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a. Code Segment Register


b. Data Segment Register

d. Extra Segment Register

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c. Stack Segment Register

These registers are used to store the 16 bit starting address of the four memory segment. The BIU
generates a 20 bit physical address using the segment and the offset component of an address.

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a) Code Segment Register : Code Segment(64 kb) of memory contains instruction of the
program. The CS register holds the 16 bit starting address of this segment. To access the storage
location of an instruction in the active code segment, the 8086 must generate its 20 bit physical
address. To do this, it combines contents of the instruction pointer register(offset address) with
the values in CS register(base address).
b) Data Segment Register: The DS register holds the starting 16 bit address of the data segment
(64 kb) where most of the datas are stored. The memory offset stored in the registers BX, SI,
and DI operate relative to data segment.

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c) Stack Segment Register: The SS register holds the starting 16 bit address of the stack segment
(64 kb). The stack is a section of memory set aside to store address and data while a subprogram
is executing.The SP and BP holds the offset address relative to the stack segment.

.c

d) Extra Segment Register: The ES Register holds the starting 16 bit address of the extra segment
(64 kb). The Extra Segment is generally used to make an additional lock of memory available
for data storage. The ES is extensively used in string instructions. It is used as the destination
segment, addressed by the combination of register ES:DI(here DI holds the offset address).

iii) Instruction Pointer Register: The IP always holds the offset address of the next instruction to
be executed. As the instruction is executed, IP is advanced to point the next instruction at the
next memory address. IP doesnt fully specify the address of the next instruction to be executed.

The 20 bit physical address=base address*10h+offset address


For Ex physical address=CS*10h+IP
2) Execution Unit(EU): The EU informs the BIU the location at which the next instruction or
data to be fetched. The phases of the EU are fetch, decode, execute and write. The fetch phase

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performs fetching of instruction. the execute phase performs the operation of string the computed
result at the destination .
The functional unit of the EU are

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i) Control circuitry
ii) Arithmetic and logic unit (ALU)

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iii) General purpose registers


iv) Pointer and index registers
v) Flag register

i)control circuitry: the control circuit of the EU directs all internal operation of the processors.
ii)Arithmetic and logic unit: the ALU performs 8-bit or 16-bit arithmetic operation such as
addition , subtraction, multiplication, division, and logical operation of the processor.

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iii)general purpose register : the 8086 processor has four 16-bit GPRS. The GPRS can be used
to store the intermediate result instead storing it in memory ,because the access speed of data
from GPRS is more compared to memory location. we can use all GPRS for data transfers. The
GPRS are AX, BX, CX, and DX. We can access these register either 16-bit register (or) two 8bit registers Each GPRS have specific function.

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AX (accumulator)register: The AX is always involved in multiplication and division as the


default operand and also for I/O operation .we can access AX register as 16-bit register (or) two
8-bit registers AH and AL.(AH-higher 8-bit and AL lower 8-bit)
BX (base) register : It is used as a pointer to a memory location .It holds offset address relative
to data segment. BX register can be treated as two 8-bit register BH and BL.

.c

CX (counter)register: CX register holds count value for loop an repeat instruction.CX Register
can be treated as two 8-bit register CH and CL.

DX (data) register: The DX is only register used as an I/O address pointer in the IN and OUT
instructions. It also involved in multiplication and division operation. DX register can be treated
as two 8 bit register DH and DL.

iv) Pointer and index registers: The 8086 processor has two 16 bit pointer, Stack Pointer (SP)
and Base Pointer (BP) and two 16 bit index registers, Source Index (SI) and Destination Index
(DI).
Stack Pointer (SP) Register: The SP register holds the offset address and always points to the top
of the stack relative to stack segment.

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Base Pointer (BP) Register: The BP register holds the offset address relative to stack segment.
The physical address=SS*10h+SP (or BP).

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Source Index (SI) Register: This register holds the offset address of the data relative to data
segment. In string instructions, SI is used as a pointer to source string element.
Destination Index (DI) Register: This register also holds the offset address of the data relative to
data segment. In string instructions, DI is used as a pointer to destination string element.

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The physical address=DS*10h+ SI (or BX or DI)


Relative to extra segment, we have to use DI to access the data. In this case
The physical address=ES*10h+DI

v) Flag Register: The 16 bit flag register of the 8086 processor stores information about the
status of the processor and the status of the instruction executed most recently.

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Conditional Flags: Carry flag (CF), Parity flag (PF), Auxiliary carry flag (AF), Zero flag (ZF),
Sign flag (SF), Overflow flag (OF), Control flags: Trap flag (TF), Interrupt flag (IF), Direction
flag (DF).U-Undefined.
3.c. Write 8086 assembly instruction which will perform the following operations:
Dec 2012 [05 marks]

Multiply AL times BL.

ii)

Load the number F3H into AL register.

iii)

Copy BP register contents to SP register.

iv)

Divide the AL register contents by 2 bu using a shift instruction.

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i)

Ans :

.c

Multiply the AL register contents by 4 using shift instruction.

i)

mul BL

ii)

mov AL,F3H

iii)

mov sp,bp

Mov CL,02
SHL AL,CL

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iv)

10CS45

mov CL,02

SHL AL,CL

Microprocessor:

Jan 2015 [6 Marks]

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4.a. Define microprocessor. With a neat block diagram

.c

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It is a semiconductor device consisting of electronic logic circuits manufactured by using either a


Large scale (LSI) or Very Large Scale (VLSI) Integration Technique. It includes the ALU,
register arrays and control circuits on a single chip. The microprocessor has a set of instructions,
designed internally, to manipulate data and communicate with peripherals. This process of data
manipulation and communication is determined by the logic design of the microprocessor called
the architecture.

Jan 2015 [6 Marks]

4.b. What is flag register? Explain the flag register format, in detail.

4.c. List and explain the addressing modes supported by 8086.

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10CS45

8086 ADDRESSING MODES


A. Immediate addressing mode:
In this mode, 8 or 16 bit data can be specified as part of the instruction.

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OP Code Immediate Operand

Moves the 8 bit data 03 H into CL


Register addressing mode :

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Example 1 : MOV CL, 03 H

The operand to be accessed is specified as residing in an internal register of 8086. Fig. below
shows internal registers, any one can be used as a source or destination operand, however only
the data registers can be accessed as either a byte or word.
Direct addressing mode :

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The instruction Opcode is followed by an affective address, this effective address is directly used
as the 16 bit offset of the storage location of the operand from the location specified by the
current value in the selected segment register.
Register indirect addressing mode :

The EA is specified in either pointer (BX) register or an index (SI or DI) register. The 20 bit
physical address is computed using DS and EA.

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Register indirect addressing mode :

The EA is specified in either pointer (BX) register or an index (SI or DI) register. The 20 bit
physical address is computed using DS and EA.

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String addressing mode:

The string instructions automatically assume SI to point to the first byte or word of the source
operand and DI to point to the first byte or word of the destination operand. The contents of SI
and DI are automatically incremented (by clearing DF to 0 by CLD instruction) to point to the
next byte or word.

I/O mode (direct) :


Port number is an 8 bit immediate operand.
Example : OUT 05 H, AL

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Outputs [AL] to 8 bit port 05 H


I/O mode (indirect):
The port number is taken from DX. Example 1 : INAL, DX

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5.a Define a microprocessor. Explain the programming model of the 8086 through the CORE-2
microprocessor including the 64-bit extensions.
June 2014[06 marks]

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A microprocessor incorporates the functions of a computer's central processing unit (CPU) on a


single integrated circuit (IC),[1] or at most a few integrated circuits.[2] All modern CPUs are
microprocessors making the micro- prefix redundant. The microprocessor is a multipurpose,
programmable device that accepts digital data as input, processes it according to instructions
stored in its memory, and provides results as output. It is an example of sequential digital logic,
as it has internal memory. Microprocessors operate on numbers and symbols represented in the
binary numeral system.

The integration of a whole CPU onto a single chip or on a few chips greatly reduced the cost of
processing power. The integrated circuit processor was produced in large numbers by highly
automated processes, so unit cost was low. Single-chip processors increase reliability as there are
many fewer electrical connections to fail. As microprocessor designs get faster, the cost of

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10CS45

manufacturing a chip (with smaller components built on a semiconductor chip the same size)
generally stays the same.

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Before microprocessors, small computers had been implemented using racks of circuit boards
with many medium- and small-scale integrated circuits. Microprocessors integrated this into one
or a few large-scale ICs. Continued increases in microprocessor capacity have since rendered
other forms of computers almost completely obsolete (see history of computing hardware), with
one or more microprocessors used in everything from the smallest embedded systems and
handheld devices to the largest mainframes and supercomputers.

5.b Explain in detail with a neat figure the working of the internal architecture of the 8086 MP

June 2014[08 marks]

The 8086 processor is divided into two independent functional units


1) Bus Interface Unit(BIU)

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2) Execution Unit(EU)

Bus Interface Unit: The BIU sends out addresses, fetches instructions from memory, reads data from ports
and memory and writes data to ports and memory.
The functional parts of the BIU are:
i) Instruction Queue(IQ)

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ii) Segment Registeriii) Instruction Pointer

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i) Instruction Queue: The Instruction Queue is of six bytes in length and is used to send up the execution
of programs by pre-fetching six instruction bytes in advance from memory.

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The BIU and EU works parallel. The BIU fetches the instruction bytes while the EU is executing an
instruction.

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The process of pre-fetching the instruction in advance while EU is executing the current instruction is
known as pipelining.
ii)Segment Register: The BIIU contains 4 16 bit segment registers. They are:
a. Code Segment Register
b. Data Segment Register
c. Stack Segment Register
d. Extra Segment Register

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These registers are used to store the 16 bit starting address of the four memory segment. The BIU
generates a 20 bit physical address using the segment and the offset component of an address.
a) Code Segment Register : Code Segment(64 kb) of memory contains instruction of the program. The
CS register holds the 16 bit starting address of this segment. To access the storage location of an
instruction in the active code segment, the 8086 must generate its 20 bit physical address. To do this, it
combines contents of the instruction pointer register(offset address) with the values in CS register(base
address).

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b) Data Segment Register: The DS register holds the starting 16 bit address of the data segment (64 kb)
where most of the datas are stored. The memory offset stored in the registers BX, SI, and DI operate
relative to data segment.

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c) Stack Segment Register: The SS register holds the starting 16 bit address of the stack segment (64 kb).
The stack is a section of memory set aside to store address and data while a subprogram is executing.The
SP and BP holds the offset address relative to the stack segment.

d) Extra Segment Register: The ES Register holds the starting 16 bit address of the extra segment (64 kb).
The Extra Segment is generally used to make an additional lock of memory available for data storage.
The ES is extensively used in string instructions. It is used as the destination segment, addressed by the
combination of register ES:DI(here DI holds the offset address).
iii) Instruction Pointer Register: The IP always holds the offset address of the next instruction to be
executed. As the instruction is executed, IP is advanced to point the next instruction at the next memory
address. IP doesnt fully specify the address of the next instruction to be executed.
The 20 bit physical address=base address*10h+offset address

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For Ex physical address=CS*10h+IP


2) Execution Unit(EU): The EU informs the BIU the location at which the next instruction or data to be
fetched. The phases of the EU are fetch, decode, execute and write. The fetch phase performs fetching of
instruction. the execute phase performs the operation of string the computed result at the destination .

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The functional unit of the EU are


i) Control circuitry

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ii) Arithmetic and logic unit (ALU)


iii) General purpose registers
iv) Pointer and index registers
v) Flag register

i)control circuitry: the control circuit of the EU directs all internal operation of the processors.

addition ,

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ii)Arithmetic and logic unit: the ALU performs 8-bit or 16-bit arithmetic operation such as
subtraction, multiplication, division, and logical operation of the processor.

iii)general purpose register : the 8086 processor has four 16-bit GPRS. The GPRS can be used to store
the intermediate result instead storing it in memory ,because the access speed of data from GPRS is more
compared to memory location. we can use all GPRS for data transfers. The GPRS are AX, BX, CX, and
DX. We can access these register either 16-bit register (or) two 8-bit registers Each GPRS have specific
function.

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AX (accumulator)register: The AX is always involved in multiplication and division as the default


operand and also for I/O operation .we can access AX register as 16-bit register (or) two 8-bit registers
AH and AL.(AH-higher 8-bit and AL lower 8-bit)
BX (base) register : It is used as a pointer to a memory location .It holds offset address relative to data
segment. BX register can be treated as two 8-bit register BH and BL.

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CX (counter)register: CX register holds count value for loop an repeat instruction.CX Register can be
treated as two 8-bit register CH and CL.

DX (data) register: The DX is only register used as an I/O address pointer in the IN and OUT instructions.
It also involved in multiplication and division operation. DX register can be treated as two 8 bit register
DH and DL.

iv) Pointer and index registers: The 8086 processor has two 16 bit pointer, Stack Pointer (SP) and Base
Pointer (BP) and two 16 bit index registers, Source Index (SI) and Destination Index (DI).
Stack Pointer (SP) Register: The SP register holds the offset address and always points to the top of the
stack relative to stack segment.

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Base Pointer (BP) Register: The BP register holds the offset address relative to stack segment. The
physical address=SS*10h+SP (or BP).
Source Index (SI) Register: This register holds the offset address of the data relative to data segment. In
string instructions, SI is used as a pointer to source string element.

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Destination Index (DI) Register: This register also holds the offset address of the data relative to data
segment. In string instructions, DI is used as a pointer to destination string element.

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The physical address=DS*10h+ SI (or BX or DI)


Relative to extra segment, we have to use DI to access the data. In this case
The physical address=ES*10h+DI

v) Flag Register: The 16 bit flag register of the 8086 processor stores information about the status of the
processor and the status of the instruction executed most recently.

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Conditional Flags: Carry flag (CF), Parity flag (PF), Auxiliary carry flag (AF), Zero flag (ZF), Sign flag
(SF), Overflow flag (OF), Control flags: Trap flag (TF), Interrupt flag (IF), Direction flag (DF).UUndefined.

5.c Explain in detail the various bits of a flag register for 8086 MP

June 2014[06 marks]

When a system is instructed to single-step, it will execute one instruction and then stop. The contents of
registers and memory locations can be examined; if they are correct, the system can be told to go on and
execute the next instruction. The Intel 8086 trap flag and type-1 interrupt response make it quite easy to

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implement a single-step feature in an 8086-based system. If the trap flag is set, the 8086 will
automatically do a type-1 interrupt after each instruction executes. When the 8086 does a type-1 interrupt,

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it pushes the flag register on the stack.

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10CS45

Unit-2
1.a. Explain how virtual address is translated into physical address with a neat diagram.

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June/July 13 [08 marks]

The memory paging mechanism located within the 80386 and above allows any physical
memory location to be assigned to any linear address. The linear address is defined as the
address generated by a program. With the memory paging unit, the linear address is invisibly

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translated into any physical address. This allows an application written to function at a specific
address to be relocated through the paging mechanism. It also allows memory to be placed into
areas where no memory exists. An example is the upper memory blocks provided by
EMM386.EXE. The EMM386.EXE program reassigns extended memory, in 4K blocks, to the

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system memory between the video BIOS and the system BIOS ROMS to provide upper memory

blocks. Without the paging mechanism, the use of this area of memory is impossible.

1.b. Identify the addressing modes of the following instructions and explain them briefly.
June/July 13 [06 marks]

a) mov word ptr[si],20h--------Ans Indexed Mode


b) move s:[1000h],10h-----------Ans Direct Mode
c) mov cx,num[bx+di]----------Ans Based Indexed Mode

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10CS45

1.c. Briefly explain the flat mode memory model with a neat diagram.

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June/July 13 [06 marks]

2.a. Illustrate the memory paging mechanism in the 80386 mp with suitable schematic.
Dec 13/Jan 14 [06 marks]

The memory paging mechanism located within the 80386 and above allows any physical
memory location to be assigned to any linear address. The linear address is defined as the

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address generated by a program. With the memory paging unit, the linear address is invisibly
translated into any physical address. This allows an application written to function at a specific
address . Paging Registers The paging unit is controlled by the contents of the microprocessor's
control registers. for the contents of control registers CRO through CR3. Note that these registers

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are only available to the 80386 through the Pentium Pro microprocessors. Also note that the

Pentium/ Pentium Pro contain an additional control register labeled CR4 that controls extensions
provided in the PentiumJPentium Pro microprocessors. One of these features is a 4M byte page

that is enabled by setting bit position 4 or CR4.

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10CS45

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MICROPROCESSORS

2.b. briefly explain various addressing modes of 8086 with suitable examples.

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Dec 13/Jan 14 [10 mark]

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10CS45

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MICROPROCESSORS

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10CS45

2.c. What do the following MOV instructions accomplish?

Dec 13/Jan 14 [04 marks]

MOV RAX,RCX
MOV ESP,[BSP]

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MOV AX,2341H

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MOV CS,AX

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3.a. State and explain instruction formats of 8086. Also generate the op-code for following
instructions.
Dec 2012 [10 marks]

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1. The upper 6 bits of the 1st byte are an opcode which indicates the general type of instruction.
A 6 bit opcode for the MOV register memory to from register instruction is find it to be 100010.

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2. The D bit is used to indicate whether the data is more to register (or) from the register. If the
instruction moving the data to register then said D=1 If the instruction moving the data from
register then said D=0

3. W bit indicates whether a byte or a word is being moved. If you are moving a byte make W=0,
If you are moving a word make W=1.

4. The 3 bit register field is used to indicate which register is involved in instruction and find the
equivalent binary code of the register fro the table.
5. The 2 bit mode field is used to specify the derived addressing mode
* If the instruction contain both the operands are register then set MOD=11.
* If the instruction having 8 bit displacement then MOD=01

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* If the instruction having 16 bit displacement then MOD=10


* If the instruction having no bit displacement then MOD=00.
6. The 3 bit (or) r/m is used to indicate 32 possible addressing modes and is chose from the table.

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i) MOV AX,BX

iii) MOV CS:[BX], AL.

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ii)MOV 46h[BP], DX

3.b. Explain the following assembler directive with example.

Dec 2012 [10 marks]

i) PROC & ENDP ii) PUBLIC & EXTRN iii) MACRO & ENDM iv) ASSUME
v) SEGMENT, ENDS vi) PROC & ENDP

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The PROC directive is used to identify the start of a procedure. The PROC directive
follows a name you give the procedure. After the PROC directive the term near or the term far is
used to specify the type of the procedure.
Syntax: procedure name PROC

Ex: SMART_DIVIDE PROC FAR.

The PROC directive is used with the ENDP directive to bracket a procedure.
ENDP: End of procedure

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This directive is used along with the name of the procedure to indicate the end of a procedure to
the assembler. The directive ENDP & PROC must lose the procedure code.
Syntax: procedure name ENDP

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Ex: XBX 2ASC ENDP

ii) PUBLIC & EXTRN

PUBLIC : The directive public informs the assembler that are specified variable or segment can
be accessed from other program modules. It helps in managing the multi program modules by
sharing the global variable is procedure.
Syntax: PUBLICvariable 1, variable 2, .., variable n
Ex: PUBLIC XMAX, YMAY
iii) MACRO and ENDM

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The macro definition directives are used to define macro construction and macro function
MACRO. The directive MACRO consists of the name of a macro followed by the keyword
MACRO and macro argument if any.

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Syntax: MACRO name MACRO (argument.argument n)


Ex: Pt String MACRO msg
MOV DH, 09h

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MOV DX, offset msg


int 21h
ENDM
ENDM: End of MACRO

The directive ENDM inform the assembler the end of the macro.

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FORM: ENDM
Ex: pointing macro
ENDM
iv) ASSUME

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It directly tells the assembler that names have been chosen for the code, data, extra and stack
segment. When the program is loaded, the processor segment register to be pointed to the
respective logical segment.
Syntax: ASSUME SEG, REG: SEGMENT_NAME

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ASSUME CS: my_code

ASSUME ES:_Extra

Where assume is an assembler directive segment register. Segment it can be any valid symbol
except the resolved keyword.

v) SEGMENT, ENDS
SEGMENT: This directive is used to indicate the beginning of a logical segment.
The directive segment follows the name of the segment.
Ex: DATA SEGMENT

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:
DATA ENDS
The directive segment & ends enclose the segment data code(or) stack of the program.

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ENDS: Refers to the end of segment. This directive informs the assembler the and of the
segment.

i)DIV ii)XLAT iii)AAA iv)XCHG


i)DIV: Unsigned Divide -DIV source
Syntax: DIV source

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Syntax: Segment name ends

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This instruction divides an unsigned word by a byte (or) to divide an unsigned double word(32
bits) by a word. When dividing a word by a byte, the word must be in AX register. After the
division AL will contain a 8 bit quotient & AH will contain an 8 bit remainder.If an attempt is
made to divide by 0/ the quotient is too large to fit in AL(i.e>FFh) then 8086 automatically
execute a type 0 interrupt. Divide a double word by a word. i.e, when a double word is divided
by a word, the MSB of the double word must be in DX and the LSB must be in AX.AX contains
quotient and DX-16 bit remainder
Ex: DIV CL : Word in AX/ byte in CL
ii) XLAT: Translate a byte.

Quotient in AL, remainder in AH

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*The XLATB instruction is used to translate a byte from one code to another code.
*The instruction replaces a byte in the AL register with a byte pointed to BX in a lookup table in
Memory.

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*Before the XLATB executed, the lookup table containing the values for the new code must be
put in memory & the offset of the starting address of the lookup table is loaded in BX.

*The code byte translated is put in AL.


AL+BX=AL

Add the AL to offset (BX) this byte is translated to AL register.


Ex: MOV AL, code Initialise AL with the code to be converted.
MOV BX, 2400h Initialise BX with the offset of lookup.

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10CS45

XLAT Replace AL with HEX equivalent of number=AL=BX+AL


iii) AAA: ASCII Adjust for Addition

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Numerical data coming into a computer from a terminal is usually in ASCII code. In this code,
the numbers 0 to 9 are represented by the ASCII codes 30h to 39h. The 8086 allows you to add
the ASCII codes for two decimal digits without marking off the 3 in the upper nibble of each.
The addition of two one digit ASCII coded nos will not result an useful data. AAA instruction is
to executed after the addition so that we get unpack BCD result.
Ex: ADD AL, BL: result: AL=0110 1110=6EH, which is incorrect BCD.

AAA: now AL=00000100, unpacked BCD 4 CF=1 indicates answer is 14 decimal.

The AAA instruction works only on the AL register. The AAA instruction updates AF and CF
but OF, PF, SF and ZF are left undefined.
iv) XCHG: Exchange instruction

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Syntax: XCHG destination, source

Here the contents of source and destination are exchanged both the operands can be registers but
not memory locations.
Ex: XCHG BX, CX
XCHG AX, DX

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XCHG BX, 1234H[BX+SI]


EA=1234H+BX+SI
PA=BA*10h+EA

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4.a. Write and explain instruction template for MOV instruction. Also generate opcode for
following instructions: the opcode for MOV is
Jan 2015 [15 Marks]

1 0 0 0 1 0

i)

MOV CL,[BX]

ii)

MOV CS,[BX],DL

iii)

MOV 43H[SI[,DH

iv)

MOV CX,[437A]H

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(10marks)

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10CS45

Ans:
(a) Instruction Templates
All instruction have its own hexadecimal codes it is available in one page chart.

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Suppose consider MOV CX,source

There fore 24+8=32

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Source ->can be anyone of eight 16- bit regiters or anyone of memory location specified by (24
memory addressing modes).

Each of 32 possible instrutions requires a different binary codes.


If mov destination, CX
Here also 32 ways of specifications destination.

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Therefore a mov has 64 different binary codes.


If CX IS ch-64 codes, CX is CL- codes-> 128 codes.

There is large number of possible codes for the 8086 instruction it is not possible to list all in a
simple table.

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Therefore we use template.

(b) Mov instruction coding format and examples:


Above figure shows the coding template or format for 8086 mov instruction.

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Which moves data from


A register to register
A simple register to a memory location.

mov reg,reg
mov reg,memory
mov memory,reg

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That is

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A memory location to a register,

The upper 6 bits of the first byte are an opcode which indicates the general type of instruction.
The D bit in the first byte of the instruction is used to indicate whether the data is movad
from the register on to the register.

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If D=0 data is moving from register.


D=1 data is moving to the register.

W bit is used to indicate whether a byte/ word is being moved.


If W=0 byte movement.
If W=1

word movement.

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In mov instruction, one operand must always be a register(reg). so 3-bits in the second
byte are (reg) used tp indicate which register is involved.
code

W=1

W=0

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Register

AX

000

BX

011

CL

CX

001

DL

DX

010

AH

SP

AL

BL

BH
CH

D1
BP

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100
111
101

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110

SEG.REG

CODE

CS

01

DS

11

ES

00

SS

10

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S1

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DH

10CS45

Remember that in a mov instruction one operand must be a register other than one is may be a
register/ member location.

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The 2-bit field labled MOD is used to specify the addressing mode.

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The 3-bit field labeled R/M is used as pattern for each of the 32 possible addressing modes.

If both operands in the mov instrction are registers then mod=11,

R/m -> put the 3-bit code for the other reg.

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If the other operand is a memory location, then effective address( offset reg) can be
specified directly in the instruction.
It can be a reg or sem of 2 reg and a displacement.

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MOD-> used to specify address specification.


R/M-> indicate reg(0) contain part of the EA.

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If EA contains no displacement like mov cx,[bx].


Then make MOD=00

R/m=choose the R/m bits which corresponds to the registers containing the EA.
Here R/m =111.
i)

Mov CL,[BX]

opcode
100010

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mov reg,memory
W MOD
00

8A0FH

REG

001

R/m

111

To find 6-bit opcode refer chart.(appendix a)

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Make D=1 because data is moving to register CL


Make w=0 because 8-bit is moving

Find 3-bit code for the register CL and replace it in REG field, ie 001.

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Find the box containing desired addressing mode.

Here [BX], read mod-bit pattern from the top of the column. Here MOD=00.

Then read R/m bit pattern from left of the box.

Here R/m=111.
Assemble all these bits in the mov temolate to genarate binary code for mov CL,[BX]

ie. 100010 10

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0000

1111

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ii)

10CS45

Mov cs:[BX],DL

This copies a byte from the DL register to a memory location EA=[BX] and PA= DS*10h+BX
(normally this happens).

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In this instruction
PA=CS*10h+BX.

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Here CS: is called segment override prefix.

When an instruction containing segment override prefix is coded, an 8 bit code for the
segment override prefix is put in memory before the code for rest of the instruction.
The code byte for the segment override prefix is 001xx110.

Insert 2 bit code in place of xs to indicate which segment base you want the EA to be added to.
ES=00
MOV CS:[BX],DL

ud
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ts

CS=01
SS=10

segment override prefix becomes 00101110

DS=11
Sop
00101110

CS

IP

SP,BP
D1

ES

BX,S1,D1

.c

DS
SS

offset reg

ity
st

Segment reg

1000100000010111

iii)mov 43h[SI],DH
100010 0

110

100

D= to mem from reg =0

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10CS45

W=0 byte data


Mod=01 because 8-bit displacent is there
REG=DH=110

om

LSB= 8 bit displacement value = 43H.


That is 887443h

PUBLIC ii) PROC iii) MACRO

iv) DB

gr
ou
p.
c

4.b. what is an assembler directive? Explain the following assembler directive with
example:
Jan 2015 [10 Marks]

Ans: assembler directive: which are translated to machine code by the assembler.

PUBLIC- indicates that the given segment will be combined with other segment
which have the same name..

Ex: DATA SEGMENT

ud
en
ts

i)

---------- ; program data definition here


---------DATA ENDS

ity
st

CODE SEGMENT
----------------------

.c

---------------------- ; PROGRAM CODE HERE

----------------------

ii)

CODE ENDS

PROC:

The directive PROC indicates the bebginning of a procedure. The directive PROC follows the
name of a procedure.

Type of procedure

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10CS45

(1) Near
(2) Far
General form

om

ProcedureName PROC [NEAR/FAR]

(a) HEX2ASC PROC NEAR

gr
ou
p.
c

Ex:

The above statement defines the procedure HEX2ASC as neas type. It can only be called within
a segment.
iii)

MACRO:

General form:

ud
en
ts

The directive MACRO informs the assembler the begining of a macro. It consists of the name of
a macro followed by the keyword MACRO and the macro arguments if any.

Macroname MACRO [Argument1,--------------,ArgumentN]


Ex: printstring MACRO msg
Mov dh,09h

Int 21h

iv)

.c

ENDM

ity
st

Mov dx, offset msg

DB:

It is used to define a byte type variable, it can be used to definr a single or multiple byte
variables. Range of values 0-255 for unsigned numbers. -128 127 for signed numbers.

General form:
Name of variable DB initialization value(,s)
Ex: TOTAL DB 0
The above statement informs the sassembler to resreve one byte of memory for a variable named
TOTAL and initialize with value zero during execution of the program.

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10CS45

5.a Explain with an example why and how a 20 bit address is generated in 8086

June 2014[05 marks]

gr
ou
p.
c

om

The 80386 provides a one Mbyte + 64 Kbyte memory space for an 8086 program. Segment relocation is
performed as in the 8086: the 16-bit value in a segment selector is shifted left by four bits to form the
base address of a segment. The effective address is extended with four high order zeros and added to
the base to form a linear address as Figure 14-1 illustrates. (The linear address is equivalent to the
physical address, because paging is not used in real-address mode.) Unlike the 8086, the resulting linear
address may have up to 21 significant bits. There is a possibility of a carry when the base address is
added to the effective address. On the 8086, the carried bit is truncated, whereas on the 80386 the
carried bit is stored in bit position 20 of the linear address.

ity
st

ud
en
ts

Unlike the 8086 and 80286, 32-bit effective addresses can be generated (via the address-size
prefix); however, the value of a 32-bit address may not exceed 65535 without causing an
exception. For full compatibility with 80286 real-address mode, pseudo-protection faults
(interrupt 12 or 13 with no error code) occur if an effective address is generated outside the range
0 through 65535.

.c

5.b Explain any five addressing modes in detail with examples in 8086

June 2014[10 marks]

8086 ADDRESSING MODES

A. Immediate addressing mode:

In this mode, 8 or 16 bit data can be specified as part of the instruction.


OP Code Immediate Operand
Example 1 : MOV CL, 03 H
Moves the 8 bit data 03 H into CL

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Register addressing mode :


The operand to be accessed is specified as residing in an internal register of 8086. Fig. below shows
internal registers, any one can be used as a source or destination operand, however only the data registers
can be accessed as either a byte or word.

om

Direct addressing mode :

Register indirect addressing mode :

gr
ou
p.
c

The instruction Opcode is followed by an affective address, this effective address is directly used as the
16 bit offset of the storage location of the operand from the location specified by the current value in the
selected segment register.

The EA is specified in either pointer (BX) register or an index (SI or DI) register. The 20 bit physical
address is computed using DS and EA.
Register indirect addressing mode :

ud
en
ts

The EA is specified in either pointer (BX) register or an index (SI or DI) register. The 20 bit physical
address is computed using DS and EA.
String addressing mode:

The string instructions automatically assume SI to point to the first byte or word of the source operand
and DI to point to the first byte or word of the destination operand. The contents of SI and DI are
automatically incremented (by clearing DF to 0 by CLD instruction) to point to the next byte or word.
I/O mode (direct) :

ity
st

Port number is an 8 bit immediate operand.


Example : OUT 05 H, AL

Outputs [AL] to 8 bit port 05 H

.c

I/O mode (indirect):

The port number is taken from DX. Example 1 : INAL, DX

5.c Explain the concept of protected mode of memory addressing

June 2014[05 marks]

PROTECTED-MODE In the protected-mode, memory larger than 1 MB can be accessed.Windows XP


operates in the protected mode. In addition, segments can be of variable size (below or above 64 KB).
Some system control instructions are only valid in the protected mode. In protected mode, the
base:offset logical memory addressing scheme (which is used in real mode) is changed. The offset part
of the logical memory address is still used. However, when in the protected mode, the processor can work
either with 16-bit offsets (the 16-bit instruction mode) or with 32- bit offsets (the 32-bit instructionmode).

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10CS45

Unit-3

gr
ou
p.
c

om

A 32-bit offset allows segments of up to 4G bytes in length. Notice that in real-mode the only available
instruction mode is the 16-bit mode (during which accessing 32-bit registers requires the prefix 66h).
However, the segment base address calculation is different in protected mode. Instead of appending a 0 at
the end of the segment register contents to create a segment base address (which gives a 20-bit physical
address), the segment register contains a selector that selects a descriptor from a descriptor table. The
descriptor describes the memory segment's location,length, and access rights. This is similar to selecting
one card from a deck of cards in one's pocket. Because the segment register and offset address still
create a logical memory address, protected mode instructions are the same as real mode instructions. In
fact, most programs written to function in the real mode will function without change in the protected
mode.

1. a. Write an ALP using 8086 instructions to search a number placed in location NUM,in
an array of ten numbers placed at location ARRAY.
June/July 13 [8 marks]

.c

ity
st

ud
en
ts

.model small ; initialize memory model


.data ; definition of Data Segment
array dw 1122H,2345H,3344H,4455H,5566H ; Ten bytes
len dw ($ -array)/2 ; Count no. of bytes & convert to dw
NUM EQU 2345H ; initialize the key element
sucmsg db Element found at position:
result DB? , cr, lf,$
failmsg db Element not found , cr, lf, $
.code ; definition of Code Segment
mov ax, @data ; initialization of Data Segment
mov ds, ax
mov bx, 1 ; least search min no. of elements in list
mov dx, len ; max no. of elements in list
mov cx, NUM ; initialize the key element to CX
again: cmp bx, dx ; if lower bound>upper bound then exit
ja failure ; jump to FAILURE if the value is above
mov ax, bx ; to find the mid element
add ax, dx ; mid = low + high
shr ax, 1 ; mid/2, shift right each bit
mov si, ax ; Formula 2(AX-1) gives actual index of mid.

dec si
add si, si
cmp cx, array [si] ; CX>=ARRAY[SI]
jae bigger ; jump to BIGGER if value is above or equal
dec ax ; subtracts 1 from the destination AX, high = mid-1
mov dx, ax
jmp again
bigger: je success ; jump to SUCCESS if the value is equal

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10CS45

gr
ou
p.
c

inc ax ; low = mid+1, adds 1 to the destination AX


mov bx, ax ; make number just above the mid as lower bound.
jmp again ; jump to label AGAIN
success: add al, 0 ; ASCII code for display on CRT, 0 - 30H
mov result, al ; copy the contents of AL to Variable RESULT
lea dx, sucmsg
jmp display ; jump to label DISPLAY
failure: lea dx, FAILMSG ; loads the effective address of FAILMSG to DX
display: mov ah, 09h ; displays the string on output device
int 21h
mov ah, 4ch ; terminates the process and exit to DOS
int 21h ; transfer to DOS by interrupt 21H
end ; end statement of the program

1.b. describe the following instructions with an example:


LEA
XCHG
DAA
MUL

June/July 13 [8 marks]

ud
en
ts

a)
b)
c)
d)

om

MICROPROCESSORS

LEA

SYNTAX: LEA REGISTER, SOURCE

The LEA instruction loads a 16- or 32-bit register with the offset address of the data
specified by the operand(source).
As the first example in Table shows, the operand address NUMB is loaded into register
AX, not the contents of address NUMB.

ity
st

XCHG

The XCHG (exchange) instruction exchanges the contents of a register with the contents
of any other register or memory location.
The XCHG instruction cannot exchange segment register or memory-to-memory data.
Exchanges are byte-, word-, or double word-sized (80386 and above)
Table shows some examples of the XCHG instruction.
XCHG AL,[DI] instruction is Identical to the XCHG [DI],AL LAHF and SAHF

.c

MUL

Multiplication is performed on bytes, words, or doublewords, and can be signed integer


(IMUL) or unsigned integer (MUL). Note that only the 80386 through the Core2
processors multiply 32-b it doublewords. The product after a multiplication is always a
double-width product. If two 8-bit numbers are multiplied, they generate a 16-bit product;
if two 16-bit numbers are multiplied, they generate a 32-bit product; and if two 32-bit

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10CS45

numbers are multiplied, a 64-bit product is generated. In the 64-bit mode of the Pentium
4, two 64-bit numbers are multiplied to generate a 128-bit product.
1.c. Give the state of all the status flags bits after the addition of 30a2 with f01ch.

gr
ou
p.
c

om

June/July 13 [8 marks]

2.a. Write and explain machine code for instruction MOV DL,[BX]

ity
st

ud
en
ts

Dec 13/Jan 14 [10 marks]

2.b. Describe the operation of each of the following instruction in brief.


Dec 13/Jan 14 [5 marks]

PUSHF

LAHF DIV XCHG

.c

PUSHF MOVS

This exists in all mps.


The PUSHF (push flags) instruction copies the contents of the flag register to the stack.
The PUSHAD and POPAD instructions push and pop the contents of the 32-bit register
set found in the 80386 through the Pentium 4. The PUSHA and POPA instructions do not
function in the 64-bit mode of operation for the Pentium 4.

MOVS

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One of the more useful string data transfer instructions is MOVS, because it transfers
data from one memory location to another.
This is the only memory-to-memory transfer allowed in the 8086 Pentium 4
microprocessors.
The MOVS instruction transfers a byte, word, or double word from the data segment
location addressed by SI to the extra segment location addressed by DI.
As with the other string instructions, the pointers then are incremented or decremented, as
dictated by the direction flag.

om

10CS45

gr
ou
p.
c

LAHF

The LAHF instruction transfers the rightmost 8 bit s of the flag register into the AH register.
The SAHF instruction transfers the AH register into the rightmost 8 bits of the flag register.
Div

As with multiplication, division occurs on 8- or 1-bit numbers in the 8086 80286


microprocssors, and on 32-bit numbers in the 80386 and above microprocessor. These
numbers are signed (IDIV) or unsigned (DIV) integers. The dividend is always a doublewidth dividend that is divided by the operand. This means that an 8-bit division divides a
16-bit number by an 8-bit number; a 16-bit division divides a 32-bit number by a 16-bit
number; and a 32-bit division divides a 64-bit number by a 32-bit number. There is no
immediate division instruction available to any microprocessor. In the 64-bit mode of the
Pentium 4 and Core2, a 64-bit division divides a 128-bit number by a 64-bit number.

ud
en
ts

XCHG

ity
st

The XCHG (exchange) instruction exchanges the contents of a register with the contents
of any other register or memory location.
The XCHG instruction cannot exchange segment register or memory-to-memory data.
Exchanges are byte-, word-, or double word-sized (80386 and above)
Table shows some examples of the XCHG instruction.
XCHG AL,[DI] instruction is Identical to the XCHG [DI],AL LAHF and SAHF

.c

Dec 13/Jan 14 [5 marks]

2.c. what is segment override prefix? Illustrate the same with an example.

The segment override prefix, which may be added to almost any instruction in any memory

addressing mode, allows the programmer to deviate from the default segment. The segment
override prefix is an additional byte that appends the front of an instruction to select an alternate
segment register. About the only instructions that cannot be prefixed are the jump and call
instructions that must use the code segment register for address generation. The segment override

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10CS45

is also used to select the FS and as segments in the 80386 through the Pentium Pro
microprocessors. For example, the MOV AX,[DI] instruction accesses data within the data
segment by default. If required by a program, this can be changed by prefixing the instruction.

addresses the extra segment if changed to MOV AX,ES:[DI].

Syntax: Procedure fact_proc


. model small
.data
n dw 4

MOV AX, @data


MOV DS, AX

jz last
MOV AX, n

Dec BX

Call fact

.c

MOV BX, AX

ity
st

cmp n,0

ud
en
ts

res dw 1
.code

Dec 2012 [10 marks]

gr
ou
p.
c

3.a. Write an ALP to find factorial of a number using recursion.

om

Suppose that the data are in the extra segment instead of the data segment. This instruction

MOV res, AX

Last: MOV AH, 4CH


Int 21h

Fact proc
Cmp BX, 1

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10CS45

Jz next
Mul BX
Dec BX

om

Cal fact

Fact endp
End

gr
ou
p.
c

Next: ret

3.b. Explain the types of program execution transfer instruction (Branch instructions) with
examples.
Dec 2012 [10 marks]
A branch instruction transfer control from the normal sequence of instruction execution to the
specified destination/ target instruction. These instructions are broadly classified into two groups:

ud
en
ts

*Unconditional branch instruction


*Conditional branch instruction

The Unconditional branch instructions transfer control to the target location. The target operand
may be specified in the instruction itself.The conditional branch instructions transfer control to
the target location if some specified condition is met (or) satisfied.

ity
st

Ex: JA, JB, JE, etc.


a)Unconditional jump(Jmp):

3 types of unconditional jump instructions are:

.c

*Short jump(2 bytes +127 to -127)

*Near jump anywhere in current segment


*Far jump anywhere within real memory system.

*Short jump: It is a two bytes instruction which allows jumps to memory location within +127 to
-127 bytes from the address following the jump.
This jump is also called as relative jumps. The target address is computed by adding IP & the
sign extended displacement.
Jmp instruction:

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10CS45

Syntax: Jmp target; unconditional transfer of control to the label.


Short: IP-(IP+ target displacement sign extended)
Near: IP-( IP+ target displacement)

om

Indirect: IP-(relative or value in memory)

IP-(target-offset)

gr
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p.
c

Far: CS-target segment

The instruction jmp unconditionally transfer control to the target location.


2 different forms of jmp are:
*Intra segment jumps:(near & short jumps)

*Short jump:
Syntax: Jmp short label
Ex: JMP SHORT NEXT1
*Near Jump:

ity
st

Syntax: Jmp NeAr LABEL

ud
en
ts

If the target I in the same code segment as the instruction jump if requires only the IP to be
changed to transfer the target location such as jump is called Intra segment jumps.

Ex: Jmp NEAR PTR NEXT1

.c

Near Jumps: It allows a branch within +_32 kb anywhere in the correct code segment. i. e the
target can be anywhere in the correct code segment. The target address is computed by adding
IP+ displacement specified in the instruction.

Indirect Near Jmp:

Target=register(or) memory content specified in the instruction.

Far jump:
It allows a jump to any memory location within the real memory system. So near and short jump
called intra segment jump & far jump called inter segment jump.
Inter Segment Jumps:

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10CS45

This instruction transfer control to the target in a different code segment. This is performed by
loading CS with segment no in which target exists & IP with offset address of the instruction to
which control transforms into the new code segment.

om

Ex: jmp FAR PTR SKIP


Indirect far jump:

gr
ou
p.
c

This transfer control to different CS. It is performed by loading IP & CS with four consecutive
memory locations. The new value for IP is in the 1st two memory locations & the new value of
CS is in the next two memory locations.
Ex: Jmp DWORD PTR [SI]
b)Conditional jumps and sets:

*These Jumps are always short jumps in the 8086/80186,80286 near jumps in 80386 & above.

ud
en
ts

*the conditional jump instructions tests the following flag bits Sign(S), Carry(C), Parity(P) &
Overfiow(O).
*If the condition under test is true, then branch occurs to the specified label
*If the condition is false, the next instruction is sequentially taken &executes.
*The operation of most conditional jump instructions is used after compare (or) subtraction
Instructions.

ity
st

It can be magnitude comparisions- JA, JB, JC


(or) sign bit comparision= JG, JL, JGE, JE

.c

Figure 5-4 Format of the XLAT instruction

4.a. What is the need for unconditional jump instructions, explain different conditional
jump supported by 8086.
Jan 2015 [10 marks]

JMP: Unconditional Jump

This instruction unconditionally transfers the control of execution to the specified


address using an 8-bit or 16-bit displacement. No Flags are affected by this instruction.
JZ/JE Label
Transfer execution control to address Label, if ZF=1.

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10CS45

JNZ/JNE Label
Transfer execution control to address Label, if ZF=0
JS Label

om

Transfer execution control to address Label, if SF=1.

Transfer execution control to address Label, if SF=0.


JO Label
Transfer execution control to address Label, if OF=1.
14
JNO Label

ud
en
ts

Transfer execution control to address Label, if OF=0.

gr
ou
p.
c

JNS Label

JNP Label

Transfer execution control to address Label, if PF=0.


JP Label

JB Label

ity
st

Transfer execution control to address Label, if PF=1.

Transfer execution control to address Label, if CF=1.


JNB Label

.c

Transfer execution control to address Label, if CF=0.

JCXZ Label

Transfer execution control to address Label, if CX=0


Jan 2015 [10 Marks]

4.b. Write a delay loop, which produces a delay of 5 clock.

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10CS45

ud
en
ts

gr
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p.
c

om

MICROPROCESSORS

5.a Write 8086 ALP to add 10 non-negative data items using string instructions.

June 2014[06 marks]

ity
st

.model small
.stack 100h
.data
str1 db 'Enter String ','$'
str2 db 50 dup('$')
str3 db 0dh, 0ah, '$'
.code

.c

main proc
mov ax,@data
mov ds,ax

; for displaying Enter String

mov ah,09h
lea dx,str1
int 21h
mov ah,0ah
lea dx,str2
int 21h

; for taking i/p from keyboard

mov ah,09h ; for displaying in new line


lea dx,str3

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MICROPROCESSORS

10CS45

int 21h
mov ah,09h
lea dx,str2+2
int 21h

; for displaying what you have entered

om

int 21h
mov ah,4ch
int 21h
main endp

5.b Explain the following instruction with examples


CMP

LAMF

XCHG

LEA

PUSH AX

LEA
SYNTAX: LEA REGISTER, SOURCE

The LEA instruction loads a 16- or 32-bit register with the offset address of the data specified by
the operand(source).
As the first example in Table shows, the operand address NUMB is loaded into register AX, not
the contents of address NUMB.

XCHG

The XCHG (exchange) instruction exchanges the contents of a register with the contents of any
other register or memory location.
The XCHG instruction cannot exchange segment register or memory-to-memory data.
Exchanges are byte-, word-, or double word-sized (80386 and above)
Table shows some examples of the XCHG instruction.
XCHG AL,[DI] instruction is Identical to the XCHG [DI],AL LAHF and SAHF
Compare.

ity
st

LDS DI,[3000h] June 2014[06 marks]

ud
en
ts

gr
ou
p.
c

end main

.c

Algorithm:

operand1 - operand2

result is not stored anywhere, flags are set (OF, SF, ZF, AF, PF, CF) according to result.

C Z S

Example:
MOV AL, 5
MOV BL, 5
CMP AL, BL ; AL = 5, ZF = 1 (so equal!)
RET
O P A

r r r r r r

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10CS45

LAHF No operands Load AH from 8 low bits of Flags register.


Algorithm:

om

AH = flags register

gr
ou
p.
c

AH bit: 7 6 5 4 3 2 1 0
[SF] [ZF] [0] [AF] [0] [PF] [1] [CF]
bits 1, 3, 5 are reserved.
C Z S O P A

unchanged
LDS REG, memory Load memory double word into word register and DS.
Algorithm:

ud
en
ts

REG = first word


DS = second word
Example:
#make_COM#
ORG 100h
LDS AX, m

m DW 1234h
DW 5678h
END

ity
st

RET

.c

AX is set to 1234h, DS is set to 5678h.


C Z S O P A

unchanged
Note: PUSH immediate works only on 80186 CPU and later!

Algorithm:
SP = SP - 2
SS:[SP] (top of the stack) = operand

Example:
MOV AX, 1234h
PUSH AX

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MICROPROCESSORS

10CS45

POP DX ; DX = 1234h
RET
C Z S O P A

om

unchanged
PUSHA No operands Push all general purpose registers AX, CX, DX, BX, SP, BP, SI, DI in the stack.
Original value of SP register (before PUSHA) is used.
Note: this instruction works only on 80186 CPU and later!

gr
ou
p.
c

Algorithm:
PUSH AX
PUSH CX
PUSH DX
PUSH BX
PUSH SP
PUSH BP
PUSH SI
PUSH DI
C Z S O P A

ud
en
ts

unchanged

5.c Explain with example the following assembler directives(any four)


ORG

DQ

PROC ENDP TYPE EVEN

June 2014[08 marks]

ity
st

DQ: Define Quadword: This directive is used to direct the assembler to reserve 4 words (8bytes) of
memory for the specified variable and may initialize it with the specified values
END: END Of Program: The END directive marks the end of an assembly language program.
ENDP: END Of Procedure: The ENDP directive is used to indicate the end of a procedure.

.c

EVEN: Align On Even Memory Address: The EVEN directive updates the location counter to the next
even address, if the current location counter contents are not even, and assigns the following routine or
variable or constant to that address. If the content of the location counter is already even, then the
procedure will be assigned with the same address.

ORG: Origin: The ORG directive directs the assembler to start the memory allotment for the particular
segment, block or code from the declared address in the ORG statement

.PROC: Procedure: The PROC directive marks the start of a named procedure in the statement. Also the
types FAR and NEAR specifies the type of the procedure.
TYPE: The TYPE operator directs the assembler to decide the data type of the specified label and
replaces the TYPE label by the decided data type.

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10CS45

Unit-4
1.a. Explain the following assembler directives with examples. June/July 13[8 marks]
i) DB

ii)EXTRN iii) PROC

iv) SEGMENT

.c

ity
st

ud
en
ts

gr
ou
p.
c

om

i) The following are some of the data directives used to define different types of
variables used in the data segment:
DB
Define Byte[8 bit integer]
DW Define Word [16-bit signed integer
DD
Define Double Word [32-bit signed integer or real number]
DQ
Define Quad Word [64-bit signed integer or real number]
ii) Is used to tell assembler that the name or labels following the directive are in some other
assembly module.
For Eg, if a procedure is called which is in a program module assembled at
different time, assembler must know that the procedure is external.
The assembler will then put information in the object code file so that the linker
can connect the two modules together.
For a reference to the external named variable, one must specify the type of the
variable Eg: EXTRN DIVISOR: WORD
For a reference it is necessary to specify whether the label is near or far.
Eg: EXTRN SMART_DIVIDE:FAR ; tells the assembler that SMART_DIVIDE
is a label of type far in another assembly module
Names and labels referred to as external in one module must be declared public
iii) PROC
Is used to identify the start of a procedure.
Proc directive follows a name given to the procedure.
After proc directive, the term near or far is used to specify the type of the
procedure.
Eg: FACT PROC NEAR
iv)SEGMENT
Is used to indicate the start of a logical segment.
Preceding the SEGMENT directive is the name of the segment given by user.

1.b. Differentiate between macros and procedures.


Procedure

Macro

June/July 13[4 mark]

RET instruction

Accessed during assembly with name given to Accessed by CALL and


macro when defined.
during program execution.

Machine code is generate for instructions each Machine code for instruction is put only once
time when macro is called
in the memory

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10CS45

With macro more memory is required

With procedure less memory is required

1.c. Write an ALP using 8086 instructions to reverse a four digit number

om

Parameter passed as part of statement which Parameters can be passed in registers memory
call macros
locations are stack.

gr
ou
p.
c

June/July 13[8 marks]


.MODEL SMALL
.DATA
STR DB 1234 $
STRLEN DW ($-STR-1)
REVSTR DB 40 DUP(?)
MSG1 DB THE STRING IS A PALINDROME, $
MSG2 DB THE STRING IS NOT A PALINDROME, $
.CODE

.c

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ud
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ts

MOV AX, @DATA ; initialization of Data Segment


MOV DS, AX
MOV ES, AX ; initialization of Extra Segment
MOV CX, STRLEN ; initialization of length of the String
LEA SI, STR ; load the EA of STR to the SI register
LEA DI, REVSTR ; load the EA of REVSTR to the DI register
ADD DI, CX ; points to the last character in DI register
DEC DI ; decrements the DI, to fill characters leaving the $
BACK: MOV AL, [SI] ; bytes in location of SI is copied to AL
MOV [DI], AL ; AL is copied to the location in DI
INC SI ; increments the SI pointer i.e. entered string byte
DEC DI ; decrements the DI pointer i.e. reversed string byte
LOOP BACK ; continues the same process until CX register is zero
MOV CX, STRLEN ; initialize all the data operands again to compare
LEA DI, REVSTR
LEA SI, STR
CLD ; clear Direction Flag, auto increments the pointer registers SI & DI
REPE CMPSB ; Compare string bytes if equal, then repeat the comparison
JCXZ SUCCESS ; jump to success if CX = 0
LEA DX, MSG2 ; loads the EA of operand msg2 to the DX register
MOV AH, 09H ; displays the string, function call of DOS interrupt 21H
INT 21H ; transfer to DOS, interrupts the process to execute the function
JMP EXIT ; jump to label EXIT

SUCCESS: LEA DX, MSG1 ; loads the EA of operand msg1 to the DX register
MOV AH, 09H
INT 21H
EXIT: MOV AH, 4CH ; exit to DOS function, terminate the process

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10CS45

INT 21H
END ; end of the program

2.a. Explain with an example how multiple if then else statement can be implemented using
ALP
Dec 13/Jan 14[10 marks]

om

The IF and ENDIF statements allow portions of the program to assemble if some condition is
met. Otherwise, the statements between IF and ENDIF do not assemble. shows how the IF,

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ou
p.
c

ELSE, and ENDIF statement are used to conditionally assemble values for the width and length
of paper in a program. Note that TRUE and FALSE are defined as 1 and O. This is important

because these values are not predefined by the assembler. Next, the width and length of the paper
are adjusted by using TRUE and FALSE statements. This can be expanded to ask an entire series

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of questions about a program so custom versions can be created.

2.b. Differentiate between short, near and far jump instructions with two examples of each
Dec 13/Jan 14 [10 marks]

.c

Short Jump. Short jumps are called relative jumps because they can be moved, along with their
related software, to any location in current code segment without a change. This is because the

jump address is not stored with the opcode. Instead of a jump address, a distance or displacement

follows the opcode. The short jump displacement is a distance represented by a I-byte signed
number whose value ranges between +127 and -128

Near Jump. The near jump is similar to the short jump except that the distance is farther. A near
jUl11jJ passes control to an instruction in the current code segment located within 32K bytes
from the near jump instruction or 2G in the 80386 and above operated in protected mode. The
near jump is a 3-byte instruction that contains an opcode followed by a signed 16-bit displacernc

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10CS45

rt. In the 80386 through the Pentium Pro processors, the displacement is 32-bits and the near is 5
bytes long. The signed displacement adds to the instruction pointer (IP) to generate the jump
address. Because the signed displacement is in the range of 32K

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Far Jump. A far jump instruction (see Figure 6-4) obtains a new segment and offset address to
accomplish the jump. Bytes 2 and 3 of this 5-byte instruction contain the new offset address, and
bytes 4 and 5 contain the new segment address.

Dec 2012 [5 Marks]

gr
ou
p.
c

3.a. Differentiate between macros and procedures.


Ans:
Macro

Procedure

Accessed during assembly with name given to Accessed by CALL and


macro when defined.
during program execution.

RET instruction

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ts

Machine code is generate for instructions each Machine code for instruction is put only once
time when macro is called
in the memory
With macro more memory is required

With procedure less memory is required

Parameter passed as part of statement which Parameters can be passed in registers memory
call macros
locations are stack.

Dec 2012 [5 Marks]

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3.b. Explain REP MOVSB instruction with example.

.c

REP is a prefix which is written before one the string instructions. It will cause the CX register to
be determined and the string instruction to be repeated until CX=0. The instruction REP MOCSB
, for example will continue to copy string bytes until the number of bytes loaded into CX has
been copoed.

3.c. Explain the sequence of operation that takes place when a procedure is called and
returned form procedure base to calling program with block diagram.

Dec 2012 [10 Marks]

Ans:

Main Program
:

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10CS45
:

SP after CALL Compute

IP

PUSH Var1
Var2

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PUSH Var2
Var1
SP before PUSH Var1

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p.
c

CALL Compute
:

COMPUTE

Subroutine
PROC
:

IP
Var2

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RET 0004H

SP if RET 0004H is executed

ENDP

.c

COMPUTE

Near

SP if RET is executed

:
Var1

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4.a. Write an assembly level program to cheek a given string is palindrome or not.

Jan 2015 [12 Marks]

.MODEL SMALL
.DATA
STR DB 'MALAYALAM$'
STRLEN DW ($-STR-1)

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REVSTR DB 40 DUP (?)


MSG1 DB 'THE STRING IS PALINDROME','$'
MSG2 DB 'THE STRING IS NOT A PALINDROME','$'

om

.CODE
MOV AX,@DATA

gr
ou
p.
c

MOV DS,AX
MOV ES,AX
MOV CX,STRLEN
LEA SI,STR
LEA DI,REVSTR

DEC DI
BACK:MOV AL,[SI]
MOV [DI],AL

DEC DI
LOOP BACK

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INC SI

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ts

ADD DI,CX

MOV CX,STRLEN

.c

LEA DI,REVSTR

LEA SI,STR

CLD

REPE CMPSB
JCXZ SUCCESS
LEA DX,MSG2
MOV AH,09H

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INT 21H
JMP EXIT
SUCCESS:LEA DX,MSG1

om

MOV AH,09H
INT 21H

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p.
c

EXIT:MOV AH,4CH
INT 21H
END

4.b. Define and differentiate between reentrant and recursive procedures.

Re Entrant Procedure:

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Jan 2015 [8 Marks]

1. A Portion of the code that can be called by a procedure while another if


already executing it is called reentrant.

2.Reentrant code can be shared between different users.

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3.It must be pure code and not contain data.

4.The data for reentrant procedures is normally laced on the stack.


Recursive Procedure:

.c

1. It calls a procedure by itself.

2. It can not shared between two different users

3. data can be passed to the procedure.

4. no need to store the data on to the stack.


Ex:fact program using recursive procedure.
5.a Explain the various string manipulation instructions with example June 2014[06 marks]

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10CS45

x86 assembly language is a family of backward-compatible assembly languages, which provide some
level of compatibility all the way back to the Intel 8008. x86 assembly languages are used to produce
object code for the x86 class of processors. Like all assembly languages, it uses short mnemonics to
represent the fundamental instructions that the CPU in a computer can understand and follow. Compilers

om

sometimes produce assembly code as an intermediate step when translating a high level program into

machine code. Regarded as a programming language, assembly coding is machine-specific and low level.

Assembly languages are more typically used for detailed and time critical applications such as small real-

gr
ou
p.
c

time embedded systems or operating system kernels and device drivers.

Data swap
Exchange.

The xchg instruction swaps the src operand with the dest operand. It's like doing three move
operations: from dest to a temporary (another register), then from src to dest, then from the temporary to
src, except that no register needs to be reserved for temporary storage.

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ts

If one of the operands is a memory address, then the operation has an implicit LOCK prefix, that is, the
exchange operation is atomic. This can have a large performance penalty.
It's also worth noting that the common NOP (no op) instruction, 0x90, is the opcode for
xchgl %eax, %eax.
Compare and exchange.

The cmpxchg instruction has two implicit operands AL/AX/EAX(depending on the size of arg1) and

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ZF(zero) flag. The instruction compares arg1 to AL/AX/EAX and if they are equal sets arg1 to arg2
and sets the zero flag otherwise it sets AL/AX/EAX to arg1 and clears the zero flag. Unlike xchg there
is not an implicit lock prefix and if the instruction is required to be atomic then lock must be prefixed.
Move sign extend.

.c

The movs instruction copies the src operand in the dest operand and pads the remaining bits not

provided by src with the sign bit (the MSB) of src.


This instruction is useful for copying a signed small value to a bigger register.

Move byte

The movsb instruction copies one byte from the memory location specified in esi to the location
specified in edi. If the direction flag is cleared, then esi and edi are incremented after the operation.
Otherwise, if the direction flag is set, then the pointers are decremented. In that case the copy would
happen in the reverse direction, starting at the highest address and moving toward lower addresses until
ecx is zero.

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10CS45

5.b Explain the the following instruction with examples any four

June 2014[08

marks]
RCL

Decimal adjust After Addition.


Corrects the result of addition of two packed BCD values.
Algorithm:

Example:
MOV AL, 0Fh ; AL = 0Fh (15)
DAA
; AL = 15h
RET
C Z S O P A

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r r r r r r

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if low nibble of AL > 9 or AF = 1 then:


AL = AL + 6
AF = 1
if AL > 9Fh or CF = 1 then:
AL = AL + 60h
CF = 1

om

ADC SHR

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p.
c

DAA MUL

MUL REG
memory
Unsigned multiply.

.c

Algorithm:

when operand is a byte:


AX = AL * operand.
when operand is a word:
(DX AX) = AX * operand.

Example:
MOV AL, 200 ; AL = 0C8h
MOV BL, 4
MUL BL
; AX = 0320h (800)
RET
C Z S O P A
r ? ? r ? ?
CF=OF=0 when high section of the result is zero.

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10CS45

Add with Carry.

om

Algorithm:
operand1 = operand1 + operand2 + CF

gr
ou
p.
c

Example:
STC
; set CF = 1
MOV AL, 5 ; AL = 5
ADC AL, 1 ; AL = 7
RET
C Z S O P A

SHR memory, immediate


REG, immediate

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r r r r r r

memory, CL
REG, CL Shift operand1 Right. The number of shifts is set by operand2.
Algorithm:

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Shift all bits right, the bit that goes off is set to CF.
Zero bit is inserted to the left-most position.
Example:
MOV AL, 00000111b
SHR AL, 1
; AL = 00000011b, CF=1.

r r

.c

RET
C O

OF=0 if first operand keeps original sign. STC No operands Set Carry flag.

RCL memory, immediate


REG, immediate
memory, CL
REG, CL Rotate operand1 left through Carry Flag. The number of rotates is set by operand2.
When immediate is greater then 1, assembler generates several RCL xx, 1 instructions because 8086 has
machine code only for this instruction (the same principle works for all other shift/rotate instructions).
Algorithm:

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10CS45

shift all bits left, the bit that goes off is set to CF and previous value of CF is inserted to the right-most
position.

OF=0 if first operand keeps original sign.

gr
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p.
c

r r

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Example:
STC
; set carry (CF=1).
MOV AL, 1Ch
; AL = 00011100b
RCL AL, 1
; AL = 00111001b, CF=0.
RET
C O

5.c Explain the different types of jump and cell instructions of 8086
program flow control

June 2014[06 marks]

unconditional jumps

ud
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controlling the program flow is a very important thing, this is where your program can make decisions
according to certain conditions.

The basic instruction that transfers control to another point in the program is JMP.
The basic syntax of JMP instruction:
JMP label

.c

label1:
label2:
a:

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To declare a label in your program, just type its name and add ":" to the end, label can be any
character combination but it cannot start with a number, for example here are 3 legal label
definitions:

Label can be declared on a separate line or before any other instruction, for example:

x1:
MOV AX, 1
x2: MOV AX, 2
here's an example of JMP instruction:
org 100h

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10CS45

mov ax, 5
mov bx, 2

; set ax to 5.
; set bx to 2.
; go to 'calc'.

back: jmp stop


calc:
add ax, bx
jmp back

; go to 'stop'.

; return to operating system.

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c

; add bx to ax.
; go 'back'.

stop:
ret

om

jmp calc

Short Conditional Jumps

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Of course there is an easier way to calculate the some of two numbers, but it's still a good
example of JMP instruction.
As you can see from this example JMP is able to transfer control both forward and backward. It
can jump anywhere in current code segment (65,535 bytes).

Unlike JMP instruction that does an unconditional jump, there are instructions that do a
conditional jumps (jump only when some conditions are in act). These instructions are divided in
three groups, first group just test single flag, second compares numbers as signed, and third
compares numbers as unsigned.

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Jump instructions that test single flag

Description

Condition

Opposite
Instruction

JZ , JE

Jump if Zero (Equal).

ZF = 1

JNZ, JNE

JC , JB, JNAE

Jump if Carry (Below, Not Above Equal).

CF = 1

JNC, JNB, JAE

JS

Jump if Sign.

SF = 1

JNS

JO

Jump if Overflow.

OF = 1

JNO

JPE, JP

Jump if Parity Even.

PF = 1

JPO

JNZ , JNE

Jump if Not Zero (Not Equal).

ZF = 0

JZ, JE

JNC , JNB,

Jump if Not Carry (Not Below, Above

CF = 0

JC, JB, JNAE

.c

Instruction

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MICROPROCESSORS

10CS45

Equal).

JNS

Jump if Not Sign.

SF = 0

JS

JNO

Jump if Not Overflow.

OF = 0

JO

JPO, JNP

Jump if Parity Odd (No Parity).

PF = 0

JPE, JP

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c

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JAE

as you may already notice there are some instructions that do that same thing, that's correct, they even are
assembled into the same machine code, so it's good to remember that when you compile JE instruction you will get it disassembled as: JZ, JC is assembled the same as JB etc...
different names are used to make programs easier to understand, to code and most importantly to
remember. very offset dissembler has no clue what the original instruction was look like that's why it uses
the
most
common
name.

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if you emulate this code you will see that all instructions are assembled into JNB, the operational code
(opcode) for this instruction is 73h this instruction has fixed length of two bytes, the second byte is
number of bytes to add to the IP register if the condition is true. because the instruction has only 1 byte to
keep the offset it is limited to pass control to -128 bytes back or 127 bytes forward, this value is always
signed.

.c

mov ax, 4
a: mov ax, 5
ret

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jnc a
jnb a
jae a

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10CS45

Unit-5
1.a. What is inline assembly? Explain its need.

June/July 13 [6 marks]

An assembler creates object code by translating assembly instruction mnemonics into opcodes,

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and by resolving symbolic names for memory locations and other entities. The use of symbolic
references is a key feature of assemblers, saving tedious calculations and manual address updates

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c

after program modifications. Most assemblers also include macro facilities for performing
textual substitutione.g., to generate common short sequences of instructions as inline, instead
of called subroutines.

Assemblers have been available since the 1950s and are far simpler to write than compilers for
high-level languages as each mnemonic instruction / address mode combination translates
directly into a single machine language opcode. Modern assemblers, especially for RISC

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architectures, such as SPARC or Power Architecture, as well as x86 and x86-64, optimize
instruction scheduling to exploit the CPU pipeline efficiently.

1.b. State the C language elements that can be used in the arm block.
June/July 13 [6 marks]

There are two main ways of writing ARM assembly language programs. One is to use a

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dedicated assembler. Such a program takes a text file containing ARM assembly language
instructions, assembles it, and produces another file containing the equivalent machine code.
These two files are called the source files and object files respectively.

.c

An alternative approach is to use the assembler built-in to BBC BASIC. The ability to mix

assembler with BASIC is a very useful feature of the language, and one that is relatively
straightforward to use. For this reason, and because of the widespread availability of BBC

BASIC, we describe how to use its built-in assembler. The examples of the next two chapters are

also in the format expected by the BASIC assembler.


Two special 'statements' are used to enter and exit from the assembler. The open square bracket
character, [, marks the start of assembly language source. Whenever this character is encountered
where BASIC expects to see a statement like PRINT or an assignment, BASIC stops executing

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10CS45

the program and starts to assemble ARM instructions into machine code. The end of the source is
marked by the close square bracket,]. If this is read where BASIC is expecting to see an
instruction to be assembled, it leaves assembler mode and starts executing the (BASIC) program

PRINT "Outside the assembler"


[ ;In the assembler
] PRINT "Outside the assembler"

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p.
c

To see the effect of entering and leaving the assembler, type in this short program:

om

again.

If you RUN this, you should see something like the following:
Outside the assembler

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In the assembler
Outside the assembler

Between the two lines produced by the PRINT statements is one which the assembler printed.
Unless you tell it not to, the assembler prints an assembly listing. We shall describe this in detail,
but for now suffice is to say that it consists of three parts: an address (the eight zeros above,
which may be different when you run the program), the machine code instruction in hex, and the
source instruction being assembled.

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1.c. Explain the basic rules for using assembly language with C/C++ for 16 bit DOS
applications with the help of examples
June/July 13 [8 marks]
USING ASSEMBLY LANGUAGE WITH C++ FOR 16-BIT DOS APPLICATIONS

Use software to build 16-bit applications when attempting any programs in this section.
if you build a 32-bit application and attempt the DOS INT 21H function, the
program will crash

.c

To build a 16-bit DOS application, you will need the legacy 16-bit compiler

Programs are generated using Notepad or DOS Edit.

It then displays each of the entries by using a few assembly language procedures.

The string procedure displays a character string, no carriage return/line feed combination
is displayedinstead, a space is displayed.

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10CS45

The Crlf procedure displays a carriage return/line feed combination. the Numb procedure
displays the integer

Basic Rules and Simple Programs

Before assembly language code can be placed in a C/C++ program, some rules
must be learned.

Assembly code in this example is placed in the _asm block.

Labels are used as illustrated by the label big.

Note that AX, BX, CX, DX, and ES registers are never used by Microsoft C/C++.

these might be considered scratchpad registers, available to use with assembly language

If you wish to use any of the other registers, make sure that you save them with a PUSH
before they are used and restore them with a POP afterwards.

if
you
fail
to
save
registers
used
by
the program may not function correctly and can crash the computer

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p.
c

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program,

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2.a. Illustrate a simple program that uses a character string defined with and display on a
separate line.
Dec 13/Jan 14 [10 marks]

.c

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.model small
.data
str db 80 dup (0) ; duplicate directive initializes allocated bytes with zero
msg1 db 13, 10, Entered String is: , '$' ; allocates the bytes for variable named msg1
.code
start: mov ax, @data
mov ds, ax
include mr.asm ; includes the external file macro read into main program
include md.asm ; includes the external file macro display into main program
mov si, offset str ; copies the contents at offset STR to Source Index
L1: read_byte ; calling the macro read function
mov [si], al ; copies the character read into location of SI
inc si
cmp al, 0dh ; compares the contents of AL and 13 - CR
jne l1 ; jump to L1 if value is not equal
lea dx, msg1
mov ah, 09h ; displays the string in variable MSG1
int 21h
lea si, str MICROPROCESSORS 10CS45 Dept., of ISE ,S.J.B.I.T Page 10

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2.b. Differentiate between :

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c

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L2: mov dl, [si] ; copies the characters to be written from SI to DL


mov bl, 0dh ; initialize the carriage return to BL
cmp bl, [si]
je exit ; jump to EXIT if equal
display ; calling the macro display function
inc si
jmp l2
exit: mov ah, 4ch
int 21h
end start
External file: mr.asm ; edit in a new file
read_byte macro ; defining macros with read_byte as macro name
mov ah,01h ; reads a character from the input device
int 21h
endm ; end the macros
External file: md.asm ; edit in a new file
display macro ; defining macros with display as macro name
mov ah,02h ; writes a character to the output device
int 21h
endm ; end the macros

Dec 13/Jan 14 [6 marks]

i) assembler and linker ii) public and extern iii) macros and procedure
i) assembler and linker

.c

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Assemblers
Assemblers need to
translate assembly instructions and pseudo-instructions into machine instructions
Convert decimal numbers, etc. specified by programmer into binary
Typically, assemblers make two passes over the assembly file
First pass: reads each line and records labels in a symbol table
Second pass: use info in symbol table to produce actual machine code for each line
Linker
Tool that merges the object files produced by
separate compilation or assembly and creates an executable file
Three tasks
Searches the program to find library routines used by program, e.g. printf(), math routines,
Determines the memory locations that code from each module will occupy and relocates its
instructions by adjusting absolute references
Resolves references among files
ii)public and extern
PUBLIC
Large programs are written as separate modules.
Each module is individually assembled, tested and debugged.
When all the modules are correct, their object code files are linked together to form
the complete program.

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gr
ou
p.
c

om

For the modules to link together correctly, any variable name or label referred to in
other modules must be declared public in the module where it is defined.
PUBLIC directive is used to tell the assembler that a specified name or label will
be accessed from other modules
Eg: Public sales
EXTRN directive
Is used to tell assembler that the name or labels following the directive are in some
other assembly module.
For Eg, if a procedure is called which is in a program module assembled at
different time, assembler must know that the procedure is external.
The assembler will then put information in the object code file so that the linker
can connect the two modules together.
For a reference to the external named variable, one must specify the type of the
variable Eg: EXTRN DIVISOR: WORD
For a reference it is necessary to specify whether the label is near or far.
Eg: EXTRN SMART_DIVIDE:FAR ; tells the assembler that SMART_DIVIDE
is a label of type far in another assembly module
Names and labels referred to as external in one module must be declared public.
Example
Calling Program
Called Program
DATA SEGMENT

EXTRN VAR: FAR

PUBLIC VAR

DATA SEGMENT

VAR DW

..

..

MOV AX, VAL

.c

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st

DATA ENDS

iii)macros and procedure


Macro

DATA ENDS

Procedure
RET instruction

Accessed during assembly with name given to Accessed by CALL and


macro when defined.
during program execution.

Machine code is generate for instructions each Machine code for instruction is put only once
time when macro is called
in the memory
With macro more memory is required

With procedure less memory is required

Parameter passed as part of statement which Parameters can be passed in registers memory

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10CS45

call macros

locations are stack.

om

2.c. Write an ALP to compute factorial of single digit positive number using recursive
procedure
Dec 13/Jan 14 [4 marks]
.MODEL SMALL

gr
ou
p.
c

.STACK 64H
.DATA
NUM Db 03H
RES DW?
.CODE

MOV DS,AX
MOV AX,01
MOV CX,[NUM]
CMP CX,00H

MOV BX,CX
CALL FAC

ity
st

JE EXIT

ud
en
ts

MOV AX,@DATA

.c

EXIT:MOV RES,AX

MOV AH,4CH

INT 21H

FAC PROC
CMP BX,01H
JE G
MUL BX

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MICROPROCESSORS

10CS45

DEC BX
CALL FAC
G:RET

om

FAC ENDP
END

gr
ou
p.
c

3.a. Write an ALP to find NCR using recursive procedure. Assume N & R are nonNegative numbers.
Dec 2012 [10 marks]
.model small
.data
n dw 6

ncr dw 0
.code
MOV AX, @data
MOV DS, AX

MOV BX, r
Call ncr_proc

.c

Int 3

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st

MOV AX, n

ud
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ts

r dw 2

Ncr_proc.proc

Cmp AX, BX

Jz n1

Cmp BX, 0
Jz n1
Cmp BX, 1

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MICROPROCESSORS

10CS45

Jz n2
MOV CX, BX
Dec CX

om

Cmp AX, CX
Jz n2

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c

Push AX
Push BX
Dec AX
Call ncr_proc
Pop BX

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ts

Pop AX
Dec BX
Dec AX
Call ncr_proc

N1: add ncr,1


Ret

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Jmp last

Last: ret

.c

N2: add ncr, AX

Ncr_proc endp

end

3.b. Explain the following instructions with an example:


i)
ii)
iii)

Dec 2012 [10 marks]

DAA
AAM
LOOP

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MICROPROCESSORS

iv)
v)
Ans:

10CS45

SUB
XLAT

Ex: ;AL=0101 1001=59 BCD


; BL=0011 0101=35 BCD
ADD AL,BL ;AL=1000 1110=8EH

; Add 0110 because 1110>9

ud
en
ts

DAA

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c

om

DAA: This instruction is used to make sure the result of adding two packed BCD numbers is
adjusted to be a legal BCD number. The result of the addition must be in AL for DAA nimber.
The result of the addition must be in AL for DAA to work correctly. If the lower nibble in AL
after an addition is greater than 9 or AF was set by the addtion, then the DAA instruction will
add 6 to the lower nibble in AL. if the result in the upper nibble of AL is now greater than 9 of if
the carry flag was set by the addition or correction. Then the DAA instrction will add 60H to AL.
a couple of simple examples should clarify how this works.

;AL=1001 0100=94 BCD


;AL=1000 1000=88 BCD
;BL=0100 1001=49 BCD
i)

AAM:

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The AAM instruction is used to adjust the product to two unpacked BCD digits in AX.
AAM works only after the multiplication of two unpacked BCD bytes, and it works only on an
operand in AL. AAM updates PF,SF, and ZF, but AF,CF, and OF are left undefined.

.c

Ex: ;AL=00000101=unpacked BCD 5

;BH=00001001= unpacked BCD 9

MUL BH

AAM

;AL x BH; result in AX


; AX=00000000 00101101=002DH
;AX=00000100 00000101=0405H,
Which is unpacked BCD for 45.
; if ASCII codes for the result are
;desired, use next instruction

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MICROPROCESSORS

ii)

10CS45

LOOP:

This instruction is used to repeat a series of instructions some number of times.

om

The number of times the instruction sequence is to be repeated is loaded into CX. Each time the
LOOP instrution executes, CX is automatically decremented by 1. If CX is not 0, execution will
jump to a destination specified by a label in the instruction. If CX=0 after the auto decrement,
execution will simply go on to the next instruction after LOOP.

;Point BX at
; first element in array
MOV CX,40 ;Load CX with number of
; elements in array
; get element from array

ADD AL,07

;Add correction factor

DAA

;Decimal adjust result

MOV [BX],AL

;Put result back in array

ud
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ts

NEXT: MOV AL,[BX]

INC BX

;Repeat until all elements adjusted.

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LOOP NEXT

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c

Ex: MOV BX,OFFSET PRICES

iii)

SUB:

.c

This instruction subtract the number in the indicated source from the number in the indicated
destination and put the result in the indicated destination.
Ex: SUB CX,BX

SBB CH,AL

SUB AX,3427
SUB BX,[3427H]

iv)

XLAT

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10CS45

It is used to translate a byte from one code to another code. The instruction replaces a byte in the
AL register with a byte pointed to by BX in a lookup table in memory.
Ex: MOV BX,OFFSET EBCDIC_TABLE

om

XLAT

gr
ou
p.
c

4.a. Explain the following instructions or directives in 8086 programming: i) global ii) call
iii) LAHE iv) TYPE v) NEG viii) TEST ix) GROUP x) XLAT Jan 2015 [10marks]

i) global

GLOBAL The labels, variables, constants or procedures declared GLOBAL may

be used by other modules of the program. Once a variable is declared GLOBAL, it

ud
en
ts

can be used by any module in the program. The following statement declares the
procedure ROUTINE as a global label.
ROUTINE PROC GLOBAL
ii)call
CALL : Unconditional Call

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st

This instruction is used to call a Subroutine (Procedure) from a main program.


Address of procedure may be specified directly or indirectly.

.c

There are two types of procedure depending upon whether it is available in the
same segment or in another segment.

i. Near CALL i.e., 32K displacement.

ii. For CALL i.e., anywhere outside the segment.

iii TYPE
TYPE The TYPE operator directs the assembler to decide the data type of the
specified label and replaces the 'TYPE label' by the decided data type. For the
word type variable, the data type is 2, for double word type, it is 4, and for byte

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MICROPROCESSORS

10CS45

type, it is 1. Suppose, the STRING is a word array. The instruction


MOV AX, TYPE STRING moves the value 0002H in AX.

NEG : Negate
The negate instruction forms 2s complement of the specified destination in the

om

NEG

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c

instruction. The destination can be a register or a memory location. This instruction can be
implemented by inverting each bit and adding 1 to it.
Eg. NEG AL

AL = 0011 0101 35H Replace number in AL with its 2s complement


AL = 1100 1011 = CBH

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ts

viii) TEST
TEST : Logical Compare Instruction

The TEST instruction performs a bit by bit logical AND operation on the two operands. The
result of this ANDing operation is not available for further use, but flags are affected.
Eg. TEST AX, BX
TEST [0500], 06H

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GROUP

.c

GROUP: Group the Related segment The directive is used to form logical groups of segments
with similar purpose or type. This directive is used to inform the assembler to form a logical
group of the following segment names. The assembler passes an information to the linker/loader
to form the code such that the group declared segments or operands must lie within a 64Kbyte
memory segment. Thus all such segments and labels can be addressed using the same segment
base.

PROGRAM GROUP CODE, DATA, STACK

The above statement directs the loader/linker to prepare an EXE file such that CODE, DATA
and STACK segment must lie within a 64kbyte memory segment that is named as PROGRAM.
Now, for the ASSUME statement, one can use the label PROGRAM rather than CODE, DATA
and STACK as shown.
ASSUME CS: PROGRAM, DS: PROGRAM, SS: PROGRAM.

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10CS45

5.a Write a ALP using C/C++ to perform the operation X+Y=Z with proper comments

June 2014[10 marks]

gr
ou
p.
c

main proc
mov ax,@data
mov ds,ax

om

.model small
.stack 100h
.data
str1 db 'Enter String ','$'
str2 db 50 dup('$')
str3 db 0dh, 0ah, '$'
.code

mov ah,09h
lea dx,str1
int 21h

; for displaying Enter String

; for taking i/p from keyboard

ud
en
ts

mov ah,0ah
lea dx,str2
int 21h

mov ah,09h ; for displaying in new line


lea dx,str3
int 21h
mov ah,09h
lea dx,str2+2
int 21h

; for displaying what you have entered

.c

end main

ity
st

int 21h
mov ah,4ch
int 21h
main endp

5.b Define modular programming. Using the concepts of public and extra directives writ a program
which reads data in a program in one module which is then used by another module June 2014[06

marks]

Registers and instructions


The 8086 has eight more or less general 16-bit registers (including the stack pointer but excluding the
instruction pointer, flag register and segment registers). Four of them, AX, BX, CX, DX, could also be
accessed as twice as many 8-bit registers (see figure) while the other four, BP, SI, DI, SP, were 16-bit
only.

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10CS45

Due to a compact encoding inspired by 8-bit processors, most instructions were one-address or twoaddress operations which means that the result was stored in one of the operands. At most one of the
operands could be in memory, but this memory operand could also be the destination, while the other
operand, the source, could be either register or immediate. A single memory location could also often be

om

used as both source and destination which, among other factors, further contributed to a code density
comparable to (and often better than) most eight bit machines.

The degree of generality of most registers were much greater than in the 8080 or 8085. However, 8086

gr
ou
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c

registers were more specialized than in most contemporary minicomputers and also used implicitly by
some instructions. While perfectly sensible for the assembly programmer, this made register allocation for
compilers more complicated compared to more orthogonal 16- and 32-bit processors such as the PDP-11,

VAX, 68000, 32016 etc. On the other hand, being more regular than rather minimalistic but ubiquitous 8bit microprocessors such as the 6502, 6800, 6809, 8085, MCS-48, 8051 and other contemporary
accumulator based machines, it was significantly easier to construct an efficient code generator for the
8086 design.

ud
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ts

Another factor for this was that the 8086 also introduced some new instructions (not present in the 8080
and 8085) to better support stack based high level programming languages such as Pascal and PL/M;
some of the more useful ones were push mem-op, and ret size, supporting the "pascal calling convention"
directly. (Several others, such as push immed and enter, would be added in the subsequent 80186, 80286,
and 80386 processors.)

The 8086 had a 64 KB of 8-bit (or alternatively 32 K-word of 16-bit) I/O space. A 64 KB (one segment)

ity
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stack growing towards lower addresses is supported in hardware; 2-byte words are pushed to the stack
and the stack top is pointed to by SS:SP. There are 256 interrupts, which can be invoked by both
hardware and software. The interrupts can cascade, using the stack to store the return addresses.
Flags

.c

8086 has a 16-bit flags register. Nine of these condition code flags are active, and indicate the current
state of the processor: Carry flag (CF), Parity flag (PF), Auxiliary carry flag (AF), Zero flag (ZF), Sign

flag (SF), Trap flag (TF), Interrupt flag (IF), Direction flag (DF), and Overflow flag (OF).

June 2014[04 marks]

5.c Differentiate between macros and procedures


Macro

Procedure

Accessed during assembly with name given to Accessed by CALL and RET instruction during
macro when defined.
program execution.
Machine code is generate for instructions each time Machine code for instruction is put only once in the

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10CS45

when macro is called

memory

With macro more memory is required

With procedure less memory is required

om

Parameter passed as part of statement which call Parameters can be passed in registers memory
macros
locations are stack.

gr
ou
p.
c

Unit-6
1.a. Explain the functions of following pins of 8086 mp
i) ALE

ii)INTR

iii)HOLD

iv)RESET

June/July 13 [5 Marks]

v)BHE

i) ALE
Address latch enable shows that the 8086/8088address/data bus contains address
information. This address can be a memory address or an I/O port number
ii)INTR

Interrupt request is used to request a hardware interrupt.

ud
en
ts

INTR is held high when IF =1, the 8086/8088 enters an interrupt acknowledge cycle (INTA
becomes active) after the current instruction has completed execution.
iii)HOLD If the HOLD signal is a logic 1, the microprocessor stops executing software and
places its address, data, and control bus at the high-impedance state.
If the HOLD pin is a logic 0, the microprocessor executes software normally.

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iv)RESET The reset input causes the microprocessor to reset itself if this pin is held high for a
minimum of four clocking periods. Whenever the 8086 or 8088 is reset, it begins executing
instructions at memory location FFFFOH and disables future interrupts by clearing the IF flag
bit.

.c

v)BHE The bus high enable pin is used in the 8086 to enable the most significant data bus bits
(D l5-D8) during a read or a write operation. The state of S7 is always a logic 1

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MICROPROCESSORS

10CS45

1.b. Explain how address de-multiplexing is done in 8086 processor based systems.

.c

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ts

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c

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June/July 13 [7 Marks]

1.c. With a neat timing diagram, explain memory read cycle.

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10CS45

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MICROPROCESSORS

.c

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2.a. Explain the minimum mode pins of 8086 and maximum mode configuration of 8086
with neat diagram.
Dec 13/Jan 14 [10 Marks]

Pin Functions

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MICROPROCESSORS

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ud
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AD7-ADo The 8088 address/data bus lines compose the multiplexed address data bus of
the 8088 and contain the rightmost 8-bits of the memory address or I/O port number
whenever ALE is active (logic 1) or data whenever ALE is active (logic 0). These pins
are at their high-impedance state during a hold acknowledged.
A15-A8 The 8088 address bus provides the upper-half memory address bits that are
present throughout a bus cycle. These address connections go to their high-impedance
state during a hold acknowledge.
AD15-AD8
The 8086 address/data bus lines compose the upper multiplexed
address/data bus on the 8086.
ALE=1 These lines contain address bits .(A15-A8)
ALE=0 These pins enter a high-impedance state whenever a hold acknowledge occurs
AD19/S6-AD16/S3 The address/status bus bits are multiplexed to provide address signals
A19-A I6 and also status bits S6-S3 These pins also attain a high impedance state during
the hold acknowledge.
Status bit S6 always remains a logic 0,
S5 indicates the condition of the IF flag bits,
S4 and S3 show which segment is accessed during the current bus cycle.
Table 8-4 for the truth table

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c

10CS45

.c

RD Whenever the read signal is a logic 0, the data bus is receptive to data from the memory or
I/O devices connected to the system.

READY The ready input is controlled to insert wait states into the timing of the microprocessor.
If the READY pin is placed at a logic 0 level, the microprocessor enters into wait states and
remains idle.
If the READY pin is placed at a logic 1 level, it has no effect on the operation of the
microprocessor.
INTR Interrupt request is used to request a hardware interrupt.

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10CS45

INTR is held high when IF =1, the 8086/8088 enters an interrupt acknowledge cycle (INTA
becomes active) after the current instruction has completed execution.
Test The Test pin is an input that is tested by the WAIT instruction.

om

If TEST is a logic 0, the WAIT instruction functions as a NOP.


If TEST is a logic 1, then the WAIT instruction waits. for TEST to become a logic O. This pin is
often connected to the 8087 numeric coprocessor.

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Non-Maskable Interrupt The non-maskable interrupt input is similar to INTR except that the
NMI interrupt does not check to see if the IF flag bit is a logic 1. If NMI is activated, this
interrupt input uses interrupt vector 2.

Reset The reset input causes the microprocessor to reset itself if this pin is held high for a
minimum of four clocking periods. Whenever the 8086 or 8088 is reset, it begins executing
instructions at memory location FFFFOH and disables future interrupts by clearing the IF flag
bit.

ud
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ts

CLK The clock pin provides the basic timing signal to the microprocessor. The clock signal
must have a duty cycle of 33% (high for one-third of the clocking period and low for two-thirds)
to provide proper internal timing for the 8086/8088.
VCC This power supply input provides a +5.0 V, 10 % signal to the microprocessor.

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GND The ground connection is the return for the power supply. Note that the 8086/8088
microprocessors have two pins labeled GND-both must be connected to ground for proper
operation.
MN/MX The minimum/maximum mode pin selects either minimum mode or maximum mode
operation for the microprocessor. If minimum mode is selected, the MN/MX pin must be
connected directly to +5.0 V.

.c

BHE/S7 The bus high enable pin is used in the 8086 to enable the most significant data bus bits
(D l5-D8) during a read or a write operation. The state of S7 is always a logic 1.

Minimum mode Pins:


Minimum mode operation of the 8086/8088 is obtained by connecting the MN/MX pin

directly to +5.0 V. Do not connect this pin to +5.0


IO/M or M/IO this pin selects memory or I/O. This pin indicates that the microprocessor
address bus contains either a memory address or an I/O port address.

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10CS45

WR The write line is a strobe that indicates that the 8086/8088 is outputting data to a memory or
I/O device. During the time that the WR is a logic 0, the data bus contains valid data for memory
or I/O. This pin floats to a high-impedance during a hold acknowledge.

om

INTA The interrupt acknowledge signal is a response to the INTR input pin. The INTA pin is
normally used to gate the interrupt vector number onto the data bus in response to an interrupt
request.

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ALE Address latch enable shows that the 8086/8088address/data bus contains address
information. This address can be a memory address or an I/O port number
DT/R The data transmit/receive signal shows that the microprocessor data bus is transmitting
(DTIR = 1) or receiving (DTIR = 0) data. This signal is used to enable external data bus buffers.
DEN Data bus enable activates external data bus buffers.

HOLD The hold input requests a direct memory access (DMA).

ud
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ts

If the HOLD signal is a logic 1, the microprocessor stops executing software and places its
address, data, and control bus at the high-impedance state.
If the HOLD pin is a logic 0, the microprocessor executes software normally.
HLDA Hold acknowledge indicates that the 8086/8088 microprocessors have entered the hold
state.

.c

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SS0 The SS0 status line is equivalent to the S0 pin in maximum mode operation of the
microprocessor. This signal is combined with IO/M and DTIR to decode the function of the
current bus cycle ( Table 8-5).

Maximum Mode Pins. In order to achieve maximum mode for use with external
coprocessors, connect the MN/MX pin to ground.

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10CS45

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om

S2, S1, and S0 The status bits indicate the function of the current bus cycle. These signals are
normally decoded by the 8288 bus controller . Table 8-6 shows the function of these three status
bits in the maximum mode.

ud
en
ts

RO/GT1 and RQ/GTO The request/grant pins request direct memory accesses (DMA) during
maximum mode operation. These lines are both bi-directional and are used to request and grant a
DMA operation
Lock The lock output is used to lock peripherals off the system. This pin is activated by using
the LOCK: prefix on any instruction.
QS1 and QS0 The queue status bits show the status of the internal instruction queue. These pins
are provided for access by the numeric coprocessor (8087).

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Table 8-7 for the operation of the queue status bits.

.c

2.b. Describe internal block diagram of 8288 bus controller with explanation of each pins
Dec 13/Jan 14 [6 Marks]

An 8086/8088 system that is operated in maximum mode must have an 8288 bus controller
to provide the signals that are eliminated from the 8086/8088 by the maximum mode
operation.

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10CS45

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MICROPROCESSORS

I/O (IORC and IOWC) and memory (MRDC and MWTC). It also contains advanced
memory (AMWC) and I/O (AIOWC) write strobes and the INTA signal.
These signals replace the minimum mode ALE, WR, IO/M, DTIR, DEN, and INTA, which
are lost when the 8086/8088 is operated in the maximum mode.

ity
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Pin Functions.

The following list provides a description of each pin of the 8288 bus controller.
S2, S1, and S0

.c

Status inputs are connected to the status output pins on the 8086/8088 microprocessors.
These three signals are decoded to generate the timing signals for the system.

CLK

The clock input provides internal timing and must be connected to the CLK output pin of the
8284A clock generator.
ALE
The address latch enable output is used to demultiplex the address/data bus.
DEN

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MICROPROCESSORS

10CS45

The data bus enable pin controls the bi-directional data bus buffers in the system. Note that
this is an active high-output pin that is the opposite polarity from the DEN signal found on
the microprocessor when operated in the minimum mode.

om

DT/R
The data transmit/receive signal is output by the 8288 to control the direction of the bidirectional data bus buffers.

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c

AEN
The address enable input causes the 8288 to enable the memory control signals.
CEN

The control enable input enables the command output pins on the 8288.
IOB

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ts

The I/O bus mode input selects either the I/O bus mode or system bus mode operation.
AIOWC

The advanced I/O write command output provides I/O with an advanced I/O write control
signal.
IOWC

IORC

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The I/O write command output provides I/O with its main write signal.

The I/O read command output provides I/O with its read control signal.

.c

AMWC

The advanced memory write control pin provides memory with an early or advanced write
signal.

MWTC

The memory write control pin provides memory with its normal write control signal.
MRDC
The memory read control pin provides memory with a read control signal.
INTA

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10CS45

The interrupt acknowledge output acknowledges an interrupt request input applied to the
INTR pin.
MCE/PDEN

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c

Dec 13/Jan 14 [4 Marks]

.c

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ud
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ts

2.c. with neat diagram explain I/O read operation.

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The master cascade/peripheral data output selects cascade operation for an interrupt
controller if IOB is grounded and enables the I/O bus transceivers if IOB is tied high.

3.a. differentiate between memory mapped I/O and direct I/O. Dec 2012 [5 Marks]
I/O mapped I/O

Memory ,apped I/O

In this device address is 16 bit. Thus A0 to A15 In this I/O device address is 8 bit. Thus A0 to
lines are used to generate device address.
A7 OR A8 to A15 lines are used to generate
device address.
Data trasfer is between any register and I/O Data transfer is between accumulator and I/O

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device.

Maximum number of I/O devices are 65536

Maximum number of I/O devices are 256.

exection speed using LDA addr,STA addr is 13 Execution speed is 10 T-states.


T-state & 7T-states for MOV M,r and MOV
r,M instructions.

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device.

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Decoding 16bit address may require more Decoding 8 bit address will require less
hardware.
hardware.

Dec 2012 [5 Marks]

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3.b. write the timing diagram for a memory read machine cycle.

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Dec 2012 [10marks]

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3.c. With a neat diagram, explain the pin configuration of 8086.

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AD15-AD0: These are the time multiplexed memory I/O address and data lines. Address remains
on the lines during T1 state, while the data is available on the data bus during T2,T3, TW and
T4. Here T1, T2, T3, T4 and TW are the clock states of a machine cycle. TW is a wait state.
These lines are active high and float to a tristate during interrupt acknowledge and local bus hold
acknowledge cycles.

A19/S6, A18/S5, A17/S4, A16/S3: These are the time multiplexed address and status lines.
During T1, these are the most significant address lines or memory operations. During I/O
operations, these lines are low. During memory or I/O operations, status information is available
on those lines for T2, T3, TW and T4 .The status of the interrupt enable flag bit(displayed on S5)
is updated at the beginning of each clock cycle. The S4 and S3 combinedly indicate which
segment register is presently being used for memory accesses as shown in Table 1.1. These lines
float to tri-state off (tristated) during the local bus hold acknowledge. The status line S6 is
always low(logical). The address bits are separated from the status bits using latches controlled
by the ALE signal.

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BHE/S7-Bus High Enable/Status: The bus high enable signal is used to indicate the transfer of
data over the higher order (D15-D8) data bus as shown in Table 1.2. It goes low for the data
transfers over D15-D8 and is used to derive chip selects of odd address memory bank or
peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles, when- ever
a byte is to be transferred on the higher byte of the data bus. The status information is available
during T2, T3 and T4. The signal is active low and is tristated during 'hold'. It is low during T1
for the first pulse of the interrupt acknowledge cycle.

RD-Read: Read signal, when low, indicates the peripherals that the processor is performing a
memory or I/O read operation. RD is active low and shows the state for T2, T3, TW of any read
cycle. The signal remains tristated during the 'hold acknowledge'.

READY: This is the acknowledgement from the slow devices or memory that they have
completed the data transfer. The signal made available by the devices is synchronized by the
8284A clock generator to provide ready input to the 8086. The signal is active high.
INTR-lnterrupt Request: This is a level triggered input. This is sampled during the last clock
cycle of each instruction to determine the availability of the request. If any interrupt request is
pending, the processor enters the interrupt acknowledge cycle. This can be internally masked by
resetting the interrupt enable flag. This signal is active high and internally synchronized.

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TEST: This input is examined by a 'WAIT' instruction. If the TEST input goes low, execution
will continue, else, the processor remains in an idle state. The input is synchronized internally
during each clock cycle on leading edge of clock. NMI-Non-maskable Interrupt: This is an edgetriggered input which causes a Type2 interrrupt. The NMI is not maskable internally by software.
A transition from low to high initiates the interrupt response at the end of the current instruction.
This input is internally synchronized.

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RESET: This input causes the processor to terminate the current activity and start execution from
FFFF0H. The signal is active high and must be active for at least four clock cycles. It restarts
execution when the RESET returns low. RESET is also internally synchronized.
CLK-Clock Input: The clock input provides the basic timing for processor operation and bus
control activity. Its an asymmetric square wave with 33% duty cycle. The range of frequency for
different 8086 versions is from 5MHz to 10MHz.
VCC : +5V power supply for the operation of the internal circuit. GND ground for the internal
circuit.

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MN/MX :The logic level at this pin decides whether the processor is to operate in either
minimum (single processor) or maximum (multiprocessor) mode.
M/IO -Memory/IO: This is a status line logically equivalent to S2 in maximum mode. When it is
low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the
CPU is having a memory operation.

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4.a. Write signal activities on 8086 buses, during a simple read operation.
Jan 2015 [10 Marks]

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AD15-AD0: These are the time multiplexed memory I/O address and data lines. Address remains
on the lines during T1 state, while the data is available on the data bus during T2,T3, TW and
T4. Here T1, T2, T3, T4 and TW are the clock states of a machine cycle. TW is a wait state.
These lines are active high and float to a tristate during interrupt acknowledge and local bus hold
acknowledge cycles.

A19/S6, A18/S5, A17/S4, A16/S3: These are the time multiplexed address and status lines.
During T1, these are the most significant address lines or memory operations. During I/O
operations, these lines are low. During memory or I/O operations, status information is available
on those lines for T2, T3, TW and T4 .The status of the interrupt enable flag bit(displayed on S5)
is updated at the beginning of each clock cycle. The S4 and S3 combinedly indicate which
segment register is presently being used for memory accesses as shown in Table 1.1. These lines
float to tri-state off (tristated) during the local bus hold acknowledge. The status line S6 is
always low(logical). The address bits are separated from the status bits using latches controlled
by the ALE signal.

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4.b. What is need of memory banking? With a neat block diagram, explain the memory
banking in 8086.
Jan 2015 [10 Marks]
The 8086 is a 16-bit processor with a 16-bit memory bus. That requires a memory subsystem that
can deliver 16-bits at a time, probably built using two sets of 8-bit memory chips.

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The 8088 uses an 8-bit memory bus, to make it cheaper. It was designed to save on the minimum
number of chips needed to build a system.

Memory Banks

8086 has a 16-bit memory bus which means that data transfer can occur at a maximum rate of
16 bits (one word) per bus cycle. However, sometimes only a byte needs to be accessed. This
means that the processor must have both options i.e., both byte and word transfer must be
possible. We know that for a word transfer, two byte locations must be accessed i.e., two
addresses are actually needed.

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5.a Describe in details the uses of the following signals

marks]
ACE

RESET

NMI

HOLD

MN/MX

June 2014[06

QSI and

QSQ

ii)INTR

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i) ALE Address latch enable shows that the 8086/8088address/data bus contains address information.
This address can be a memory address or an I/O port number
Interrupt request is used to request a hardware interrupt.

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INTR is held high when IF =1, the 8086/8088 enters an interrupt acknowledge cycle (INTA becomes
active) after the current instruction has completed execution.

iii)HOLD If the HOLD signal is a logic 1, the microprocessor stops executing software and places its
address, data, and control bus at the high-impedance state.

If the HOLD pin is a logic 0, the microprocessor executes software normally.

iv)RESET The reset input causes the microprocessor to reset itself if this pin is held high for a minimum
of four clocking periods. Whenever the 8086 or 8088 is reset, it begins executing instructions at memory
location FFFFOH and disables future interrupts by clearing the IF flag bit.
v)BHE The bus high enable pin is used in the 8086 to enable the most significant data bus bits (D l5-D8)
during a read or a write operation. The state of S7 is always a logic 1

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5.b Explain in detail with a neat figure demultiplexing of address and data lines in 8086

June 2014[06

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The Address and Data Busses

The address bus has 8 signal lines A8 A15which are unidirectional.


The other 8 address bits are multiplexed(time shared) with the 8 data bits.
So, the bits AD0 AD7are bi-directionaland serve as A0 A7and D0 D7at the same time.
During the execution of the instruction, these lines carry the address bits during the early part,
then during the late parts of the execution, they carry the 8 data bits.
In order to separate the address from the data, we can use a latch to save the value before the
function of the bits changes.
Demultiplexing AD7-AD0
From the above description, it becomes obvious that the AD7AD0lines are serving a dual
purposeand that they need to be demultiplexed to get all the information.The high order bitsof

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the address remain on the bus for three clock periods. However, the low order bitsremain for
only one clock period and they would be lost if they are not saved externally. Also, notice that
the low order bitsof the address disappearwhen they are needed most.
To make sure we have the entire address for the full three clock cycles, we will use an external
latchto save the value of AD7AD0 when it is carrying the address bits. We use the ALE signal
to enable this latch.

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ALE operates as a pulse during T1, we will be able to latch the address. Then when ALE goes
low, the address is saved and the AD7AD0 lines can be used for their purpose as the bidirectional data lines.

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The high order address is placed on the address bus and hold for 3 clk periods,
The low order address is lost after the first clk period, this address needs to be hold however we
need to use latch
The address AD7 AD0 is connected as inputs to the latch 74LS373.
The ALE signal is connected to the enable (G) pin of the latch and the OC Output control of
the latch is grounded which you can see in the given diagram

5.c Explain with a neat figure the working of 8086 in MIN mode configuration

marks]
Minimum mode Pins:

June 2014[08

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Minimum mode operation of the 8086/8088 is obtained by connecting the MN/MX pin directly to +5.0 V.
Do not connect this pin to +5.0
IO/M or M/IO this pin selects memory or I/O. This pin indicates that the microprocessor address bus
contains either a memory address or an I/O port address.

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WR The write line is a strobe that indicates that the 8086/8088 is outputting data to a memory or I/O
device. During the time that the WR is a logic 0, the data bus contains valid data for memory or I/O. This
pin floats to a high-impedance during a hold acknowledge.

INTA The interrupt acknowledge signal is a response to the INTR input pin. The INTA pin is normally
used to gate the interrupt vector number onto the data bus in response to an interrupt request.

ALE Address latch enable shows that the 8086/8088address/data bus contains address information. This
address can be a memory address or an I/O port number
DT/R The data transmit/receive signal shows that the microprocessor data bus is transmitting (DTIR = 1)
or receiving (DTIR = 0) data. This signal is used to enable external data bus buffers.
DEN Data bus enable activates external data bus buffers.

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HOLD The hold input requests a direct memory access (DMA).


If the HOLD signal is a logic 1, the microprocessor stops executing software and places its address, data,
and control bus at the high-impedance state.

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If the HOLD pin is a logic 0, the microprocessor executes software normally.


HLDA Hold acknowledge indicates that the 8086/8088 microprocessors have entered the hold state.

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SS0 The SS0 status line is equivalent to the S0 pin in maximum mode operation of the microprocessor.
This signal is combined with IO/M and DTIR to decode the function of the current bus cycle ( Table 8-5).

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Unit-7
1.a. List various memory devices.

June/July 13 [2 Marks]

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The EPROM (erasable programmable read-only memory), a type of ROM, is more


commonly used when software must be changed often or when too limited a number are in
demand to make the ROM economical. For a ROM to be practical, we usually must purchase
at least] 10,000 devices. An EPROM is programmed in the field on a device called an
EPROM programmer. The EPROM is also erasable if exposed to high-intensity ultraviolet
light for about 20 minutes or less, depending on the type of EPROM.

PROM memory devices are also available, but they are not as common today. The PROM
(programmable read-only memory) is also programmed in the field by burning open tiny
Nichrome or silicon oxide fuses, but once programmed it cannot be erased,
RMM Newer type of read-mostly memory (RMM) is called the flash memory. The flash
memory! is also often called an EEPROM (electrically erasable programmable ROM),

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EAROM (electrically alterable ROM), or a NOVRAM (nonvolatile RAM). These memory


devices are electrically erasable in the system, but require more time to erase than a normal
RAM.
1.b. What is memory address decoding? Design a memory system for 8086 for the following
specifications
June/July 13 [10marks]
32 kbytes EPROM using 16 Kbytes devices
64 kbytes SRAM using 16 Kbytes devices

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i)
ii)
Draw memory map.

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Memory Address Decoding


The processor can usually address a memory space that is much larger than the memory space
covered by an individual memory chip. In order to splice a memory device into the address space
of the processor, decoding is necessary. For example, the 8088 issues 20-bit addresses for a total
of 1MB of memory address space. However, the BIOS on a 2716 EPROM has only 2KB of
memory and 11 address pins. A decoder can be used to decode the additional 9 address pins and
allow the EPROM to be placed in any 2KB section of the 1MB address space.
Memory Address Decoding
To determine the address range that a device is mapped into: This 2KB memory segment maps
into the reset location of the 8086/8088 (FFFF0H). NAND gate decoders are not often used

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Large fan-in NAND gates are not efficient Multiple NAND gate IC's might be required to
perform such decoding Rather the 3-to-8 Line Decoder (74LS138) is more common.

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1.c. what are the sources of interrupts? Briefly explain the steps taken by a processor to
execute an interrupt instruction.
June/July 13 [8marks]
interrupt sources and processor handling

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In systems programming, an interrupt is a signal to the processor emitted by hardware or


software indicating an event that needs immediate attention. An interrupt alerts the processor to a
high-priority condition requiring the interruption of the current code the processor is executing,
the current thread. The processor responds by suspending its current activities, saving its state,
and executing a small program called an interrupt handler (or interrupt service routine, ISR) to
deal with the event. This interruption is temporary, and after the interrupt handler finishes, the
processor resumes execution of the previous thread. There are two types of interrupts:

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A hardware interrupt is an electronic alerting signal sent to the processor from an external
device, either a part of the computer itself such as a disk controller or an external peripheral. For
example, pressing a key on the keyboard or moving the mouse triggers hardware interrupts that
cause the processor to read the keystroke or mouse position. Unlike the software type (below),
hardware interrupts are asynchronous and can occur in the middle of instruction execution,
requiring additional care in programming. The act of initiating a hardware interrupt is referred to
as an interrupt request (IRQ).
A software interrupt is caused either by an exceptional condition in the processor itself, or a
special instruction in the instruction set which causes an interrupt when it is executed. The
former is often called a trap or exception and is used for errors or events occurring during
program execution that are exceptional enough that they cannot be handled within the program
itself. For example, if the processor's arithmetic logic unit is commanded to divide a number by

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zero, this impossible demand will cause a divide-by-zero exception, perhaps causing the
computer to abandon the calculation or display an error message. Software interrupt instructions
function similarly to subroutine calls and are used for a variety of purposes, such as to request
services from low level system software such as device drivers. For example, computers often
use software interrupt instructions to communicate with the disk controller to request data be
read or written to the disk.

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Each interrupt has its own interrupt handler. The number of hardware interrupts is limited by the
number of interrupt request (IRQ) lines to the processor, but there may be hundreds of different
software interrupts.
2.a. with a neat diagram, explain simple NAND gate address decoding logic.

Dec 13/Jan 14 [10 marks]

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When the 2K 8 EPROM is used, address connections A10A0 of the 8088 are connected to
address inputs A10A0 of the EPROM. The remaining nine address pins (A19A11) are
connected to the inputs of a NAND gate decoder (see Figure 1013). The decoder selects the
EPROM from one of the 2K-byte sections of the 1M-byte memory system in the 8088
microprocessor.In this circuit, a single NAND gate decodes the memory address. The output of
the NAND gate is a logic 0 whenever the 8088 address pins attached to its inputs (A19A11) are
all logic 1s. The active low, logic 0 output of the NAND gate decoder is connected to the CE*
input pin that selects (enables) the EPROM. Recall that whenever CE* is a logic 0, data will be
read from the EPROM only if OE* is also a logic 0. The OE* pin is activated by the 8088 RD*
signal or the MRDC* (memory read control) signal of other family members. If the 20-bit binary
address, decoded by the NAND gate, is written so that the leftmost nine bits are 1s and the
rightmost 11 bits are dont cares (X), the actual address range of the EPROM can be determined.
(A dont care is a logic 1 or a logic 0, whichever is appropriate.) Example below illustrates how
the address range for this EPROM is determined by writing down the externally decoded address
bits (A19A11) and the address bits decoded by the EPROM (A10A0) as dont cares. We really
do not care about the address pins on the EPROM because they are internally decoded. As the
example illustrates, the dont cares are first written as 0s to locate the lowest address and then as
1s to find the highest address.Example also shows these binary boundaries as hexadecimal
addresses. Here, the 2K EPROM is decoded at memory address locations FF800HFFFFFH.
Notice that this is a 2K-byte section of the memory and is also located at the reset location for
the 8086/8088 (FFFF0H), the most likely place for an EPROM in a system

EXAMPLE:
1111 1111 1XXX XXXX XXXX
OR

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1111 1111 1000 0000 0000 ->FFE00


to

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1111 1111 1111 1111 1111 ->FFFFF

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Although this example serves to illustrate decoding, NAND gates are rarely used to decode
memory because each memory device requires its own NAND gate decoder. Because of the
excessive cost of the NAND gate decoder and inverters that are often required, this option
requires that an alternate be found.

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2.b. differentiate between memory mapped I/O and direct I/O Dec 13/Jan 14 [5 marks]
The characteristics of isolated I/O are as follows:

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- The devices of I/O are treated in a separate domain as compared to memory.


- A total of 1mb address space is allowed for memory applications.

- In order to maximize the I/O operations ( isolated ) separate instructions are always provided to
perform these operations.

- One of the disadvantages is that the data transfer only occurs between the I/O port and the AL,
AX registers.

The characteristics of the memory mapped I/O are as follows:


- In such scenarios the devices (I/O) are treated as a part of the memory only.

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- Complete 1mb of memory cannot be used as they are a part of the memory.
- In case of memory mapped I/O operations no external separate instructions are required.

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- There is data transfer restriction in case of memory mapped instructions.

Memory 1M

Memory
I/O

I/O 64K

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Memory mapped I/0


Total
1M

Traditional setup

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Memory

Memory mapped I/O

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2.c. Briefly explain handshaking or polling with necessary diagrams


Dec 13/Jan 14 [5 marks]

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More sophisticated devices require synchronization. Synchronization techniques notify the


microcontroller when new data is at an input port and notify external devices when new data is at
an output port. Synchronization takes two forms, strobesand state or level handshakingIn
general, handshaking negotiates secure and reliable transfer of data commonly called
communications. It involves both knowledge and acknowledge. The sender needs a signal from
the receiverto know when the receiver is ready to accept the data .The sender supplies a signal
line that is used to tell the receiver two distinct pieces of information: then the receiver can read
valid data and when the write cycle has finished. The receiver uses a signal line to tell the sender
when it is ready to receive data and when it has read the data. These handshaking requirements
are summarized in the timing diagram shown in Figure 2. When handshaking uses hardware ires,
bits in a status register or bits within a stream of communications to implement the interaction
between sender and receiver as shown in Figure 2, the handshaking is calledexplicate. Some
handshaking schemes assume that the receiver is always ready and can accept the data within
specified timing constrains. Such handshaking schemes are calledimplicate or time
implicate handshaking

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3.a. Briefly explain the structure of 8086 interrupt response and interrupt vector table with
a neat diagram.
Dec 2012 [10 Marks]

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The 8086 responds to the interrupt by stepping through the following series of major actions.

1. It decrements the stack pointer by 2 and pushes the flag register on the stack.
2. It disables the 8086 INTR interrupt input by clearing the interrupt flag(IF) in the flag
register.
3. It resets the trap flag in the register.
4. It decrements the stack pointer by 2 and pushes the current code segment register
contents on the stack.

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5. It decrements the stack pointer again by 2 and pushes the current instruction pointer
contents on the stack.

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6. It does an indirect far jump to the start of the procedure you wrote to respond to the
interrupt.

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The starting address of an interrupt-service procedure is often called the interrupt vector or the
interrupt pointer, so the table is referred to as the interrupt-vector table or the interrupt-pointer
table.
Note that the instruction pointer value is put in as the low word of the vector, and the code
segment register is put in as the high word of the vector. Each doubleword interrupt vector is
identified buy a number from 0 to 255.
3.b. explain with block diagram, the working of 8259 and also explain ICWs format.

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Dec 2012 [10 Marks]

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4.a Differentiate between memory mapped I/O and I/O mapped I/O

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marks]
Memory ,apped I/O

June

2014[04

I/O mapped I/O

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In this device address is 16 bit. Thus A0 to A15 lines In this I/O device address is 8 bit. Thus A0 to A7
are used to generate device address.
OR A8 to A15 lines are used to generate device
address.

Data trasfer is between any register and I/O device.

Maximum number of I/O devices are 256.

Maximum number of I/O devices are 65536

Data transfer is between accumulator and I/O


device.

exection speed using LDA addr,STA addr is 13 T- Execution speed is 10 T-states.


state & 7T-states for MOV M,r and MOV r,M
instructions.
Decoding 16bit
hardware.

address

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may

require

more Decoding 8 bit address will require less hardware.

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4.b i)64 kbytes EPROM ii)64 kbytes RAM . assume Ram is connected at 30000h and

EPROM at F00000h.

June 2014[08 marks]

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Memory Address Decoding


The processor can usually address a memory space that is much larger than the memory space covered by
an individual memory chip. In order to splice a memory device into the address space of the processor,
decoding is necessary. For example, the 8088 issues 20-bit addresses for a total of 1MB of memory
address space. However, the BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins. A
decoder can be used to decode the additional 9 address pins and allow the EPROM to be placed in any
2KB section of the 1MB address space.
Memory Address Decoding
To determine the address range that a device is mapped into: This 2KB memory segment maps into the
reset location of the 8086/8088 (FFFF0H). NAND gate decoders are not often used
Large fan-in NAND gates are not efficient Multiple NAND gate IC's might be required to perform such
decoding
Rather
the
3-to-8
Line
Decoder
(74LS138)
is
more
common.

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4.c. what are the sources of interrupts? Briefly explain the steps taken by a processor to execute an
interrupt instruction.
June/July 13 [8marks]
interrupt sources and processor handling

In systems programming, an interrupt is a signal to the processor emitted by hardware or software


indicating an event that needs immediate attention. An interrupt alerts the processor to a high-priority
condition requiring the interruption of the current code the processor is executing, the current thread. The
processor responds by suspending its current activities, saving its state, and executing a small program
called an interrupt handler (or interrupt service routine, ISR) to deal with the event. This interruption is
temporary, and after the interrupt handler finishes, the processor resumes execution of the previous
thread. There are two types of interrupts:

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A hardware interrupt is an electronic alerting signal sent to the processor from an external device, either a
part of the computer itself such as a disk controller or an external peripheral. For example, pressing a key
on the keyboard or moving the mouse triggers hardware interrupts that cause the processor to read the
keystroke or mouse position. Unlike the software type (below), hardware interrupts are asynchronous and
can occur in the middle of instruction execution, requiring additional care in programming. The act of
initiating a hardware interrupt is referred to as an interrupt request (IRQ).

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A software interrupt is caused either by an exceptional condition in the processor itself, or a special
instruction in the instruction set which causes an interrupt when it is executed. The former is often called
a trap or exception and is used for errors or events occurring during program execution that are
exceptional enough that they cannot be handled within the program itself. For example, if the processor's
arithmetic logic unit is commanded to divide a number by zero, this impossible demand will cause a
divide-by-zero exception, perhaps causing the computer to abandon the calculation or display an error
message. Software interrupt instructions function similarly to subroutine calls and are used for a variety of
purposes, such as to request services from low level system software such as device drivers. For example,
computers often use software interrupt instructions to communicate with the disk controller to request
data be read or written to the disk.

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Each interrupt has its own interrupt handler. The number of hardware interrupts is limited by the number
of interrupt request (IRQ) lines to the processor, but there may be hundreds of different software
interrupts.

5.a. List and explain the hardware interrupt applications.

Jan 2015 [8 Marks]

In general the interrupts can be classified in the following three ways :


1. Hardware and software interrupts

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2. Vectored and Non Vectored interrupt:

3. Maskable and Non Maskable interrupts.

.c

The interrupts initiated by external hardware by sending an appropriate signal to the interrupt pin
of the processor is called hardware interrupt. The 8086 processor has two interrupt pins INTR
and NMI. The interrupts initiated by applying appropriate signal to these pins are called
hardware interrupts of 8086. The software interrupts are program instructions. These instructions
are inserted at desired locations in a program. While running a program, if software interrupt
instruction is encountered then the processor initiates an interrupt. The 8086 processor has 256
types of software interrupts. The software interrupt instruction is INT n, where n is the type
number in the range 0 to 255.
5.b. With a neat block diagram, explain the 8259A system connections.
Jan 2015 [9 Marks]
Architecture and Signal Descriptions of 8259A

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The architectural block diagram of 8259A is shown in Fig. 1.1. The functional explanation of
each block is given in the following text in brief.
Interrupt Request Register (IRR)

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The interrupts at IRQ input lines are handled by Interrupt Request Register internally. IRR stores
all the interrupt requests in it in order to serve them one by one on the priority basis.
In-Service Register (ISR)

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This stores all the interrupt requests those are being served, i.e ISR keeps a track of the requests
being served.
Priority Resolver

This unit determines the priorities of the interrupt requests appearing simultaneously. The
highest priority is selected and stored into the corresponding bit of ISR during INTA pulse. The
IR0 has the highest priority while the IR7 has the lowest one, normally in fixed priority mode.

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The priorities however may be altered by programming the 8259A in rotating priority mode.
Interrupt Mask Register (IMR)

This register stores the bits required to mask the interrupt puts. IMR operates on IRR at the
direction of the Priority Resolver.
Interrupt Control Logic

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This block manages the interrupt and interrupt acknowledge sigD8ls to be sent to the CPU for
serving one of the eight interrupt requests. This also accepts interrupt acknowledge (INTA)
signal from CPU that causes the 8259A to release vector address on to the data bus.
Data Bus Buffer

.c

This tristate bidirectional buffer interfaces internal 8259A bus to the microprocessor system data
bus. Control words, status and vector information pass through buffer during read or write
operations.

Read write Control Logic

This circuit accepts and decodes commands from the CPU. This also allows the status of the
8259A to be transferred on to the data bus.
Cascade Buffer/Comparator This block stores and compares the ID's of all the 8259As used in
the system.

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Jan 2015 [3 Marks]

.c

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5.c. List the differences between 8086 and 8088.

Unit-8

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1.a. briefly explain the control word format of 8255 in I/O mode and BSR mode. Give the
control word format to program port A and port C lower as input and port B and port C
upper as output parts in mode 0.
June/July 13 [10 Marks]

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1.b.write an ALP using 8086 instructions to read a byte of data from port A and display its
parity status as 00h or ffh for odd and even parity respectively on port B

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June/July 13 [5 Marks]
.MODEL SMALL

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.DATA
PA EQU 0DE90H
PB EQU 0DE91H
CR EQU 0DE93H
CW DB 82H

MOV AX,@DATA
MOV DS,AX
MOV AL,CW
MOV DX,CR

;send control word

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OUT DX,AL

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.CODE

MOV DX,PB

;PB is input port

IN AL,DX

.c

MOV BL,AL

MOV BH,0

MOV CX,8

NEXT_BIT:ROR AL,1
JNC NEXT
INC BH
NEXT:LOOP NEXT_BIT

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MOV AL,BL
OR AL,AL
JPE DISPFF

DISP:MOV DX,PA

;PA is 0utput port

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OUT DX,AL
CALL DELAY
MOV AL,BH
MOV DX,PA
OUT DX,AL

DISPFF:MOV AL,0FFH
JMP DISP

PUSH SI
PUSH DI

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DELAY PROC NEAR

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MOV AH,4CH
INT 21H

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MOV AL,00H

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MOV si,0FFFFH

B2: MOV di,0FFFFH

B1: dec di

jnz B1
DEC SI
JNZ B2
POP DI

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POP SI
RET
DELAY ENDP

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END

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1.c. List the features of 8254 PIT (programmable interval timer) June/July 13 [5 Marks]

2.a. Explain pin out of 8255 along with different operational modes.

.c

Dec 13/Jan 14 [10 marks]

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Dec 13/Jan 14 [10 marks]

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2.b Explain the structure of IVT with the neat diagram.

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3.a. Explain the different methods of parallel data transfer with figure in a programmable
peripheral interface.
Dec 2012 [10 Marks]

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SIMPLE INPUT AND OUTPUT

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When you need to get digital data from a simple switch, such as a thermostat, into a
microprocessor, all you have to do is connect the switch to an input port line and read the port.
The thermostat data is always present and ready, so you can read it at any time.
SIMPLE STROBE I/O

.c

In many application, valid data is present on an external device only at a certain time,so it must
be read in at that time. An example of this is the ASCII encoded keyboard. When a key is
pressed, circuitry on the keyboard sends out the ASCII code for the pressed on eight parallel data
lines, and then sends out a strobe signal on another line to indicate that valid data is present on
the eight data lines.

SINGLE HANDSHAKE I/O


Figure shows the circuit connections and fig shows some example for a handshake data transfer
from a peripheral device to a micoprocessor.
The peripheral outputs some parallel data and sends an STB signal to the microprocessor. The
microprocessor detects the asserted STB signal on a polled or interrupt basis and reads in the

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byte of data. Then the microprocessor sends an Acknowledgement signal(ACK) to the peripheral
to indicate that the data has been read and that peripheral can send the next byte of data. From
the viewpoint of the microprocessor, this operation is referred to as a handshake or strobed input.

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DOUBLE-HANDSHAKE DATA TRANSFER

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For data transfers where even more coordination is required between the sending system and the
receiving system, a double handshake is used. The circuit connections are the same as those in
fig 9.2. figure 9.1d shows some example waveforms for a double-handshake input from a
peripheral to a microprocessor.
In these waveforms each signal edge has meaning. The sending device asserts its STB line low to
ask,Arre you ready? the receiving system raises its ACK line high to say, Im ready. The
peripheral device then sends the byte of data and raises its STB line high to say, here is some
valid data for you. After it has read in the data, the receiving system drops its ACK line low to
say, I have the data, thank you, and I await your request ti send the next byte of data.

.c

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3.b. Explain with the internal block diagram of 8255, the different operational modes and
the control word formats.
Dec 2012 [10 Marks]

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Mode 0 : Simple Input or Output

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In this mode, Port A and Port B are used as two simple 8-bit I/O ports and Port C as two 4-bit
I/O ports. Each port (or half-port, in case of Port C) can be programmed to function as simply an
input port or an output port. The input/output features in mode 0 are : Outputs are latched, Inputs
are not latched. Ports do not have handshake or interrupt capability.
Mode 1 : Input or Output with handshake

.c

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In mode 1, handshake signals are exchanged between the microprocessor and peripherals prior to
data transfer. The ports (A and B) function as 8-bit I/O ports. They can be configured either as
input or output ports. Each port (Port A and Port B) uses 3 lines from port C as handshake
signals. The remaining two lines of port C can be used for simple I/O functions. Input and output
data are latched and Interrupt logic is supported.

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Mode 1 : Output control signals

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Mode 2 : Bidirectional Data Transfer

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This mode is used primarily in applications such as data transfer between the two computers or
floppy disk controller interface. Port A can be configured as the bidirectional port and Port B
either in mode 0 or mode 1. Port A uses five signals from Port C as handshake signals for data
transfer. The remaining three lines from Port C can be used either as simple I/O or as handshake
signals for Port B.
4.a. With a neat block diagram, explain the internal block diagram of 8255A.
Jan 2015 [8 Marks]

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The 8255 is a widely used, programmable parallel I/O device. It can be programmed to transfer
data under data under various conditions, from simple I/O to interrupt I/O. It is flexible, versatile
and economical (when multiple I/O ports are required). It is an important general purpose I/O
device that can be used with almost any microprocessor.

.c

The 8255 has 24 I/O pins that can be grouped primarily into two 8 bit parallel ports: A and B,
with the remaining 8 bits as Port C. The 8 bits of port C can be used as individual bits or be
grouped into two 4 bit ports : CUpper (CU) and CLower (CL). The functions of these ports are
defined by writing a control word in the control register.

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Jan 2015 [2 Marks]

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4.b. Design a control word for interfacing keyboard.

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Control word of keyboard interface is 1000 0000=80H

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4.c. Write on assembly level program to interface logic controller for multiplication of two
8-bit numbers.
Jan 2015 [10 Marks]
DISPLAY MACRO MSG
LEA DX,MSG

.c

MOV AH,09H

INT 21H

ENDM

.MODEL SMALL
.STACK 64
.DATA

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PA EQU 0DE90H
PB EQU 0DE91H
CR EQU 0DE93H

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CW DB 82H

M2 DB 10,13,"SET VALUE OF Y$"


.CODE
MOV AX,@DATA
MOV DS,AX
MOV DX,CR

OUT DX,AL
DISPLAY M1
MOV AH,08H
INT 21H

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MOV DX,PB

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MOV AL,CW

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M1 DB 10,13,"SET VALUE OF X$"

IN AL,DX

MOV BL,AL

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DISPLAY M2

MOV AH,08

INT 21H

MOV DX,PB
IN AL,DX
MUL BL
MOV DX,PA

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OUT DX,AL
CALL DELAY
MOV AL,AH

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MOV DX,PA
OUT DX,AL

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MOV AH,4CH
INT 21H

DELAY PROC NEAR


PUSH SI

MOV si,0FFFFH
B2: MOV di,0FFFFH
B1: dec di

DEC SI
JNZ B2
POP DI

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POP SI

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jnz B1

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PUSH DI

RET

DELAY ENDP

END

5.c Explain how a 3-8 line decoder could be used to interfaced eight 8K memory chips.

June 2014[08 marks]

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The 3-to-8 Line Decoder (74LS138)

Note that all three Enables (G2A, G2B, and G1) must be active, e.g. low, low and high,
respectively.

Each output of the decoder can be attached to an 2764 EPROM ( 8K X 8 ).

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5.a Explain different signals of 8255 PP and control words.

.c

marks]

June 2014[08

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5.b Explain with a neat diagram the interfacing of stepper motor to 8086 using 8255 in

detail

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STEPPER MOTOR

June 2014[06 marks]

.c

A stepper motor is a brushless, synchronous electric motor that converts digital pulses into mechanical
shaft rotation. Every revolution of the stepper motor is divided into a discrete number of steps, and the
motor must be sent a separate pulse for each step.

INTERFACING STEPPER MOTOR

Fig. 1 shows how to interface the Stepper Motor to microprocessor. As you can see the stepper motor is
connected with Microprocessor output port pins through a ULN2803A array. So when the microprocessor
is giving pulses with particular frequency to ls293A, the motor is rotated in clockwise or anticlockwise.

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Fig. 1 Interfacing Stepper Motor to Microprocessor

5.c Explain the working of different blocks of 8254 PIT with a neat figure

.c

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marks]

June 2014[06

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Basic operation:
1. The user inputs a control word and then an initial count. The Control Word itself specifies
which Counter is being programmed and which counting Mode is desired.
2. Counting is enabled via the GATE input.
3. Either at the end of a count or during the count, transitions occur on the Counter OUT pin.
4. These OUT pin transitions are used to do things in the system.
5. The types of OUT pin transitions depend on the Mode which was programmed.

.c

Major device blocks


Data bus buffer:
1. 3-state, bi-directional, 8-bit buffer.
2. Interfaces the 8254 to the system bus.

Read Write Logic Block:


1. The Read/Write Logic Block accepts inputs from the system bus and generates control signals
for the other functional blocks of the 8254.
2. A1 and A0 select one of the three counters or the Control Word Register to be read from or
written into.
3. A low on RD# tells the 8254 that the CPU is reading one of the counters.
4. A low on WR# tells the 8254 that the CPU is writing either a Control Word or an initial count.
5. Both RD# and WR# are qualified by CS#.
Control Word Register:
1. This register is selected by the Read/Write Logic when A1,A0=11.
2. If the CPU then does a write operation to the 8254, the data is stored in the Control Word

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Register and is interpreted as a Control Word used to define the operation of the counters.
3. The Control Word Register can only be written to. Status information is available with the
Read-Back command.

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Counters:
1. There are three Counters. Each is fully independent of the others. Each Counter may operate
in a different Mode.
2. Each counter is a 16-bit synchronous down counter.
3. After power-up, the count value and output of all Counters are undefined.
4. Each counter must be programmed before it can be used.
5. Unused counters need not be programmed.
6. Counters are programmed by writing a Control Word and then an initial count.
7. GATE=1 enables counting, GATE=0 disables counting.

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Counter description
Counting element, OLm, OLl, OL:
1. The actual Counter is "CE" in figure 5.
2. OLm and OLl are two 8-bit latches. OL is "Output Latch" The subscripts m and l stand for
"Most significant byte" and "Least significant byte". Both are normally referred to as one unit
and called just OL. These latches "follow" the CE as it counts.
3. If a suitable Counter Latch Command is sent to the 8254, the latches capture the present count
until read by the CPU. Once read, the latches return to "following" the CE.
4. One latch at a time is enabled by the counter's control logic to drive the internal bus. This is
how the 16-bit counter communicates over the 8-bit bus.
5. The CE itself cannot be read. If the user wants to read the count, it is the OL that is being read.

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