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Hi folks,
here are the questions I have compiled while reading books/articles etc...
I hope these questions help you in understanding/reasoning the subject ......
1.Why does a CMOS inverter has finite gain in transition region ?
or ( to put it the other way)
What is the reason for not having a ideal VTC for a CMOS inverter?
2.In what way is Memory design different from Random logic design?
or ( to put it the other way)
How is Memory design different from combo logic design?
3.Why don't we use a FlipFlop (say a D flop) as a memory cell?
4.Why is it essential to have data stable in the metastable window period of
a FlipFLop/Latch? What is the actual cause forcing such requirement (
setup/hold time requirements)?
5.Why Sub-threshold leakage current increases with decrease in Vt?
6.Is Technology scaling all advantageous? Explain.
7.What happens to the VTC of a CMOS inverter if Vdd is reduced ?
8.What is the optimum value of Vdd for a CMOS inverter?
9.Why BiCMOS in not being used extensively inspite of it's advantages over
CMOS?
10.A CMOS inverter has it's o/p fed back to it's input. What will be the
function of the ckt?
11.There is a chain of inverters with the o/p fedback to i/p. What will be
the frequency of oscillation if Tp of the inverter is 2ns and the no: of
inverters is
a) 3 b) 25 c) 10
12)For routing power in a process techhnology that supports 3 level metal
layers, which metal layer will you choose and why ?
Hi folks,
I have collected these QUestions from frens, web, campus experience .....
If u have Questions please send me @ my mail id. I'll update the blog.
1. A BJT has it's base connected to i/p ( sinusoidal signal with Vp = 5v , Vpp
= 10v), collector
tied to Vcc = 5v and emitter connected to Vee= -5v through 100K resistor.
Plot output. [MOTOROLA]
2. A PLL has it's direct i/p from a divide by N counter and feedback i/p from
divide by M
counter. what would be the output frequency? [SASKEN]
3.For low noise applications Transistors used should be wide or narrow ? why
? [Analog]
4.What is Miller Compensation? [TI]
5.For an Op-Amp, offset at the input is 5mv.If Voltage Gain is 10,000 and
Vsat = +/-15v,
what is the o/p voltage with both i/ps of Op-Amp are shorted. [intel]
6.An Op-Amp has it's o/p connected back to it's non-inverting terminal and
input is given to
the same i/p terminal with the other i/p terminal grounded. what will be
the o/p or th circuit acts as a____________ ? [TI]
7.A BJT has it's base connected to a 1V dc battery through 52K resistor, it's
emitter is grounded
and collector is connected to Vcc=10v through 10K(Rc) resistor.Calculate the
currnet flowing through resistor,Rc(10K ) ,if Beta = 200. [MOTOROLA]
8.Given a RL ckt ( with o/p taken across L ) and a square wave applied as
i/p to the series RL ckt with peak value of +/- Vmax. Plot the o/p for
different normalized time constants ( small, medium, large). [ST]
9.Given an Op-Amp ckt with i/p applied to non-inverting i/p terminal and
o/p fedback to oinverting terminal with resistive feedback and beta(
feedback factor equal to 1/2).
Input applied is sinusoidal signal with peak value of 4 V. Op-Amp supply
voltages are +/-5V.
Plot output. [ST].
10.If X1(t) is a ectangular pulse from -T to T with amplitude of 1 and X2(t) is
a series of three delta functions at -3T O and 3T.Plot X1(t) * X2(t) where * is
INV is a inverter.
a) Latch b) Amplifier c) Schmitt trigger [Analog]
12.In a BJT ckt i/p to the base of the BJT is given through a resistor to
which a capacitor is connected in parallel.What is the capacitor used for
a) to improve switching b) dc coupling c) ac coupling [Analog]
# posted by blograma @ 3:16 AM 0 comments
COMPUTER ORGANIZATION:
Hi folks,
I thought, Computer organization is required for a VLSI design
engineer.Intel,amd,....do processor design and expect you to have "what is
what" knowledge, you may not be doing the architecture development but
nothing wrong in knowing "what is what "......
these are the Questions I have collected from my frens (and personal
experience).
1.What is a Cache? What is it used for? What is the principle behind it?
2.what should be the size of a cache -- large/small?
3. What is a cache hit and cache hit ratio?
4. what are the various mappings used in Cache?
( direct, assosciative , set-assosciative )
5.What are the stages of a 5 stage DLX pipeline?
24.Processor is busy , but you want to perform some task . How will you do
that?
25.What is ACBF ( hex number) divided by 16 , give Quotient and remainder?
26.Given cache size is 64KB , Block size is 32B and the cache is two-way set
assosciative.
For a 32-bit physical address, give the division between block offset, index
and tag.
27.Differentiate RISC and CISC. Is RISC always fast?
28. How is a DSP different from a GPP?
Give me feedback
# posted by blograma @ 2:26 AM
Hi folks,
the Questions I am posting here are what I have collected from my friends,
web, my campus tests. I thank my frens for their help.
These Questions are asked by Companies like
Motorola,TI,Intel,Nvidia,Atrenta,ST,Agilent,
Sasken,AMD,.......
DIGITAL DESIGN
1.Using a 2:1 Mux realize the following
a) NOT gate b) AND gate c) OR gate d) Ex-OR gate e) Ex-NOR gate
f) NAND gate g) NOR gate h) Latch i) FlipFlop
hint : Use Shannon's Expansion , get expression in the form of Mux equation
muxout = sel_bar * Input0 + sel*Input1.
2.Using Combo logic Multiply Clock by two ( freq of clock at o/p = 2* freq at
i/p)
3.Realize transistor level circuit for