ST.

MARTINS ENGINEERING COLLEGE

Dhulapally, Quthbullapur, Secunderabad- 14.
Department of Electronics and Communication Engineering
Tutorial Questions
Digital Design using Verilog HDL
UNIT-I
1

Discuss different levels of design description in Verilog with suitable examples

Discuss the different driving strengths in Verilog with strength level

What is the need for simulation and synthesis

Discuss the Various Operators in Verilog with example

Explain different parameters used in Verilog with example

What are the Logic levels used in verilog

What are different Scalars and Vectors with example

Discuss white space characters with examples

Discuss the Numbers used in verilog with examples

10

With an example explain how the comments are declared in verilog

UNIT-II
1.

How the basic circuit can be constructed and how the programming can
be done in verilog

2.

Write a verilog program for full adder in gate level modeling

3.

Write a verilog program for full adder using two half adders in gate level
modeling

4.

Write a verilog program for master-slave j-k flipflop using gate level
modeling

5.

Describe the different strengths and contention resolutions

6.

Write a verilog program and testbench for full subtractor in gate level
modeling

7.

Write a verilog program and testbench for full subtractor using two half
subtractors in gate level modeling

8.

Explain the design of flip-flops with gate primitives

9.

Write a Verilog Program and testbench for AOI gate in Gate Level
Modelling

10.

What is the difference between Always and Initial block

UNIT-III

1.

With an example explain how the INITIAL construct used in Verilog

2.

Explain how the ALWAYS statements are used in Verilog

3.

Explain the blocking and non-blocking assignments with the help of an

example

4.

Explain the repeat construct with an example

5.

With an example explain the assign-deassign constructs

6.

Explain briefly about parallel blocks

7.

Discuss about force-release construct with an example

8.
9.

Write the difference between while loop and forever loop

Write a verilog program for priority encoder in behavioural modeling

10.

Write a program for 4:1 mux using if-else-if construct using verilog and

also testbench
UNIT-IV
1.

What is the difference between gate level modeling and dataflow

modeling

2.

Explain about the continuous assignment structures using data flow

modeling

3.

Write a verilog program for full adder using two half adders in data flow
style of modeling

4.

Write a verilog program and also testbench for active low 2:4 decoder in
data flow modeling

5.

Write a verilog program and testbench for binary to gray codeconverter

using dataflow modeling

6.

Write a verilog program and testbench for j-k flipflop using dataflow
modeling

7.

Write a verilog program and testbench for 4-bit comparator usin dataflow
style of modeling

8.

Explain about basic transistor switches

9.

Explain the operation of CMOS inverter and write the program and
testbench for the same

10.

Write a verilog program and testbench for CMOS NAND gate using switch level modeling
UNIT-V

1.

Explain different types of path delays in verilog

2.

Explain User defined primitives. Explain with an example program

3.

Explain briefly about the Hierarchical access

4.

Explain the Moore design with the help of an example program

5.

Explain the mealy design with the help of a sequence detector

6.

Write the difference between the combinational and sequential circuits

7.
8.

Discuss briefly about the module parameters

Design Moore circuit to detect the sequence of 11001

9.

Write the differences between Mealy and Moore designs

10.

Write the differences between the UDPs and general module structure