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Analog Multiplier
AD633
Data Sheet
FEATURES
4-quadrant multiplication
Low cost, 8-lead SOIC and PDIP packages
Completeno external components required
Laser-trimmed accuracy and stability
Total error within 2% of full scale
Differential high impedance X and Y inputs
High impedance unity-gain summing input
Laser-trimmed 10 V scaling reference
X1
1
X2
A
1
10V
Y1
00786-023
1
Y2
Figure 1.
APPLICATIONS
Multiplication, division, squaring
Modulation/demodulation, phase detection
Voltage-controlled amplifiers/attenuators/filters
GENERAL DESCRIPTION
The AD633 is a functionally complete, four-quadrant, analog
multiplier. It includes high impedance, differential X and Y inputs,
and a high impedance summing input (Z). The low impedance
output voltage is a nominal 10 V full scale provided by a buried
Zener. The AD633 is the first product to offer these features in
modestly priced 8-lead PDIP and SOIC packages.
The AD633 is laser calibrated to a guaranteed total accuracy of
2% of full scale. Nonlinearity for the Y input is typically less
than 0.1% and noise referred to the output is typically less than
100 V rms in a 10 Hz to 10 kHz bandwidth. A 1 MHz bandwidth,
20 V/s slew rate, and the ability to drive capacitive loads make
the AD633 useful in a wide variety of applications where
simplicity and cost are key concerns.
The versatility of the AD633 is not compromised by its simplicity.
The Z input provides access to the output buffer amplifier, enabling
the user to sum the outputs of two or more multipliers, increase
the multiplier gain, convert the output voltage to a current, and
configure a variety of applications. For further information, see
the Multiplier Application Guide.
Rev. K
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Document Feedback
AD633
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Specifications..................................................................................... 3
Error Sources................................................................................. 8
REVISION HISTORY
3/15Rev. J to Rev. K
Changes to General Description Section ...................................... 1
Changes to Figure 12 Caption and Figure 14 Caption ................ 9
Added Model Results Section, Examples of DC, Sin, and
Pulse Solutions Using Multisim Section, and Figure 24
Through Figure 29, Renumbered Sequentially........................... 13
Added Examples of DC, Sin, and Pulse Solutions Using
PSPICE Section, Examples of DC, Sin, and Pulse Solutions
Using SIMetrix Section, and Figure 30 Through Figure 37 ...... 14
Added Figure 38 Through Figure 41 ........................................... 15
9/13Rev. I to Rev. J
Reorganized Layout ............................................................ Universal
Change to Table 1 ............................................................................. 3
Changes to Figure 4 .......................................................................... 6
Added Figure 10, Renumbered Sequentially ................................ 7
Changes to Figure 15 ........................................................................ 9
Changes to Figure 20 ...................................................................... 10
Changes to Figure 31 ...................................................................... 14
Added Figure 32.............................................................................. 15
2/12Rev. H to Rev. I
Changes to Figure 1 .......................................................................... 1
Changes to Figure 2 .......................................................................... 5
Changes to Generating Inverse Functions Section ...................... 8
Changes to Figure 15 ........................................................................ 9
Added Evaluation Board Section and Figure 23 to Figure 29,
Rev. K | Page 2 of 20
Data Sheet
AD633
SPECIFICATIONS
TA = 25C, VS = 15 V, RL 2 k.
Table 1.
Parameter
TRANSFER FUNCTION
MULTIPLIER PERFORMANCE
Total Error
TMIN to TMAX
Scale Voltage Error
Supply Rejection
Nonlinearity, X
Nonlinearity, Y
X Feedthrough
Y Feedthrough
Output Offset Voltage2
DYNAMICS
Small Signal Bandwidth
Slew Rate
Settling Time to 1%
OUTPUT NOISE
Spectral Density
Wideband Noise
OUTPUT
Output Voltage Swing
Short Circuit Current
INPUT AMPLIFIERS
Signal Voltage Range
Offset Voltage (X, Y)
CMRR (X, Y)
Bias Current (X, Y, Z)
Differential Resistance
POWER SUPPLY
Supply Voltage
Rated Performance
Operating Range
Supply Current
1
Conditions
Min
W=
10 V X, Y +10 V
AD633J, AD633A
Typ
Max
(X1 X2 )(Y1 Y2 ) + Z
10 V
1
3
0.25%
0.01
0.4
0.1
0.3
0.1
5
SF = 10.00 V nominal
VS = 14 V to 16 V
X = 10 V, Y = +10 V
Y = 10 V, X = +10 V
Y nulled, X = 10 V
X nulled, Y = 10 V
Unit
21
11
0.41
11
0.41
501
% full scale
% full scale
% full scale
% full scale
% full scale
% full scale
% full scale
% full scale
mV
VO = 0.1 V rms
VO = 20 V p-p
VO = 20 V
1
20
2
MHz
V/s
s
f = 10 Hz to 5 MHz
f = 10 Hz to 10 kHz
0.8
1
90
V/Hz
mV rms
V rms
111
RL = 0
30
Differential
Common mode
101
101
VCM = 10 V, f = 50 Hz
60
5
80
0.8
10
401
301
2.01
15
81
Quiescent
181
61
V
mA
V
V
mV
dB
A
M
V
V
mA
This specification was tested on all production units at electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum
specifications are guaranteed; however, only this specification was tested on all production units.
Allow approximately 0.5 ms for settling following power on.
Rev. K | Page 3 of 20
AD633
Data Sheet
Rating
18 V
500 mW
18 V
Indefinite
65C to +150C
THERMAL RESISTANCE
0C to 70C
40C to +85C
300C
1000 V
For supply voltages less than 18 V, the absolute maximum input voltage is
equal to the supply voltage.
Package Type
8-Lead PDIP
8-Lead SOIC
ESD CAUTION
Rev. K | Page 4 of 20
JA
90
155
Unit
C/W
C/W
Data Sheet
AD633
X2
Y1
Y2
1
A
1
10V
1
+VS
Y1
Y2
VS
VS
AD633JN/AD633AN
(X1 X2)(Y1 Y2)
10V
+Z
W=
Pin No.
1
2
3
4
5
6
7
8
1
10V
X2
X1
+VS
AD633JR/AD633AR
00786-001
W=
Description
X Multiplicand Noninverting Input
X Multiplicand Inverting Input
Y Multiplicand Noninverting Input
Y Multiplicand Inverting Input
Negative Supply Rail
Summing Input
Product Output
Positive Supply Rail
00786-002
X1
Rev. K | Page 5 of 20
Mnemonic
Y1
Y2
VS
Z
W
+VS
X1
X2
Description
Y Multiplicand Noninverting Input
Y Multiplicand Inverting Input
Negative Supply Rail
Summing Input
Product Output
Positive Supply Rail
X Multiplicand Noninverting Input
X Multiplicand Inverting Input
AD633
Data Sheet
90
CL = 1000pF
80
CL = 0.01F
CMRR (dB)
10
70
50
20
40
00786-003
NORMAL
CONNECTION
100k
1M
FREQUENCY (Hz)
30
20
100
10M
10k
FREQUENCY (Hz)
1k
100k
1M
10k
100k
600
500
400
200
60
00786-004
300
40
20
20
40
60
80
TEMPERATURE (C)
100
120
1.0
0.5
00786-007
700
00786-006
30
10k
0
10
140
100
1k
FREQUENCY (Hz)
14
1k
12
OUTPUT, RL 2k
10
ALL INPUTS
8
6
00786-005
TYPICAL
FOR X, Y
INPUTS
60
4
8
10
12
14
16
18
PEAK POSITIVE OR NEGATIVE SUPPLY (V)
Y-FEEDTHROUGH
100
X-FEEDTHROUGH
10
0.1
10
20
00786-008
100
1k
10k
100k
FREQUENCY (Hz)
Rev. K | Page 6 of 20
1M
10M
Data Sheet
AD633
OUTPUT (mV)
0.5
1.0
1.5
2.0
2.5
3.0
TIME (Minutes)
3.5
4.0
4.5
5.0
00786-009
Figure 10. Typical VOS vs. Time, For Five Minutes Following Power Up
Rev. K | Page 7 of 20
AD633
Data Sheet
FUNCTIONAL DESCRIPTION
The AD633 is a low cost multiplier comprising a translinear
core, a buried Zener reference, and a unity-gain connected
output amplifier with an accessible summing node. Figure 1
shows the functional block diagram. The differential X and Y
inputs are converted to differential currents by voltage-to-current
converters. The product of these currents is generated by the
multiplying core. A buried Zener reference provides an overall
scale factor of 10 V. The sum of (X Y)/10 + Z is then applied
to the output amplifier. The amplifier summing Node Z allows
the user to add two or more multiplier outputs, convert the
output voltage to a current, and configure various analog
computational functions.
Inspection of the block diagram shows the overall transfer
function is
(X1 X2 )(Y1 Y2 ) + Z
10 V
(1)
300k
50k
1k
50mV
TO APPROPRIATE
INPUT TERMINAL
(FOR EXAMPLE, X2, Y2, Z)
VS
Rev. K | Page 8 of 20
00786-010
W=
ERROR SOURCES
Data Sheet
AD633
APPLICATIONS INFORMATION
The AD633 is well suited for such applications as modulation
and demodulation, automatic gain control, power measurement,
voltage-controlled amplifiers, and frequency doublers. These
applications show the pin connections for the AD633JN (8-lead
PDIP), which differs from the AD633JR (8-lead SOIC).
+15V
0.1F
R
+15V
0.1F
+
X2
Y1
Z 6
Y2
VS 5
W=
W 7
AD633JN
Y
INPUT
00786-011
+15V
Y1
Z 6
Y2
VS 5
AD633JN
VS 5
E2
10V
10 V
E
(1 cos 2 t )
20 V
0.1F
E < 0V
1
(sin 2 )
2
10k
AD711
3
(3)
Rev. K | Page 9 of 20
X1
+VS 8
X2
W 7
AD633JN
4
(2)
0.1F
0.01F
+15V
+15V
(E sin t )
(5)
10k
15V
(4)
W = (10E )V
0.1F
R2
3k
00786-012
W=
Y2
0.1F
W 7
X2
Z 6
1
E
(
)E(
)
(10 V ) 2 sin 0t + 45 2 sin 0t + 45
E
(
)
=
(40 V ) sin 2 t
Y1
E2
10V
W=
Figure 12. Basic Multiplier Connections (See the Model Results Section)
+VS 8
W=
R1
1k
15V
X1
W 7
Figure 14. Bounceless Frequency Doubler (See the Model Results Section)
OPTIONAL SUMMING
INPUT, Z
X2
15V
0.1F
0.1F
+VS 8
X1
+VS 8
Y1
Z 6
Y2
VS 5
15V
1N4148
0.1F
0.1F
15V
W = (10V)E
000786-014
X
INPUT
X1
AD633JN
MULTIPLIER CONNECTIONS
Figure 12 shows the basic connections for multiplication. The X
and Y inputs normally have their negative nodes grounded, but
they are fully differential, and in many applications, the grounded
inputs may be reversed (to facilitate interfacing with signals of a
particular polarity while achieving some desired output polarity),
or both may be driven.
00786-013
AD633
Data Sheet
E
EX
R
10k
0.1F
EX
X1
+VS 8
X2
W 7
Y1
Z 6
Y2
VS 5
AD633JN
AD711
3
+15V
0.1F
0.1F
+15V
W' = 10V
00786-015
15V
15V
E
EX
Y
INPUT
X1
+VS 8
X2
W 7
W=
AD633JN
R1
Y1
Z 6
Y2
VS 5
+S
0.1F
MODULATION +
INPUT
EM
X2
W 7
Y1
Z 6
Y2
VS 5
Figure 20 shows a single multiplier used to build a voltagecontrolled, low-pass filter. The voltage at Output A is a result of
filtering ES. The break frequency is modulated by EC, the control
input. The break frequency, f2, equals
EC
(8)
10 ( 2 RC )
f2 f1
+15V
X2
W 7
Y1
Z 6
Y2
VS 5
IO =
AD633JN
1
R
0.1F
CONTROL
INPUT EC
X1
+VS 8
X2
W 7
Y1
Z 6
Y2
VS 5
AD633JN
0.1F
10V
1k R 100k
6dB/OCTAVE
OUTPUT A
OUTPUT B
1 + T1P
1 + T2P
R
1
OUTPUT A =
1 + T2P
C
1
T1 =
= RC
1
OUTPUT B =
15V
T2 =
1
2
10RC
EC
00786-017
Y
INPUT
+VS 8
R
+15V
SIGNAL
INPUT ES
0.1F
X
INPUT
X1
EC sin t
CURRENT OUTPUT
EM
10V
W = 1+
0.1F
0.1F
00786-016
+VS 8
15V
f2
15V
X1
AD633JN
CARRIER
INPUT
EC sin t
R2
S
00786-018
R
10k
(7)
+15V
0.1F
1 X1 X2Y1 Y2
R
10 V
IO
(6)
00786-019
W 10 V
The voltage at Output B, the direct output of the AD633, has the
same response up to frequency f1, the natural breakpoint of RC
filter, and then levels off to a constant attenuation of f1/f2 = 10/EC
f1
Rev. K | Page 10 of 20
1
2 RC
(9)
Data Sheet
AD633
f1 f2
0
+15V
0.1F
SIGNAL
INPUT ES
X1
+VS 8
X2
W 7
Y1
Z 6
Y2
VS 5
OUTPUT B
AD633JN
C
OUTPUT A
R
00786-020
0.1F
15V
D5
1N5236
D1
1N914
D3
1N914
(10V) cos t
D2
1N914
D4
1N914
+15V
0.1F
R1
1k
EC
X1
+VS 8
X2
W 7
Y1
Z 6
0.1F
R2
16k
AD633JN
Y2
C2
0.01F
+15V
C1
0.01F
VS 5
X1
+VS 8
X2
W 7
Y1
Z 6
Y2
VS 5
AD633JN
R3
330k
R5
16k
0.1F
0.1F
(10V) sin t
C3
0.01F
15V
15V
Rev. K | Page 11 of 20
R4
16k
f=
EC
= kHz
10V
00786-021
CONTROL
INPUT EC
OUTPUT B
+6dB/OCTAVE
OUTPUT A
AD633
Data Sheet
R2
1k
R3
10k
R4
10k
AGC THRESHOLD
ADJUSTMENT
+15V
0.1F
+15V
0.1F
1
+VS 8
X1
X2
Y1
Z 6
Y2
VS 5
C1
1F
1/2
AD712
W 7
R5
10k
AD633JN
E
A1
R6
1k
0.1F
15V
C2
0.02F
C3
0.2F
CC COMMON 8
VIN
+VS 7
CF
OUTPUT 6
VS
+15V
0.1F
AD736
0.1F
R10
10k
CAV 5
15V
C4
33F
A2
6
1N4148
7
1/2
AD712
4
+15V
R8
50k
0.1F
OUTPUT
LEVEL
ADJUST
00786-022
R9
10k
EOUT
15V
Rev. K | Page 12 of 20
Data Sheet
AD633
00786-126
MODEL RESULTS
00786-127
00786-128
00786-124
Figure 25. Circuit to Multiply Two Integers Response Graph Displayed in Multisim
(2 V 4 V)/10 V = 0.8 V
Rev. K | Page 13 of 20
00786-129
00786-125
AD633
Data Sheet
00786-130
00786-131
00786-134
00786-135
00786-136
00786-132
00786-137
00786-133
Rev. K | Page 14 of 20
AD633
00786-140
00786-138
Data Sheet
00786-139
00786-141
Rev. K | Page 15 of 20
AD633
Data Sheet
EVALUATION BOARD
00786-026
00786-024
00786-027
00786-028
Figure 43 through Figure 46 are the signal, power, and groundplane artworks, and Figure 47 shows the component and circuit
side silkscreen. Figure 48 shows the assembly.
Rev. K | Page 16 of 20
AD633
00786-031
00786-029
Data Sheet
00786-030
+V
+
+
+V
IN
SEL_Y1
X2_TP
IN
GND
2
TEST
VS
3
C1
0.1F
Z_IN
IN
GND
G6
TEST
AD633ARZ
Y1 DUT1 X2
Y2
VS
Z
GND
X1_TP
X1
+VS
W
X1_IN
(DENOM)
IN
SELX1
R1
100
GND
7
TEST
+V
Y2_TP
SEL_Y2
+V
X2_IN
C2
0.1F
FUNCT(2)
TEST
G5
X2_IN
IN
SEL_X2
Y1_TP
Y2_TP
SEL_Y2
G4
C6
10F
25V
FUNCT(1)
TEST
Y2_IN
G3
Y1_IN
GND
G2
3
R2
10k
+
Z2
2 AD711
M
R3
10k
NOM_TP
C3
0.1F
6
FUNCTION SWITCH S1
MULTIPLY:
[(X1-X2)(Y1-Y2)/10V] + Z
4
C4
0.1F
DIVIDE:
10V (NUM/DENOM)
NUMERATOR
S1
M
OUT_TP
Rev. K | Page 17 of 20
OUT
00786-032
C5
10F
25V
G1
AD633
Data Sheet
POWER SUPPLY
X INPUT DC
VOLTAGE
Y INPUT DC
VOLTAGE
00786-033
OUT DMM
Rev. K | Page 18 of 20
Data Sheet
AD633
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
070606-A
8
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45
8
0
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
Rev. K | Page 19 of 20
012407-A
4.00 (0.1574)
3.80 (0.1497)
AD633
Data Sheet
ORDERING GUIDE
Model1
AD633ANZ
AD633ARZ
AD633ARZ-R7
AD633ARZ-RL
AD633JN
AD633JNZ
AD633JR
AD633JR-REEL
AD633JR-REEL7
AD633JRZ
AD633JRZ-R7
AD633JRZ-RL
AD633-EVALZ
1
Temperature Range
40C to +85C
40C to +85C
40C to +85C
40C to +85C
0C to 70C
0C to 70C
0C to 70C
0C to 70C
0C to 70C
0C to 70C
0C to 70C
0C to 70C
Package Description
8-Lead Plastic Dual-in-Line Package [PDIP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel
8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel
8-Lead Plastic Dual-in-Line Package [PDIP]
8-Lead Plastic Dual-in-Line Package [PDIP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel
8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel
8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel
Evaluation Board
Rev. K | Page 20 of 20
Package Option
N-8
R-8
R-8
R-8
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8