Digital System Design

Dr. Oday A.L.A Ridha

University of Baghdad 2010
Syllabus
-Digital system in general;
-Simplification of logic circuits;
-Combinational circuit design;
-Design using programmable logic circuits such as ROM, PLA, PAL and GAL
-Design of synchronous sequential circuit;
-Algorithmic state machine;
-Design of asynchronous sequential circuit;
-Microprocessor and microcontroller based systems.
References
1. M. Morris Mano, Digital design, Prentice/ Hall International, 1984.
2. Fredreck J. Hill and Gerald R. Peterson, Digital logic and microprocessors.
3. Malvino, Digital principles and applications.
4. Tony R. Kuphaldt, Lessons In Electric Circuits, Volume IV Digital, 2005.
5. Others

Digital System
Digital design is concerned with the design of digital electronic circuits. The subject is
also known by other names such as logic design, switching circuits, digital logic, and
digital systems. Digital circuits are employed in the design of systems of digital
computers, electronic calculators, digital control devices, digital communication
equipments, and many other applications that required electronic digital hardware.

Basic elements of the digital systems

The basic elements of any digital system are logic gates. These gates are:
1- NOT gate (inverter)
Truth table

X
0
1

Z
1
0

Z=X
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2- AND gate (multiplication)

x
y

Z = X Y

X
0
0
1
1

Truth table
Y
0
1
0
1

Z
0
0
0
1

X
0
0
1
1

Truth table
Y
0
1
0
1

Z
0
1
1
1

3- OR gate (sum)

x
y

Z = X +Y
Positive and negative logic

There are two choices for logic-level assignment. Choosing the high-level H to
represent logic-1 defines a positive logic system. Choosing the low-level L to represent
logic-1 defines a negative logic system.

ByDr.OdayA.L.ARidha

Logic
value

Signal
value

Logic
value

Signal
value

a) Positive logic

b) Negative logic

Example:

Truth table
Y

a) if we use positive logic system

Truth table
Y

x
y

z
NAND gate

b) if we use negative logic system

Truth table
Y

ByDr.OdayA.L.ARidha

x
y

NOR gate

Simplification of logic circuits

Logic circuits can be simplified using one or combination of the following methods
1) Boolean algebra
2) Karnaugh mapping
3) Tabular method
Boolean algebra
Like "normal" algebra, Boolean algebra uses alphabetical letters to denote
variables. Unlike "normal" algebra, though, Boolean variables are always CAPITAL
letters, never lower-case. Because they are allowed to possess only one of two possible
values, either 1 or 0, each and every variable has a complement: the opposite of its value.
For example, if variable "A" has a value of 0, then the complement of A has a value of 1.
Boolean notation uses a bar above the variable character to denote complementation.
Basic Boolean identities:
a) Additive (equivalent to OR logic function)
1) A + 0 = A
2) A + 1 = 1
3) A + A = 1
4) A + A = A
b) Multiplicative (equivalent to AND logic function)
1) A 1 = A
2) A 0 = 0
3) A A = A
4) A A = 0
c) Double complement
A=A

Basic Boolean algebraic properties:

1)
2)
3)
4)

A + B = B + A (commutative property of addition)

A B = B A (commutative property of multiplication)
A + ( B + C ) = ( A + B) + C (associative property of addition)
A( B C ) = ( A B )C (associative property of multiplication)

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5) A( B + C ) = A B + A C (distributive property)
Boolean rules are
1) A + AB = A
2) A + A B = A + B
3) ( A + B)( A + C ) = A + BC
DeMorgan's Theorems
A mathematician named DeMorgan developed a pair of important rules regarding
group complementation in Boolean algebra.
DeMorgan's theorem may be thought of in terms of breaking a long bar symbol.
When a long bar is broken, the operation directly underneath the break changes from
addition to multiplication, or vice versa, and the broken bar pieces remain over the
individual variables.

Boolean rules for simplification

Boolean algebra finds its most practical use in the simplification of logic circuits. If
we translate a logic circuit's function into symbolic (Boolean) form, and apply certain
algebraic rules to the resulting equation to reduce the number of terms and/or arithmetic
operations, the simplified equation may be translated back into circuit form for a logic
circuit performing the same function with fewer components. If equivalent function may
be achieved with fewer components, the result will be increased reliability and decreased
cost of manufacture.

ByDr.OdayA.L.ARidha

Steps for simplifying logic circuits

Step 1: Convert the logic circuit to a Boolean expression. Label each gate output with a
Boolean sub-expression corresponding to the gates' input signals, until a final expression
is reached at the last gate;
Step 2 : simplify Boolean expression, obtained from first step, using basic rules and
properties of the Boolean algebra;
Step 3: convert simplified Boolean expression to a logic circuit. Evaluate the expression
using standard order of operations: multiplication before addition, and operations within
parentheses before anything else.

Example: simplify the following logic circuit

Solution:
Step 1:
a)

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b)

c)

Step 2:

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Step 3:

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Minterms (standard products) vs. maxterms (standard sums)

For a logic circuit with n input variables there are 2 n different
combinations (numbers) of the input variables. If the input variables of these
combinations are combined by an AND operation, they are called minterms
or standard products. For the output, minterm is a combination of the input
variables that produces a 1 at the output. Each variable in the minterm is
unprimed if the corresponding bit in the equivalent binary number is a 1 and
prime if it is a 0. In the other words, minterm is an AND term of the n
variables, with each variable being unprimed if the corresponding bit in the
equivalent binary number is a 1 and prime if it is a 0.
On the other hand, If the input variables of these combinations are
combined by an OR operation, they are called maxterms or standard sums.
For the output, maxterm is a combination of the input variables that
produces a 0 at the output. Each variable in the maxterm is primed if the
corresponding bit in the equivalent binary number is a 1 and unprimed if it is
a 0.
Equivalent
binary number

Minterms

Maxterms

term

designation

term

designation

000

X Y Z

m0

X +Y + Z

M0

001

X Y Z

m1

X +Y + Z

M1

010

X Y Z

m2

X +Y + Z

M2

011

X Y Z

m3

X +Y + Z

M3

100

X Y Z

m4

X +Y + Z

M4

101

X Y Z

m5

X +Y + Z

M5

110

X Y Z

m6

X +Y + Z

M6

111

X Y Z

m7

X +Y + Z

M7

(sum) and

(product) notation

Any truth table or a Boolean equation description of unsimplified

logic can be expressed by summing minterms m . Sigma indicates sum
and lower case m indicates minterms.

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12

Example

No.

Inputs

Output

Z = F ( A, B ) = (m0 , m3 )

Z = F ( A, B ) = (0,3)

Z = F ( A, B) = A B + A B . (a)

It is also can express any truth table or a Boolean equation description

of unsimplified logic by multiplying maxterms ( M ). Pi indicates product
and upper case M indicates maxterms. For the same above example, Z
can be expressed by using maxterms.
Z = F ( A, B ) = ( M 1 , M 2 )
Z = F ( A, B) = (1,2)

Z = F ( A, B ) = ( A + B ) ( A + B ) .. (b)

Exercise Show that expressions (a) and (b) in the above example are
equivalents.

Karnaugh map
The Karnaugh map, like Boolean algebra, is a simplification tool
applicable to digital logic. The Karnaugh Map will simplify logic faster and
more easily in most cases. Boolean simplification is actually faster than the
Karnaugh map for a task involving two or fewer Boolean variables. It is still
quite usable at three variables, but a bit slower. At four input variables,
Boolean algebra becomes tedious. Karnaugh maps are both faster and easier.
Karnaugh maps work well for up to six input variables, are usable for up to
eight variables. For more than six to eight variables, simplification should be
by CAD (computer automated design).
The outputs of a truth table correspond on a one-to-one basis to Karnaugh
map (simply k-map) entries.
For two input variables A and B k-map is formed as follow:
Starting at the top of the truth table, the A=0, B=0 inputs produce an
output . Note that this same output is found in the Karnaugh map at the
A=0, B=0 cell address, upper left corner of K-map where the A=0 row and
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13

B=0 column intersect. The other truth table outputs , , from inputs
AB=01, 10, 11 are found at corresponding K-map locations.

Procedure for simplification using k-map

a) Divide input variables into two groups, such that the difference between
the numbers of variables in each group doesnt exceed one.
b) Draw two dimensions grid.
c) Arrange corresponding binary numbers of the input variables
combinations of the first and second groups on the top and left sides of
the grid, respectively, such that the difference between any adjacent
numbers is in only one digit (variable). In other words, corresponding
binary number of input variables must be arranged on the top and left
sides of the grid as gray code.
d) Identify the minterm (product term) term to be mapped.
e) Write the corresponding binary numeric value.
f) Use binary value as an address to place a 1 in the K-map.
g) Repeat steps (d-f) for other minterms.
h) Form largest groups of 1s possible covering all minterms. Groups must
be a power of 2.
i) Write binary numeric value for groups.
j) Convert binary value to a product term.
k) Repeat steps (i-j) for other groups. Each group yields a product term
within a Sum-Of-Products.

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14

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15

Examples
Binary
number

Inputs
ABCD

Output
Z

0000

1111

ABC D
ABC D
A B CD
A B CD
A BC D
A BC D
A BCD
A BCD
AB C D
AB C D
AB CD
AB CD
ABC D
ABC D
ABCD
ABCD

Binary
number

Inputs
ABCD

Output
Z

0000

ABCD
ABC D
A B CD
A B CD
A BC D
A BC D
A BCD
A BCD
AB C D
AB C D
AB CD
AB CD
ABC D
ABC D
ABCD
ABCD

0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110

0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

ByDrOdayAl.ARidha

out = (0,2,8,15)

1
0
0
0
0
0
1
0
0
0
0
0
0
1

out = (0,1,4,5,8,9,12,13,15)

1
0
0
1
1
0
0
1
1
0
0
1
1
0
1

16

Binary
number

Inputs
ABCD

Output
Z

Binary
number

Inputs
ABCD

Output
Z

0000

ABC D
ABC D
A B CD
A B CD
A BC D
A BC D
A BCD
A BCD

1000

1001

AB C D
AB C D
AB CD
AB CD
ABC D
ABC D
ABCD
ABCD

0001
0010
0011
0100
0101
0110
0111

1010
1011
1100
1

1110
1

Binary
number

Inputs
ABCD

Output
Z

0000

ABC D
ABC D
A B CD
A B CD
A BC D
A BC D
A BCD
A BCD
AB C D
AB C D
AB CD
AB CD
ABC D
ABC D
ABCD
ABCD

0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

ByDrOdayAl.ARidha

1101
1111

0
1
0
0
0
1
1

out = (3,7,11,12,13,14,15)

0
0
1
0
0
0
1
0
0
0
1
1
1
1
1

17

Binary
number

Inputs
ABCD

Output
Z

0000

1111

ABCD
ABCD
A B CD
A B CD
A BC D
A BC D
A BCD
A BCD
AB C D
AB C D
AB CD
AB CD
ABC D
ABC D
ABCD
ABCD

Binary
number

Inputs
ABCD

Output
Z

0000

ABCD
ABCD
A B CD
A B CD
A BC D
A BC D
A BCD
A BCD
AB C D
AB C D
AB CD
AB CD
ABC D
ABC D
ABCD
ABCD

0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110

0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

ByDrOdayAl.ARidha

out = ( 0,1,3, 4,5,7 ,12 ,13,15 )

0
1
1
1
0
1
0
0
0
0
1
1
0
1

out = (0,1,2,3,8,9,10,11)

1
1
0
0
0
0
1
1
1
1
0
0
0
0

18

Don't care cells in the Karnaugh map

Up to this point we have considered logic reduction problems where the
input conditions were completely specified. That is, a 3-variable truth table
or Karnaugh map had 2n = 23 or 8-entries, a full table or map. It is not
always necessary to fill in the complete truth table for some real-world
problems. We may have a choice to not fill in the complete table. For
example, when dealing with BCD (Binary Coded Decimal) numbers
encoded as four bits, we may not care about any codes above the BCD range
of (0, 1, 2...9). The 4-bit binary codes for the hexadecimal numbers (Ah, Bh,
Ch, Dh, Eh, Fh) are not valid BCD codes. Thus, we do not have to fill in
those codes at the end of a truth table, or K-map, if we do not care to. We
would not normally care to fill in those codes because those codes (1010,
1011, 1100, 1101, 1110, 1111) will never exist as long as we are dealing
only with BCD encoded numbers. These six invalid codes are don't cares as
far as we are concerned. That is, we do not care what output our logic circuit
produces for these don't cares. Don't cares in a Karnaugh map, or truth table,
may be either 1s or 0s, as long as we don't care what the output is for an
input condition we never expect to see. We plot these cells with an asterisk,
*, among the normal 1s and 0s. When forming groups of cells, treat the don't
care cell as either a 1 or a 0, or ignore the don't cares. This is helpful if it
allows us to form a larger group than would otherwise be possible without
the don't cares. There is no requirement to group all or any of the don't cares.
Only use them in a group if it simplifies the logic.

Example
Design a lamp logic circuits that drives five lamps (L1-L5), as shown
in the figure below. These lights work as follows:
No lamps will light for no motion of the bicycle. As speed increases, the
lower lamp, L1 lights, then L1 and L2, then, L1, L2, and L3, until all lamps
light at the highest speed. Once all the lamps illuminate, no further increase
in speed will have any effect on the display. A small DC generator coupled
to the bicycle tire outputs a voltage proportional to speed. It drives a
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19

tachometer board which limits the voltage at the high end of speed where all
lamps light. No further increase in speed can increase the voltage beyond
this level. This is crucial because the downstream A to D (Analog to Digital)
converter puts out a 3-bit code, ABC, 23 or 8-codes, but we only have five
lamps. A is the most significant bit, C the least significant bit. The lamp
logic needs to respond to the six codes out of the A to D. For ABC=000, no
motion, no lamps light. For the five codes (001 to 101) lamps L1, L1&L2,
L1&L2&L3, up to all lamps will light, as speed, voltage, and the A to D
code (ABC) increases. We do not care about the response to input codes
(110, 111) because these codes will never come out of the A to D due to the
limiting in the tachometer block. We need to design five logic circuits to
drive the five lamps.

Solution

A/D
000
001
010
011
100
101
110
111

ByDrOdayAl.ARidha

Inputs
ABC

ABC
ABC
A BC
A BC
AB C
AB C
ABC
ABC

L1

L2

Output
L3

L4

L5

20

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21

Larger 5 & 6-variable Karnaugh maps

We can arrange variables in 5-variable map in two ways:
1) Using Gray code.
2) Using overlay code.

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22

Examples:

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23

Tabulation method (Quine-McCluskey)

The map method of simplification is convenient as long as the number
of input variables doesnt exceed five or six. As the number of variables
increases, the excessive number of squares prevents a reasonable selection of
adjacent squares. The tabulation method overcomes this difficulty. It is a
specific step-by-step procedure that is guaranteed to produce a simplified
standard-form (sum of products) expression for a function. It can be applied
to problems with many variables and has the advantage of being suitable for
machine computation, but it is tedious for human.
Tabulation method consist from two parts
Part1: find by an exhaustive search all terms that are candidate for
inclusion in the simplified function. These terms are called primeimplicants.
Part2: choose among the prime-implicants those that give an
expression with least number of literals.
Determination of prime-implicants (part 1)
Step 1: group binary number representation of according to number of
1s contained.
Step 2: form second column. Combine any two minterms which differ
from each other by only one variable. Differed variable is replaced by a
dash. Combined minterms are marked. Process of comparison and
combination (if possible) are done between any two members of adjacent
groups.
Step 3: form third column. Again combine any two new minterms in
the second column which differ from each other by only one variable and
dash position are the same. Differed variable is replaced by a new dash.
Combined minterms are marked again.
Process of forming further columns is continued until no new
combination can be done.
Step 4: prime-implicants are these terms that unmarked from the first
to the last column.
Example: simplify the following function:
F ( A, B, C , D) = (1,4,6,7,8,9,10,11,15)

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Step 1
1

3
4

ABCD

No.

Step2

Step3

0001

-001 (1,9)

10- - (8,9,10,11)

0100

01-0 (4,6)

10- - (8,9,10,11)

1000

100- (8,9)

0110

10-0 (8,10)

1001

011- (6,7)

1010

10

10-1 (9,11)

0111

101- (10,11)

1011

11

-111 (7,15)

1111

15

1-11 (11,15)

For the above example prime-implicant are (-001, 01-0, 011-, -111, 1-11,
10--) or ( B C D , A BD , A BC , BCD , ACD , AB ).
F ( A, B, C , D) = B C D + A BD + A BC + BCD + ACD + AB

NOTE: first part of tabulation method not necessary give

minimum expression of a function, therefore we need to
progress to the second part of the method.

Selection of prime-implicants (part 2)

Sum of all prime-implicants obtained in first part of the method. In
some cases these terms can be farther reduced. To get an expression with
least literals, a selection must be done. The selection of prime-implicants
that form the minimized function is made from a prime-implicants table. In
this table, each prime-implicants is represented in a row and each minterm in
a column (Step1), as shown.
Step2: for each prime-implicants row, crosses are placed to indicate
minterms covered by this prime-implicants.
Step 3: inspect complete prime-implicants table for columns containing only
a single cross. In our example there are four minterms whose columns have
single cross: 1, 4, 8, and 10. Prime-implicants that cover minterms with
single cross in their columns are called essential prime-implicants and must
selected. A check mark is placed in the table next to the essential primeimplicants to indicate that they have been selected. Essential primeimplicants must be included in the final simplified expression.
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STEP 1 and 2
Terms

No.

BCD

1,9

A BD

4,6

A BC

6,7

BCD

7,15

ACD

11,15

AB

8,9,10,11

10 11 15

X
X X
X X
X

X
X X
X X X X

STEP 3
Terms

No.

BCD

1,9

A BD

4,6

A BC

6,7

BCD

7,15

ACD

11,15

AB

8,9,10,11

10 11 15

X
X X
X X
X

X
X X
X X X X

Step 4: check each column whose minterms is covered by essential primeimplicants. A check is inserted in the bottom of the columns.
Step 5: uncovered minterms must be included by selecting one or more of
prime-implicants. In our example, we have two minterms (7, 15) uncovered
and three unchecked prime-implicants ( A BC , BCD , ACD ). Selecting BCD
only will lead to covered all minterms; therefore it must be included in the
final simplified expression in addition to essential prime-implicants terms.
F ( A, B, C , D) = B C D + A BD + BCD + AB

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STEP 4
Terms

No.

BCD

1,9

A BD

4,6

A BC

6,7

BCD

7,15

ACD

11,15

AB

8,9,10,11

10 11 15

X
X X
X X
X

X
X X
X X X X

10 11 15

STEP 5
Terms

No.

BCD

1,9

A BD

4,6

A BC

6,7

BCD

7,15

ACD

11,15

AB

8,9,10,11

X
X X
X X
X

X
X X
X X X X

NOTES
1) We can use decimal number instead of binary numbers
2) Tabulation method can be adopted to give a simplified expression in
product of sums. As in the map method, we have to start with the
complement of the function by taking the 0s as the initial list of
minterms. This list contains those minterms not included in the
original function which are numerically equal to the maxterms of the
function. The tabulation process is carried out with 0s of the function
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27

and terminates with a simplified expression in sum of products of the

complement of the function. By taking the complement again, we
obtain the simplified product of sums expression.
3) A function with dont-care conditions can be simplified by the
tabulation method after a slight modification. The dont-care terms
are included in the list of minterms when the prime-implicants are
determined. This allows the derivation of prime-implicants with least
number of literals. The dont-care terms are not included in the list of
minterms when prime-implicants table is set up, because dont-care
terms do not have to be covered by the selected prime-implicants.

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NAND and NOR implementation

Digital circuits are more frequently construct with NAND or NOR
gates than with AND and OR gates. NAND and NOR gates are easier to
fabricate with electronic components and are the basic gates used in all IC
digital logic families.

Not equivalent

OR equivalent

AND equivalent
Example: implement the following logic circuit using NAND gates only

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29

Solution:
Step 1:

Step 2:

Properties of exclusive OR and Equivalence

Exclusive-OR and equivalence, denoted by and , respectively.
The two operations are complements of each other. Each is
commutative and associative.
( A B) C = A ( B C ) = A B C

An n-variable XOR expression is equal to the Boolean function with

n

2 / 2 minterms whose equivalent binary numbers have an odd

numbers of 1s.
n

An n-variable equivalence is equal to the Boolean function with 2 / 2

minterms whose equivalent binary numbers have an even numbers of
0s.
When the number of variables in a function is odd the minterms with
an even number of 0s are the same as the minterms with odd number
DrOdayA.L.ARidha

30

of 1s, therefore an XOR expression is equal to Equivalence

expression when both have the same odd number of variables.
A B C = ABC

When the minterms of a function with an odd number of variables

have an even number of 1s (or equivalently, an odd number of 0s),
the function can be expressed as the complement of either an
exclusive-OR or an equivalence expression.
( A B C ) = A BC = AB C
( ABC ) = AB C = A BC

Complement one of the inputs of XOR or equivalence function is

equal to complement the same function. (Prove that).
Exclusive-OR and Equivalence functions very useful in system
requiring error-detection and error-correction codes. Parity bit is a
scheme for detecting errors during transmission of binary information. A
parity bit is an extra bit included with a binary message to make the
number of 1s either odd or even. The message included the parity bit, is
transmitted and then checked at receiving end for error.

Example: design a 3-bit odd parity generator

3-bit
message
ABC

Parity bit
Generated
P

000
001
010
011
100
101
110
111

1
0
0
1
0
1
1
0

DrOdayA.L.ARidha

BC
A

00 01 11 10
0 1
1
1
1
1

P = ( A B C ) = A B C

31

Example: design an odd parity checker for 4-bit pattern

4-bit message
ABCP

Check
E

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1

AB
CP

00

00

01

01

11
1

11

10

10

1
1

E = ABC P

Parallel adder

A4 B 4
C5

FA
4
S4

A3 B 3
C4

FA
3
S3

A2 B 2
C3

FA
2

A1 B 1
C2

S2

FA
1

C1

S1

4-bit parallel binary adder

DrOdayA.L.ARidha

32

Carry propagation

An
Bn

Cn+1

HA
HA

Cn

FA n

A2
B2

HA

C3
HA

C2

FA 2

A1
B1

HA

Sn

S2

C2
HA

C1

S1

FA 1

Time required to propagate a carry from C1 to Cn+1 in an n-bit parallel

adder is equal to 2n times propagation delay time of one gate.
Look-ahead Carry
The carry propagation time is a limiting factor on the speed with
which two numbers are added in parallel. There are several techniques for
reducing the carry propagation time in a parallel adder. The most widely
used technique employs the principle of look-ahead carry.
Consider the full-adder shown in the figure below. If we define two
new binary variables:

Pi = Ai Bi

Gi = Ai Bi
DrOdayA.L.ARidha

33

The output sum and carry can be expresses as:

Si = Pi Ci
C i +1 = Gi + Pi C i

Now we can write the Boolean function for the carry output of each
stage and substitute for each its value from the previous equations:
C 2 = G1 + P1C1
C3 = G2 + P2C2 = G2 + P2 (G1 + P1C1 ) = G2 + P2G1 + P2 P1C1
C4 = G3 + P3C3 = G3 + P3G2 + P3 P2G1 + P3 P2 P1C1

Since the Boolean function for each output carry is expressed in sum
of products, each function can be implemented with one level of AND gates
follows by an OR gate. Note that Cn does not have to wait for Cn-1, Cn-2, ...,
and C1 to propagate; in fact, Cn is propagated at the same time as C1, and C2.
A4
B4

P4

C5
C4

C5
P4

S4

P3

S3

P2

S2

G4
A3
B3

P3

C3

Lookahead carry
P2 generator C2

G3
A2
B2

G2
A1
B1

P1

P1

S1

G1
C1

C1

BCD adder
Is a circuit that adds two BCD digits with a possible carry from previous
stage, in parallel, and produces a sum digit also in BCD. Since each input
digit doesnt exceed 9, the output sum cannot be greater 19, (9+9+1).
Suppose we apply two BCD digits to a 4-bit binary adder. The adder
will form the sum in binary and produce a result which may range from 0 to
19. These binary numbers are listed in the table below and are labeled by
symbols K, Z8, Z4, Z2, Z1. K is the carry, and subscripts under the letter Z
represent the weights that can be assigned to the four bits in the BCD code.
The first column in the table lists the binary sums as they appear in the
outputs of a 4-bit binary adder. The output sum of two decimal digits must

DrOdayA.L.ARidha

34

be represented in BCD and should appear in the form listed in the second
column of the table.
K
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1

Z8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0

Binary sum
Z4
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

Z2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Z1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

C
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1

S8
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1

BCD sum
S4
S2
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0

S1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

In examination the contents of the table, it is apparent that when the sum is
equal or less than 9, the corresponding BCD number is identical, and
therefore no conversion is needed. When the binary sum is greater than 9,
we obtain a nonvalid BCD representation. The addition of 6 to the binary
sum converts it to the correct BCD representation and also produces an
output carry as required.
The logic circuit that detects the necessary correction can be derived from
the table entries. It obvious that correction is needed when the binary sum
has an output carry K=1. The other six combinations from 1010 to 1111 that
need a correction have a 1 in position Z8. To distinguish them from binary
1000 and 1001 which also have a 1 in position Z8, we specify further that
either Z4 or Z2 must have a 1. The condition for a correction and an output
carry can be expressed by the Boolean function:
C = K + Z8Z 4 + Z8Z 2

When C=1, it is necessary to add 6 to the binary sum and provide an output
carry for next stage.

DrOdayA.L.ARidha

35

Addend

Augend

Carry in

4-bit binary adder

Z8

Z4

Z2

Z1

0
4-bit binary adder

S8

S4

S2

S1

Output Carry

Magnitude Comparator
The comparison of two numbers is an operation that determines if one
number is greater than, less than, or equal to the other number. A magnitude
comparator is a combinational circuit that compares two numbers, A and B,
and determines their relative magnitude. The outcome of the comparison is
specified by three binary variables that indicate whether A>B, A=B, or A<B.
If
A = A3 A2 A1 A0
B = B3 B2 B1 B0

We define
xi = Ai Bi + AiBi

i=0, 1, 2, 3

Then
( A = B) = x3 x 2 x1 x0
( A > B) = A3 B3 + x3 A2 B2 + x3 x 2 A1 B1 + x3 x 2 x1 A0 B0
( A < B) = A3 B3 + x3 A2 B2 + x3 x 2 A1B1 + x3 x 2 x1 A0 B0

Exercise: draw the logic circuit of 3-bit magnitude binary comparator

DrOdayA.L.ARidha

36

Decoders
Discrete quantities of information are represented in digital system with
binary codes. A binary code of n bits is capable of representing up 2n distinct
elements of the coded information. Decoder is a combinational circuit that
converts binary information from n input lines to a maximum of 2n unique
output lines. If n-bit decoded information has unused or dont-care
conditions, the output decoder will have less than 2n output. The name
decoder is also used in conjunction with some code converters such as BCDto-seven-segment decoder.
Inputs

Outputs

XYZ

D0

D1

D2

D3

D4

D5

D6

D7

000
001
010
011
100
101
110
111

1
0
0
0
0
0
0
0

0
1
0
0
0
0
0
0

0
0
1
0
0
0
0
0

0
0
0
1
0
0
0
0

0
0
0
0
1
0
0
0

0
0
0
0
0
1
0
0

0
0
0
0
0
0
1
0

0
0
0
0
0
0
0
1

Truth table of 3-to-8 lined decoder

Observe that the output variables are mutually exclusive because only one
output can be equal to 1 at any time. The output line whose value is equal to
1 represents the minterm equivalent of the binary number presently available
in the input lines.
We can construct a more big line decoder using small decoders
Example: construct a 4-to-8 (416) line decoder using 3-to-8 decoder.

A
B
C

38
Decoder
En

D0
D1
D2
D3
D4
D5
D6
D7

38
Decoder
En

DrOdayA.L.ARidha

D8
D9
D2
D11
D12
D13
D14
D15

37

Exercise1: Design BCD-to-decimal decoder.

Exercise2: Design BCD-to-seven-segment decoder.
Exercise3: Implement a full-adder circuit using 3-to-8 decoder.
Encoders
An Encoder is a digital function that produces a reverse operation from that
of decoder.
Inputs

Outputs

D7

D6

D5

D4

D3

D2

D1

D0

XYZ

0
0
0
0
0
0
0
1

0
0
0
0
0
0
1
0

0
0
0
0
0
1
0
0

0
0
0
0
1
0
0
0

0
0
0
1
0
0
0
0

0
0
1
0
0
0
0
0

0
1
0
0
0
0
0
0

1
0
0
0
0
0
0
0

000
001
010
011
100
101
110
111

Truth table of 8-to-3 encoder

Multiplexers
Multiplexing means transmitting a large number of information units over a
smaller number of channels or lines. A digital multiplexer is a combinational
circuit that selects binary information from one of many input lines and
directs it to single output line. The selection of particular input line is
controlled by a set of selection lines. Normally, there are 2n input lines and n
selection lines whose bit combinations determine which input is selected.
I0
I1
Inputs
I2
I3

0
1
2
3

41
MUX

S0 S1

Output

S1

S0

I0

I1

I2

I3

Select

Boolean function implementation using multiplexers

If we have a Boolean function of n+ 1 variables, we take n of these variables
and connect them to the selection lines of the multiplexer. The remaining
single variable of the function is used for the inputs of the multiplexer. If A
is this single variable, the inputs of the multiplexer are chosen to be either A
or A or 1 or 0. By judicious use of these four values for the inputs and by
connecting the other variables to the selection lines, one can implement any

DrOdayA.L.ARidha

38

Boolean function with a multiplexer. In this way it is possible to generate

any function of n+1 variables with a 2n to-1 multiplexer.
Procedure
1) express the function in its sum of minterms form, Assume that the
ordered sequence of variables chosen for minterms is ABCD, where
A is leftmost variable in the ordered sequence of n and BCD are the
remaining n-1 variables. Connect the n-1 variables to the selection lines
of the multiplexer with B connected to high-order selection line, C to
the next lower selection line and so on down to the last variable.
2) List the inputs of the multiplexer and under them list all the minterms in
two rows. The first row lists all those minterms where A is
complemented, and the second row all the minterms with A
uncomplemented.
3) Circle all the minterms of the function and inspect each column
separately.
a) If the two minterms in a column are not circled, apply 0 to the
corresponding multiplexer input.
b) If the two minterms are circled, apply 1 to the corresponding
multiplexer input.
c) If the bottom minterm is circled and the top is not circled, apply
A to the corresponding multiplexer input.
d) If the top minterm is circled and the bottom is not circled, apply
A to the corresponding multiplexer input.
Example: Implement F ( A, B, C , D) = (0,1,3,4,8,9,15) with a multiplexer
Solution
1
I0

I1

I2

I3

I4

I5

I6

I7

10

11

12

13

14

15

I0
I1
I2
I3
I4
I5
I6
I7

81
MUX

B
C
D

DrOdayA.L.ARidha

39

Demultiplexers
It is a combinational logic circuit that receives information on a single line
and transmits this information on one of 2n possible output lines. The
selection of a specific output line is controlled by the bit values of n
selection lines. A decoder with an enable input can function as a
demultiplexer.

14
Demultiplexer

E
Input

D0
D1
D2
D3

A
B
E
Enable

A
B
Select
A
0
0
1
1

B
0
1
0
1

D0
E
0
0
0

D1
0
E
0
0

D2
0
0
E
0

D0
D1
D2
D3

24
Decoder

E
0
1
1
1
1

D3
0
0
0
E

A
X
0
0
1
1

B
X
0
1
0
1

D0
0
1
0
0
0

D1
0
0
1
0
0

D2
0
0
0
1
0

D3
0
0
0
0
1

Read-only memory (ROM)

We know that a decoder can generate 2n minterms of the n input variables.
By inserting OR gates to sum the minterms of Boolean functions, we were
able to generate any desired combinational circuit. A read-only memory
(ROM) is a device that includes both the decoder and the OR gates within a
single IC package. The connections between the outputs of the decoder and
the inputs of the OR gates can be specified for each particular configuration
by programming the ROM. The ROM is very often used to implement a
complex combinational circuit in one IC package and thus eliminate all
interconnecting wires.

n Inputs
(Address)

2nm
ROM

m Outputs
(Data)

Memory size=2nm

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40

ROM types
1) Mask programming ROM
2) Programmable ROM (PROM)
3) Erasable Programmable ROM (EPROM)
4) Electrically Erasable Programmable ROM (E2PROM)
Example: Design a combinational circuit that accept a 3-bit number and
generates an output binary number equal to the square of the input number.
Use a minimum ROM size.
Solution:
Inputs
XYZ
000
001
010
011
100
101
110
111

Outputs
D5
0
0
0
0
0
0
1
1

DrOdayA.L.ARidha

D4
0
0
0
0
1
1
0
1

D3
0
0
0
1
0
1
0
0

D2
0
0
1
0
0
0
1
0

D1
0
0
0
0
0
0
0
0

D0
0
1
0
1
0
1
0
1

X
Y
Z

D5
D4

2 4
ROM

D3
D2

D1
D0

41

Sequential logic circuit

Introduction
Combinational logic refers to circuits whose output is strictly depended on the present value of the inputs. As
soon as inputs are changed, the information about the previous inputs is lost, that is, combinational logics
circuits have no memory. In many applications, information regarding input values at a certain instant of time
is required at some future time. Although every digital system is likely to have combinational circuits, most
systems encountered in practice also include memory elements, which require that the system be described in
terms of sequential logic. Circuits whose outputs depends not only on the present input value but also the
past input value are known as sequential logic circuits. A general block diagram of a sequential circuit is
shown below.

Block Diagram of Sequential Circuit.

The diagram consists of combinational circuit to which memory elements are connected to form a feedback
path. The memory elements are devices capable of storing binary information within them. The
combinational part of the circuit receives two sets of input signals: one is primary (coming from the circuit
environment) and secondary (coming from memory elements). The particular combination of secondary
input variables at a given time is called the present state of the circuit. The secondary input variables are
also know as the state variables.
The block diagram shows that the external outputs in a sequential circuit are a function not only of external
inputs but also of the present state of the memory elements. The next state of the memory elements is also a
function of external inputs and the present state. Thus a sequential circuit is specified by a time sequence of
inputs, outputs, and internal states.

DrOdayA.LARidha

42

Synchronous and Asynchronous Operation

Sequential circuits are divided into two main types: synchronous and asynchronous. Their classification
depends on the timing of their signals.
Synchronous sequential circuits change their states and output values at discrete instants of time, which are
specified by the rising and falling edge of a free-running clock signal. The clock signal is generally some
form of square wave as shown below.

Clock Signal
From the diagram you can see that the clock period is the time between successive transitions in the same
direction, that is, between two rising or two falling edges. State transitions in synchronous sequential circuits
are made to take place at times when the clock is making a transition from 0 to 1 (rising edge) or from 1 to 0
(falling edge). Between successive clock pulses there is no change in the information stored in memory.
The reciprocal of the clock period is referred to as the clock frequency. The clock width is defined as the
time during which the value of the clock signal is equal to 1. The ratio of the clock width and clock period is
referred to as the duty cycle. A clock signal is said to be active high if the state changes occur at the clock's
rising edge or during the clock width. Otherwise, the clock is said to be active low. Synchronous sequential
circuits are also known as clocked sequential circuits.
The memory elements used in synchronous sequential circuits are usually flip-flops. These circuits are binary
cells capable of storing one bit of information. A flip-flop circuit has two outputs, one for the normal value
and one for the complement value of the bit stored in it. Binary information can enter a flip-flop in a variety
of ways, a fact which give rise to the different types of flip-flops.
In asynchronous sequential circuits, the transition from one state to another is initiated by the change in the
primary inputs; there is no external synchronization. The memory commonly used in asynchronous
sequential circuits are time-delayed devices, usually implemented by feedback among logic gates. Thus,
asynchronous sequential circuits may be regarded as combinational circuits with feedback. Because of the
feedback among logic gates, asynchronous sequential circuits may, at times, become unstable due to transient
conditions. The instability problem imposes many difficulties on the designer. Hence, they are not as
commonly used as synchronous systems.

DrOdayA.LARidha

43

Flip-flops types
1) RS Flip-Flop
Basic flip-flop circuit with NOR gates
S

1
0
0
0
1

0
0
1
0
1

1
1
0
0
0

0
0
1
1
0

after SR=10
after SR=01

Truth table
Basic flip-flop circuit with NAND gates
S

1
1
0
1
0

0
1
1
1
0

0
0
1
1
1

1
1
0
0
1

after SR=10
after SR=01

Truth table

2) Clocked RS Flip-Flop
Qi S

Qi+1

indeterminate

indeterminate

Characteristic table

DrOdayA.LARidha

44

3) D-type Flip-Flop
Qi

Qi+1

0
0
1
1

0
1
0
1

0
1
0
1

Characteristic table

4) JK Flip-Flop
Qi J

Qi+1

Characteristic table

5) T Flip-Flop

Qi

Qi+1

0
0
1
1

0
1
0
1

0
1
1
0

Characteristic table

DrOdayA.LARidha

45

6) Master-slave Flip-Flop

CLK

Master

Slave

Y
Q

CLK

Timing relationships in a master-slave flip-flop

The master-slave combination can be constructed for any type of flip-flop by adding a clock RS flip-flop with
an inverted clock to form the slave

7) Edge-triggered Flip-Flop

tS tH
CLK

D
Q

Valid
Valid

tS Setup time
tH Hold time
Setup time is a definite time in which D input must be maintained at a constant value prior to the application
of the clock pulse.

Hold time is a definite time that D input must be not change after application of positive going transition of
the clock pulse.

DrOdayA.LARidha

46

Summary of the Types of Flip-flop Behavior

Since memory elements in sequential circuits are usually flip-flops, it is worth summarizing the behavior of
various flip-flop types before proceeding further.
All flip-flops can be divided into four basic types: SR, JK, D and T. They differ in the number of inputs and
in the response invoked by different value of input signals. The four types of flip-flops are defined in Table
below.
FLIPFLOP
NAME

SR

JK

FLIP-FLOP
SYMBOL

CHARACTERISTIC
TABLE

Q(next)

CHARACTERISTIC
EQUATION

Q(next) = S + R'Q
SR = 0 (condition)

EXCITATION TABLE

Q Q(next) S

Q Q(next) J

Q(next)

Q'

Q(next)

Q(next)

Q(next)

Q(next)

Q'

Q(next) = JQ' + K'Q

Q(next) = D

Q(next) = TQ' + T'Q

Each of these flip-flops can be uniquely described by its graphical symbol, its characteristic table, its
characteristic equation or excitation table. All flip-flops have output signals Q and Q'.

DrOdayA.LARidha

47

The characteristic table in the third column of the table defines the state of each flip-flop as a function of its
inputs and previous state. Q refers to the present state and Q(next) refers to the next state after the
occurrence of the clock pulse. The characteristic table for the RS flip-flop shows that the next state is equal to
the present state when both inputs S and R are equal to 0. When R=1, the next clock pulse clears the flip-flop.
When S=1, the flip-flop output Q is set to 1. The equation mark (?) for the next state when S and R are both
equal to 1 designates an indeterminate next state.
The characteristic table for the JK flip-flop is the same as that of the RS when J and K are replaced by S and
R respectively, except for the indeterminate case. When both J and K are equal to 1, the next state is equal to
the complement of the present state, that is, Q(next) = Q'.
The next state of the D flip-flop is completely dependent on the input D and independent of the present state.
The next state for the T flip-flop is the same as the present state Q if T=0 and complemented if T=1.
The characteristic table is useful during the analysis of sequential circuits when the value of flip-flop inputs
are known and we want to find the value of the flip-flop output Q after the rising edge of the clock signal. As
with any other truth table, we can use the map method to derive the characteristic equation for each flip-flop,
which are shown in the third column of the table.
During the design process we usually know the transition from present state to the next state and wish to find
the flip-flop input conditions that will cause the required transition. For this reason we will need a table that
lists the required inputs for a given change of state. Such a list is called the excitation table, which is shown
in the fourth column of the table. There are four possible transitions from present state to the next state. The
required input conditions are derived from the information available in the characteristic table. The symbol X
in the table represents a "don't care" condition, that is, it does not matter whether the input is 1 or 0.

DrOdayA.LARidha

48

Analysis of Sequential Circuits

The behavior of a sequential circuit is determined from the inputs, the outputs and the states of its flip-flops.
Both the output and the next state are a function of the inputs and the present state. The suggested analysis
procedure of a sequential circuit is set out in the Figure below.

Analysis procedure of sequential circuits

DrOdayA.LARidha

49

We start with the logic schematic from which we can derive excitation equations for each flip-flop input.
Then, to obtain next-state equations, we insert the excitation equations into the characteristic equations. The
output equations can be derived from the schematic, and once we have our output and next-state equations,
we can generate the next-state and output tables as well as state diagrams. When we reach this stage, we use
either the table or the state diagram to develop a timing diagram which can be verified through simulation.
Now let's look at some examples, using these procedures to analyze a sequential circuit.
This example is taken from D. D. Gajski, Principles of Digital Design, Prentice Hall, 1997, p.230.

Example Modulo-4 counter

Derive the state table and state diagram for the sequential circuit shown in the Figure below.

Logic schematic of a sequential circuit

SOLUTION:
STEP 1: First we derive the Boolean expressions for the inputs of each flip-flops in the schematic, in
terms of external input Cnt and the flip-flop outputs Q1 and Q0. Since there are two D flip-flops in this
example, we derive two expressions for D1 and D0:

D0 = Cnt Q0 = Cnt'.Q0 + Cnt.Q0'

D1 = Cnt'.Q1
Cnt.Q1'.Q0
Cnt.Q1.Q0'
These Boolean expressions are called excitation equations since they represent the inputs to the flip-flops of
the sequential circuit in the next clock cycle.
STEP 2:
Derive the next-state equations by converting these excitation equations into flip-flop
characteristic equations. In the case of D flip-flops, Q(next) = D. Therefore the next state equal the excitation
equations.

Q0(next) = D0 = Cnt'.Q0 + Cnt.Q0'

Q1(next) = D1 = Cnt'.Q1
Cnt.Q1'.Q0

DrOdayA.LARidha

Cnt.Q1.Q0'
50

STEP 3:

Now convert these next-state equations into tabular form called the next-state table.
Present State
Q1Q0
00
01
10
11

Next State
Cnt = 0
Cnt = 1
00
01
10
11

01
10
11
00

Each row is corresponding to a state of the sequential circuit and each column represents one set of input
values. Since we have two flip-flops, the number of possible states is four - that is, Q1Q0 can be equal to 00,
01, 10, or 11. These are present states as shown in the table.
For the next state part of the table, each entry defines the value of the sequential circuit in the next clock
cycle after the rising edge of the CLK. Since this value depends on the present state and the value of the
input signals, the next state table will contain one column for each assignment of binary values to the input
signals. In this example, since there is only one input signal, Cnt, the next-state table shown has only two
columns, corresponding to Cnt = 0 and Cnt = 1.
Note that each entry in the next-state table indicates the values of the flip-flops in the next state if their value
in the present state is in the row header and the input values in the column header.
Each of these next-state values has been computed from the next-state equations in STEP 2.
STEP 4:

The state diagram is generated directly from the next-state table, shown in the Figure below.

State diagram
Each arc is labeled with the values of the input signals that cause the transition from the present state (the
source of the arc) to the next state (the destination of the arc).

DrOdayA.LARidha

51

In general, the number of states in a next-state table or a state diagram will equal 2m , where m is the number
of flip-flops. Similarly, the number of arcs will equal 2m x 2k, where k is the number of binary input signals.
Therefore, in the state diagram, there must be four states and eight transitions. Following these transition
arcs, we can see that as long as Cnt = 1, the sequential circuit goes through the states in the following
sequence: 0, 1, 2, 3, 0, 1, 2,.... On the other hand, when Cnt = 0, the circuit stays in its present state until Cnt
changes to 1, at which the counting continues.
Since this sequence is characteristic of modulo-4 counting, we can conclude that the given sequential circuit
is a modulo-4 counter with one control signal, Cnt, which enables counting when Cnt = 1 and disables it
when Cnt = 0.
Below, we show a timing diagram, representing four clock cycles, which enables us to observe the behavior
of the counter in greater detail.

Timing Diagram
In this timing diagram we have assumed that Cnt is asserted in clock cycle 0 at t0 and is disserted in clock
cycle 3 at time t4. We have also assumed that the counter is in state Q1Q0 = 00 in the clock cycle 0. Note that
on the clock's rising edge, at t1, the counter will go to state Q1Q0 = 01 with a slight propagation delay; in
cycle 2, after t2, to Q1Q0 = 10; and in cycle 3, after t3 to Q1Q0 = 11. Since Cnt becomes 0 at t4, we know that
the counter will stay in state Q1Q0 = 11 in the next clock cycle.
In the previous Example, we demonstrated the analysis of a sequential circuit that has no outputs by
developing a next-state table and state diagram which describes only the states and the transitions from one
state to the next. In the next example we complicate our analysis by adding output signals, which means that
we have to upgrade the next-state table and the state diagram to identify the value of output signals in each
state.
This example is taken from D. D. Gajski, Principles of Digital Design, Prentice Hall, 1997, p.234.
Example Derive the next state, the output table and the state diagram for the sequential circuit shown in the
Figure below.

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52

Logic schematic of a sequential circuit.

SOLUTION:
The input combinational logic in the above Figure is the same as in the previous example, so the excitation
and the next-state equations will be the same.
Excitation equations:

D0 = Cnt
Q0 = Cnt'.Q0 + Cnt.Q0'
D1 = Cnt'.Q1
Cnt.Q1'.Q0
Cnt.Q1.Q0'
Next-state equations:

Q0(next) = D0 = Cnt'.Q0 + Cnt.Q0'

Q1(next) = D1 = Cnt'.Q1 Cnt.Q1'*Q0

Cnt.Q1.Q0'

In addition, however, we have computed the output equation.

Y = Q1Q0

Output equation:

As this equation shows, the output Y will equal to 1 when the counter is in state Q1Q0 = 11, and it will stay 1
as long as the counter stays in that state.
Next-state and output table:
Present State
Q1 Q0
00
01
10
11

DrOdayA.LARidha

Next State
Cnt=0
Cnt=1
00
01
10
11

01
10
11
00

Output
Y
0
0
0
1

53

State diagram:

State diagram of the sequential circuit

Timing diagram of the sequential circuit

Note that the counter will reach the state Q1Q0 = 11 only in the third clock cycle, so the output Y will equal
1 after Q0 changes to 1. Since counting is disabled in the third clock cycle, the counter will stay in the state
Q1Q0 = 11 and Y will stay asserted in all succeeding clock cycles until counting is enabled again.

Design of Sequential Circuits

The design of a synchronous sequential circuit starts from a set of specifications and culminates in a logic
diagram or a list of Boolean functions from which a logic diagram can be obtained. In contrast to a
combinational logic, which is fully specified by a truth table, a sequential circuit requires a state table for its

DrOdayA.LARidha

54

specification. The first step in the design of sequential circuits is to obtain a state table or an equivalence
representation, such as a state diagram.
A synchronous sequential circuit is made up of flip-flops and combinational gates. The design of the circuit
consists of choosing the flip-flops and then finding the combinational structure which, together with the flipflops, produces a circuit that fulfils the required specifications. The number of flip-flops is determined from
the number of states needed in the circuit.
The recommended steps for the design of sequential circuits are set out below.

Sequential circuit design steps

DrOdayA.LARidha

55

STEP 2

State Diagram
STEP 3
Present State
Q0 Q1

Next State
x=0
x=1

00
01
10
11
STEP 4

00
10
10
11

01
01
11
00

State Reduction

Any design process must consider the problem of minimizing the cost of the final circuit. The two most
obvious cost reductions are reductions in the number of flip-flops and the number of gates.
The number of states in a sequential circuit is closely related to the complexity of the resulting circuit. It is
therefore desirable to know when two or more states are equivalent in all aspects. The process of eliminating
the equivalent or redundant states from a state table/diagram is known as state reduction. Two states are
said to be equivalent if, for each member of the set of inputs, they give exactly the same output and send
the circuit either to the same state or to an equivalent state. When two states are equivalent, one of them
can be removed without altering the input-output relationships.
Example: Let us consider the state table of a sequential circuit shown below.
Present State
A
B
C
D
E
F

DrOdayA.LARidha

Next State
x=0
x=1
B
F
D
F
A
B

C
D
E
E
D
C

Output
x=0 x=1
1
0
1
0
0
1

0
0
1
1
0
0

56

It can be seen from the table that the present state A and F both have the same next states, B (when x=0) and
C (when x=1). They also produce the same output 1 (when x=0) and 0 (when x=1). Therefore states A and F
are equivalent. Thus one of the states, A or F can be removed from the state table. For example, if we remove
row F from the table and replace all F's by A's in the columns, the state table is modified as shown in the
table below.
Present State
A
B
C
D
E

Next State
x=0
x=1
B
A
D
A
A

C
D
E
E
D

Output
x=0 x=1
1
0
1
0
0

0
0
1
1
0

State F removed
It is apparent that states B and E are equivalent. Removing E and replacing E's by B's results in the reduce
table below..
Present State
A
B
C
D

Next State
x=0
x=1
B
A
D
A

C
D
B
B

Output
x=0 x=1
1
0
1
0

0
0
1
1

Reduced state table

The removal of equivalent states has reduced the number of states in the circuit from six to four. Two states
are considered to be equivalent if and only if for every input sequence the circuit produces the same output
sequence irrespective of which one of the two states is the starting state.
Note: A circuit with m flip-flops would have 2m states. There are occasions when a sequential circuit may use
less than this maximum number of states. States that are not used in specifying the sequential circuit are not
listed in state table. When simplifying the input functions to flip-flops, the unused states can be treated as
dont conditions.

Design of Sequential Circuits Examples

This example is taken from M. M. Mano, Digital Design, Prentice Hall, 1984, p.235.

Example 1 We wish to design a synchronous sequential circuit whose state diagram is shown below. The
type of flip-flop to be use is J-K.

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57

State diagram
From the state diagram, we can generate the state table shown in Table 9. Note that there is no output section
for this circuit. Two flip-flops are needed to represent the four states and are designated Q0Q1. The input
variable is labeled x.
Present State
Q0 Q1

Next State
x=0
x=1

00
01
10
11

00
10
10
11

01
01
11
00

State table.
We shall now derive the excitation table and the combinational structure. The table is now arranged in a
different form shown in the table below, where the present state and input variables are arranged in the form
of a truth table. Remember, the excitable for the JK flip-flop was derive in the table.
Excitation table for JK flip-flop
Output Transitions
Q Q(next)
0
0
1
1

DrOdayA.LARidha

0
1
0
1

Flip-flop inputs
JK
0 X
1 X
X 1
X 0

58

Excitation table of the circuit

Present State
Q0 Q1

Next State
Q0 Q1

Input
x

00
00
01
01
10
10
11
11

00
01
10
01
10
11
11
00

0
1
0
1
0
1
0
1

Flip-flop Inputs
J0K0
J1K1
0X
0X
1X
0X
X0
X0
X0
X1

0X
1X
X1
X0
0X
1X
X0
X1

In the first row of the above table, we have a transition for flip-flop Q0 from 0 in the present state to 0 in the
next state. In the table we find that a transition of states from 0 to 0 requires that input J = 0 and input K = X.
So 0 and X are copied in the first row under J0 and K0 respectively. Since the first row also shows a
transition for the flip-flop Q1 from 0 in the present state to 0 in the next state, 0 and X are copied in the first
row under J1 and K1. This process is continued for each row of the table and for each flip-flop, with the input
conditions as specified in the table.
The simplified Boolean functions for the combinational circuit can now be derived. The input variables are
Q0, Q1, and x; the outputs are the variables J0, K0, J1 and K1. The information from the truth table is plotted
on the Karnaugh maps shown in the figure below.

Karnaugh Maps
The flip-flop input functions are derived:

J0 = Q1.x'
J1 = x

DrOdayA.LARidha

K0 = Q1.x
K1 = Q0'.x' + Q0.x = Q0

59

The logic diagram is drawn in the figure below.

Logic diagram of
the sequential
circuit.

Example 2

Design a sequential circuit whose state tables are specified in the table below, using D flip-

flops.
This example is taken from P. K. Lala, Practical Digital Logic Design and Testing, Prentice Hall, 1996,
p.176.

State table of a sequential circuit.

Present State
Q0 Q1

Next State
x=0
x=1

00
01
10
11

00
00
11
00

Output
x=0 x=1

01
10
10
01

0
0
0
0

0
0
0
1

Excitation table for a D flip-flop.

Output Transitions
Q
Q(next)

DrOdayA.LARidha

Flip-flop inputs
D

60

Next step is to derive the excitation table for the design circuit, which is shown in the table below. The output
of the circuit is labeled Z.
Present State
Q0 Q1

Next State
Q0 Q1

Input
x

00
00
01
01
10
10
11
11

00
01
00
10
11
10
00
01

0
1
0
1
0
1
0
1

Flip-flop
Inputs
D0
D1
0
0
0
1
1
1
0
0

0
1
0
0
1
0
0
1

Output
Z
0
0
0
0
0
0
0
1

Excitation table
Now plot the flip-flop inputs and output functions on the Karnaugh map to derive the Boolean expressions,
which is shown in Figure below.

Karnaugh maps
The simplified Boolean expressions are:

D0 = Q0.Q1' + Q0'.Q1.x
D1 = Q0'.Q1'.x + Q0.Q1.x + Q0.Q1'.x'
Z = Q0.Q1.x
Finally, draw the logic diagram.

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61

Logic diagram of the sequential circuit.

Example 3 A counter is first described by a state diagram, which is shows the sequence of states through
which the counter advances when it is clocked. Figure below shows a state diagram of a 3-bit binary counter.
This example is taken from T. L. Floyd, Digital Fundamentals, Fourth Edition, Macmillan Publishing, 1990,
p.395.

State diagram of a 3-bit binary counter

The circuit has no inputs other than the clock pulse and no outputs other than its internal state (outputs are
taken off each flip-flop in the counter). The next state of the counter depends entirely on its present state, and
the state transition occurs every time the clock pulse occurs. Figure below shows the sequences of count after
each clock pulse.

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62

State diagram of a 3-bit binary counter

Once the sequential circuit is defined by the state diagram, the next step is to obtain the next-state table,
which is derived from the state diagram in the above Figure and is shown in the Table below.

State table
Present State
Q2 Q1 Q0
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Next State
Q2 Q1 Q0
0
0
0
1
1
1
1
0

0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0

Since there are eight states, the number of flip-flops required would be three. Now we want to implement the
counter design using JK flip-flops.
Next step is to develop an excitation table from the state table, which is shown in the table below

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63

Excitation table
Output State Transitions
Present State
Q2 Q1 Q0
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Flip-flop inputs

Next State
Q2 Q1 Q0
0
0
0
1
1
1
1
0

0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0

J2 K2

J1 K1

J0 K0

0X
0X
0X
1X
X0
X0
X0
X1

0X
1X
X0
X1
0X
1X
X0
X1

1X
X1
1X
X1
1X
X1
1X
X1

Now transfer the JK states of the flip-flop inputs from the excitation table to Karnaugh maps to derive a
simplified Boolean expression for each flip-flop input. This is shown in the Figure below.

The 1s in the Karnaugh maps of the above Figure are grouped with "don't cares" and the following
expressions for the J and K inputs of each flip-flop are obtained:

J0 = K0 = 1
J1 = K1 = Q0

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64

J2 = K2 = Q1.Q0
The final step is to implement the combinational logic from the equations and connect the flip-flops to form
the sequential circuit. The complete logic of a 3-bit binary counter is shown in the Figure below.

Logic diagram of a
3-bit binary counter.

Example 4

Design a counter specified by the state diagram in Example 3 using T flip-flops. The state
diagram is shown here again in the Figure below.
This example is taken from M. M. Mano, Digital Design, Prentice Hall, 1984, p.243.

State diagram of a 3-bit binary counter

The state table will be the same as in Example 3.
Now derive the excitation table from the state table, which is shown in the Table below.

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65

Excitation table.
Output State Transitions
Present State
Q2 Q1 Q0
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Flip-flop inputs

Next State
Q2 Q1 Q0
0
0
0
1
1
1
1
0

0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0

T2 T1 T0
0
0
0
1
0
0
0
1

0
1
0
1
0
1
0
1

1
1
1
1
1
1
1
1

Next step is to transfer the flip-flop input functions to Karnaugh maps to derive a simplified Boolean
expressions, which is shown in the Figure below.

The following expressions are obtained:

T0 = 1;

T1 = Q0;

T2 = Q1.Q0

Finally, draw the logic diagram of the circuit from the expressions obtained. The complete logic diagram of
the counter is shown in the Figure below.

Logic diagram of 3-bit binary counter.

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66

Registers
Registers: is a group of binary storage cells suitable for holding binary information.
O4

O3

O2

O1

I3
I2
Simple register

I1

Load

I4

Shift Registers: it is a register that capable of shifting its binary contents either to the left or
right.
O4
Serial in

O3
Q

O2
Q

O1
D

Serial Out

Shift right

Shift-right register
O4

O3

O2

Q
D

O1

CLK
Clear
S1
S0

41

41

41

41

3 2 1 0

3 2 1 0

3 2 1 0

3 2 1 0

SI
for shift right

I4

I3

I2

I1

SI
for shift left

S1S0=00 no change, S1S0=01 Shift right

S1S0=10 Shift left, S1S0=11 parallel load

Bidirectional shift register with parallel load

DrOdayA.L.ARidha

67

Serial addition
Two binary numbers must be first loaded to the shift registers. Shift right signal must
be asserted for one word time. Otherwise incorrect results obtained.

CLK
Shift right
Load

Shift register A

Y
Z

Shift register B

F.A
C
Q

Clear

Exercises
1) Design a sequential circuit whose state table is shown below. Use JK flip-flops for the
design.
Present State
Q1 Q0

Next State
x=0
x=1

00
01
10
11

00
01
10
11

01
00
01
00

Output
x=0
x=1
0
0
0
0

0
1
0
1

2) Using sequential circuit design procedure design k-bit serial adder

Shift register A

a
Serial adder

Shift register B

Shift register C

3) Design a logic circuit that count the number of occurs of the sequence 00 11 10 01 11

DrOdayA.L.ARidha

68

Counters
Counters come in two categories: ripples counters and synchronous counters.
1) Ripple Counters
a) Binary ripple counter
A4
To next
Stage

A3
Q

A1

A2
Q

CLK

CLK

CLK

CLK

Count
Pulses

b) BCD ripple counter

Q4

Q8
Q

J
CLK

Q1

Q2
J

CLK

J
CLK

CLK

Count
Pulses

The following are the conditions for each F.F transition:

Q1 is complemented on the negative edge of every count pulse;
Q2 is complemented if Q8=0 and Q1 goes from 1 to 0, Q2 is cleared if Q8=1 and Q2 is
cleared if Q8=1 and Q1 goes from 1 to 0;
Q4 is complemented when Q2 goes from 1 to 0;
Q8 is complemented when Q4Q2=11 and Q1 goes from 1 to 0. Q8 is cleared if either
Q4 or Q2 is 0 and Q1 goes from 1 to 0.
Three Digits BCD ripple counter

DrOdayA.L.ARidha

Q8 Q4 Q2 Q1

Q8 Q4 Q2 Q1

Q8 Q4 Q2 Q1

BCD Counter

BCD Counter

BCD Counter

102Digit

101 Digit

100 Digit

Count
Pulses

69

2) Synchronous Counters
Synchronous counters are distinguished from ripple counters in that clock pulses are
applied to the CLK inputs of all flip-flops. The common pulse triggers all flip-flops
simultaneously, rather than one at a time in succession as in ripple counters.
a) Synchronous binary counter
A4

A3

A1

A2

CLK
Q

J
CLK

J
CLK

J
CLK

J
CLK

To next
stage

Count
enable

b) Universal binary up/down counters with a parallel load (see Morris Mano p.282)
A4

A3

A2

A1

Load
Clear

4-bit counter

Up/Down

Carry

Enable
CLK

I4

I3

I2

I1

Signal name

Function description

Load
Clear
Up/Down
Enable
Carry

Load counter with I4I3I2I1

1 Clear the content of counter
1 makes counter count up, 0 makes counter count down
1 make counter count, 0 stop counting
1 Generated when the counter reaches the maximum count

DrOdayA.L.ARidha

70

Exercise: Construct a mod-6 counter using universal counter

a) count sequence 0,1,2,3,4,5
b) 10,11,12,13,14,15
c) 3,4,5,6,7,8
A4

A3

A2

A1

Load=0
Clear

4-bit counter

Up/Down=1

Max/Min

Enable=1
CLK

I4

I3

I2

I1

(a)

Johnson Counter

CLK

Content

0
1
2
3
4

0000
1000
1100
1110
1111
0111
0011
0001
0000

5
6
7
8

Ring Counter

O4
D

O3
D

O2
D

O1
D

Q
Q

CLK

CLK
Shift Right
Load

Shift Register with parallel load

Load counter with an initial value=1000

Counting sequence is 1000, 0100,0010,0001,1000, and so on

DrOdayA.L.ARidha

71

Sequential circuit implementation

1) Sequential logic circuit can be implemented using a register and a combinational
circuit as shown below:

Register
CLK
Inputs

Combinational
circuit

Outputs

Register and combinational parts is constructed from discrete components.

2) Sequential logic circuit can be implemented using a register and a ROM as shown
below:

Register

ROM

CLK
Inputs

Outputs

3) Sequential logic circuit can be implemented using Programmable logic devices (PLD)
One of the most popular PLD in our university is generic array logic (GAL). This type
of PLD can be used to implement either combinational or sequential logic circuits. There are
number of GAL ICs, like PALCE20V8 and PALCE16V8, which can be erased and
reprogrammed electrically. The general structure of PALCE20V8 is shown in the figure
below:

DrOdayA.L.ARidha

72

GAL consists of micro cells (MC0-MC7). Each micro cell has a general structure is shown
below:

Moreover, Micro cells can be configured to work in one of the

ninth modes. Cells configuration is done through setting control
bits (SG1, SG0, SL1x, and SL0x). The table below shows the
different configurations. SL1x control bit, where x represents
micro cell number, is used to program the output polarity of cell,
i.e., output is active low or active high.

Figures below represent the different possible configurations of micro cells

DrOdayA.L.ARidha

73

Overall block diagram of PALCE20V8

DrOdayA.L.ARidha

74

DrOdayA.L.ARidha

75

ALGORITHMIC STATE MACHINE (ASM)

The binary information stored in a digital system can be classified as either data or
control information. Data are discrete elements of information that are manipulated to
perform arithmetic, logic, shift, and other similar data processing tasks. These operations are
implemented with digital components such as adders, decoders, multiplexers, counter, and
shift registers. Control information provides command signals that supervise the various
operations in the data section in order to accomplish the desired data-processing tasks. The
logic design of a digital system can be divided into two distinct parts. One part is concerned
with the design of the digital circuits that perform the data-processing operations. The other
part is concerned with the design of the control circuit that supervises the operations and their
sequence.
The relationship between the control logic and the data processor in a digital system is
shown in the figure below.
Status conditions
Commands
External
Inputs

Control Logic

Input
Data

Data processor

Output
Data

The control sequence and data-processing tasks of a digital system are specified by a
mean of a hardware algorithm, a finite number of procedural steps that specify how to obtain
a solution to a problem. The most challenging and creative part of a digital design is the
formulation of hardware algorithms for achieving required objectives.
A flowchart is a convenient way to specify the sequence of procedural steps and
decision paths for an algorithm. A special flowchart that has been developed specially to
define digital hardware algorithms is called Algorithmic state machine (ASM) chart.
The chart is composed of three basic elements: the state box, the decision box, and the
conditional box. A state in the control sequence is indicated by state box. The shape of the
state box is rectangle within which are written register operations or output signal names that
the control generates while being in this state. The state is given a symbolic name, which
placed at the upper left corner of the box. The binary code assigned to the state is placed at
the upper right corner. Inside box is written register operations or output signals.
Binary code
Name
Register operations or
output signals

General description
Dr Oday A.L.A Ridha

001

T1

START

Example
76

The decision box describes the effect of an input on the control subsystem. It has a
diamond-shape box with two or more exit paths, as shown below.

Condition

Exit path

Exit path

The input condition to be tested is written inside the box. One exit path is taken if the
condition is true and another when the condition is false.
The third element of ASM chart is the conditional box. It has an oval shape. The
rounded corner is to differentiate it from state box. The input path of conditional box must
come from one of the exit paths of the decision box. The register operations or outputs listed
inside the conditional box are generated during a given state provided that the input condition
is satisfied.

Register operations or
output signals

ASM block is a structure consisting of one state box and all the decision and
conditional boxes connecting to its exit path. An ASM block has one entrance and any
number of exit paths represented by the structure of the decision boxes. An ASM chart
consists of one or more of interconnected blocks. Each ASM block describes the state of
logic circuit during one clock pulse interval.
ASM block
T1

001
A A+1

0
0

T2

Dr Oday A.L.A Ridha

010

T3

One clock
cycle

R 1

011

T4

Present state Next state

T2, T3, or
T1
T4

100

77

Some ASM figures

T1

001
A A+1
1

E
0

T2

T1

001
A A+1
1

010

T2

Invalid feedback

010

Valid feedback

T1
T1

001
A A+1

001
A A+1

1
0

I1

I2

R 1

I2

K 1

K 1
0
Parallel interconnection

I1

R 1

Serial interconnection

Some of register operations

Symbolic notation

Dr Oday A.L.A Ridha

Description

AB

Transfer the content of reg. B to A

R0

Clear reg. R

AA+1

Increment the content of reg. A by one

AA-1

Decrement the content of reg. A by one

AA+B

Add reg. A and B then store the result in A

78

 The ASM chart is very similar to a state diagram. Each state block is equivalent to a
state in sequential circuit. The decision box is equivalent to the binary information
written along the directed lines that connect two states in a state diagram. As
consequence, it is sometimes convenient to convert the chart to a state diagram and
then use sequential circuit procedures to design the control logic.

T1

001
A A+1
001

0
0

EF=00

R 1

E=1
EF=01

010

T2

010

T3

011

T4

100

100
011

The ASM chart gives all the information necessary to design digital system. The
requirements for the design of data-processor subsystem are specified inside the state
and conditional boxes. The control logic (circuit) is determined from decision boxes
and required state transitions.
The control section of a digital system is essentially a sequential circuit that can be
designed by the procedure used for previous lectures. However, in most cases this
method is impractical because of the large number of state and inputs that a typical
control circuit may have, except for small controllers. There are special methods for
control logic design. These methods may be considered as an extension of the
sequential method. One of these methods is design with multiplexers.

Dr Oday A.L.A Ridha

79

Example: design a digital system with two flip-flops (E and F) and one 4-bit binary counter
(A). A start signal (S) initiates the system by clearing the counter (A) and the flip-flop (F).
The counter is then incremented by one starting from the next clock pulse, and continues
counting until the operations stop.

Counter bits A3 and A4 determine the sequence of

operations as follows:
If A3=0, E is cleared to 0 and the counting continues.
If A3=1, E is set to 1; then if A4=0, the counting continues. But if A4=1, F is set to 1 on
the next clock pulse and the system stops counting.

Control
Circuit

T0
T1
Tn
Q

E
K

Combinational
circuit

F
A4 A3
CLK

Dr Oday A.L.A Ridha

A2

4-bit
Counter

A1

Clear
Count

80

Solution:
P.S
symbol
T0
T0
T1
T1
T1
T2

P.S.
Code
G 1G 2
00
00
01
01
01
11

I/Ps
S
0
1
X
X
X
X

A3
X
X
0
1
1
X

A4
X
X
X
0
1
X

N.S.
Code
G1G2
00
01
01
01
11
00

O/Ps
T0
1
1
0
0
0
0

T1
0
0
1
1
1
0

T2
0
0
0
0
0
1

T0

00

S
1
A0, F0

State table for control

01

T1

AA+1

By using G1 & G2 (JK-type F.F) for representing

states and using k-map for simplification, we
obtain the following logic equations for the control
circuit:

A3

1
E1

E0

J1=QG2A3A4 , K1=1,
J2=S, K2=QG1,
T0=QG2, T1=QG1.QG2, T2=QG1.

1 A
4
11

T2

F1

Combinational circuit equations

Control circuit

Clear=S.T0, Count=T1,
JE=T1.A3, KE=T1.A3,
JF=T2, KF=S.T0.

G2
Q

T0
T1

A4
A3

T2

G1

CLK

For more examples see Morris Mano page 305.

Dr Oday A.L.A Ridha

81

Design with multiplexers

One major goal of control-logic design is the development of a circuit that implements
the desired control sequence in a logical and straightforward manner. The attempt to
minimize the number of gates tends to produce an irregular network making it difficult for
anyone but designer to identify the sequence of events the control undergoes. As
consequence, it is difficult to alter, service, or maintain the equipment after initial design. The
sequence of states in the control should be clearly evident from the circuit configuration even
if this requires additional components and results in a nonminimal circuit. The multiplexer
method is such an implementation.
The control circuit consists of three levels: the first level consists of multiplexers that
determine the next state. Second level contains a register that holds the present binary state.
The third level has a decoder that provides separate output for each control state.
For example we redraw the control logic circuit using multiplexer method.
P.S.
N.S.
G1 G2 G1 G2
0 0 0 0
0 0 0 1
0 1 0 1
0 1 0 1
0 1 1 1
1 1 0 0

A3
A4

0
1 MUX
2
3
S0 S1

Input
conditions
S
S
A3
A3.A4
A3.A4

Multiplexer inputs
MUX1
MUX2
0

A3.A4

F.F.

G1
T0
T1
Decoder

S
1
0

S0 S1
0
1 MUX
2
3

G2

T2

F.F.
Control circuit

CLK
Dr Oday A.L.A Ridha

82

Exercises
1. A digital system consists of two registers (R1 and R2) and a flip-flop E (as shown in the
figure below). Draw the ASM chart of the control circuit that makes the digital system count
the number of 1s in the number loaded into register R1 and store the result in R2.
Input data

Inputs= All 1s

Load E
SI=0
Shift right
Load R1

Shift register R1

Count
Load R2

Counter R2

Output count

Z=1 if R1=0
Data processor subsystem of 1s counter

Solution
T0

00

S
1
R1input,
R2All 1s

01

T1

R2R2+1

1
T2

Z
0

10

P.S.
G1 G2
0
0
0
0

N.S.
Input
Multiplexer inputs
G1 G2 conditions MUX1
MUX2
0
0
S
0
S
0
1
S

1
1

1
1

1
0

0
1

0
Z
1
E

0
1 MUX
2
3 S0 S1

none

E
E

F.F.

G1
T0

Shift R1 to E
T1

11

T3

Decoder
T2

S
0
1
E

S0 S1
0
1 MUX
2
3

G2

T3

F.F.
Control circuit

CLK

Count=R2R2+1=T1, Load R2=S.T0

Shift R1=load E=T2, Load R1=S.T0

Dr Oday A.L.A Ridha

83

2. Design a logic circuit that multiplies two numbers

Dr Oday A.L.A Ridha

84

Z
Register B

Load B

Cout

B - Multiplicand
Q - Multiplier
P - down counter,
initially hold the
length of Q (n)

Z=1 if P=0
Count
Load P

Parallel Adder

Counter P
Q1

Load E
Clear E

Register Q

Register A

E
Clear A
Load A
Shift right

Load Q
Shift right

Data processor subsystem of multiplier

Solution

T0

P.S.
G1 G2

00

S
T1 1

0
01

A0
Pn

N.S.
Input
Multiplexer inputs
conditions
G1 G2
MUX1 MUX2

none

none

10

T2
PP-1

Q1

AA+B, ECout

E0

1
Z

0
1 MUX
2
3 S0 S1

F.F.

G1
T0
T1
Decoder

11

T3

T2

Shift right AQ

0
Z

S
0
1
0

S0 S1
0
1 MUX
2
3

G2

T3

F.F.
Control circuit

CLK

Clear A=Load P=T1, Count=PP-1=T2, Load A=Load E=T2.Q1

Shift A=Shift Q=T3, Clear E=T2.Q1

Dr Oday A.L.A Ridha

85

3.Design a circuit that controls the process of mixing and heating two liquids (A and B).
The ratio between A and B in produced mixed liquid must be and at temperature of 100 C.
Design the control circuit in such away that the production is maximum.

M5

Pump

Size= 1 volume

M1

Full A

Sensor
Motor

M2

Empty
A

Size= 2 volume

100 C

M6

M3

Full B

M4

Empty C

Empty B

Heater

Start

Control and Driving circuit

Stop

Dr Oday A.L.A Ridha

86

T0

000
011

T3
0

Start

M5

1
001

T1

1 Stop
0
0

1 Stop

Heater

0
0

100 C

Full A

M1

T4

100
M5

Full B 1

Full B

0
1 Stop

M3

M3

0
T2

010
M5

0
1

100 C

0
M3

Empty
A

T1
Full A

M1

Heater
0

M6

1 Stop
0

Empty
C

Full B

Full B

0
M3

M2

Empty
B

Empty
B

0
M4

M4

T3

Dr Oday A.L.A Ridha

87

Calling Machine A

Calling Machine B

Idle state

Some states
ZA
ZA

ZB

Some states

ZB
Other states

Dr Oday A.L.A Ridha

88

Asynchronous Sequential Circuits

A sequential circuit is specified by a time sequence of inputs, outputs, and internal
states. In synchronous sequential circuit the change of internal state occurs in response to the
synchronized clock pulses. Asynchronous sequential circuits do not use clock pulses. The
change of internal state occurs when there is a change in the input variables. The memory
elements in synchronous sequential circuits are clocked flip-flops. The memory elements in
asynchronous sequential circuits are either unclocked flip-flops or time delay elements. An
asynchronous sequential circuit is often resembles a combinational circuit with feedback.
The design of asynchronous sequential circuit is more difficult than that of
synchronous circuits because of the timing problems involved in the feedback path.
Applications of Asynchronous circuits
They are used when speed of operation is important
They are more economical to use in small independent system that require only a few
components.
They are useful when the inputs signals to the system change independently to the internal
clock.
Communication between two units with each unit having its independent clock.
Knowledge of asynchronous sequential logic behavior is helpful in verifying the operation
of the total digital system in a proper manner.
Asynchronous sequential structure
The block diagram of an asynchronous sequential circuit consists of the following parts:
Combinational circuit;
k- delay elements of unclocked flip-flops;
n-input variables;
m-output variables.
n Inputs variables

X1
X2

Z1
Z2 m Output variables

Xn
y1

Combinational
Circuit

yk

Zm
Y1
Yk

Y1

k Secondary variables
(Present state)

Delay

k Excitation variables
(Next state)

Delay

DrOdayA.L.ARidha

88

Asynchronous operation
When an input variable changes its value, the secondary variables do not changed
instantaneously. It takes a certain amount of time for the signal to propagate from the input
terminals through the combinational circuit to the (Y) excitation variables where new values
are generated for the next state. These values propagate through delay elements and become
the new present state for secondary variables. For a given value of input variables the system
is stable if the circuit reaches a steady-state condition with yi=Yi for i=1, 2,, k. Otherwise
the circuit is in continuous transition and is unstable.
To ensure proper operation, asynchronous sequential circuit must be attaining a stable
state before the input is changed to a new value. Because of delays in the wires and the gate
circuit, it is impossible to have two or more input variables change at exactly the same instant
of time without uncertainty as to which one changes first. Therefore, simultaneously changes
of two or more variables are usually prohibited. This restriction means that only one input
variable can change at any one time and the time between two input changes must be longer
than the time it takes the circuit to reach a stable state. This type of operation is defined as
fundamental mode.
Analysis Asynchronous circuits
A procedure for analyzing asynchronous sequential circuit is explained through the following
example:
Example: analyze the following circuit using
transition table method.
Solution:
1) Determine all feedback loops in the circuit.
2) Designate the output of each feedback loop
with a variable Yi and corresponding input
with yi, where i represent the feedback loop
number.
3) Drive the Boolean expression for excitation variables.

Y1=x.y1+xy2, Y2=x.y1+x.y2

4) Plot the above function in a map form.

5) Combine the binary values in corresponding squares of the map to obtain the transition
table.
6) Circle those values of Y in each square that are equal to the values of y=y1y2yk in the
same column for a stable condition.
Y1=y1, Y2=y2 or Yi=yi

DrOdayA.L.ARidha

89

Y1=x.y1+xy2
y1y2
x
00
0 0
1 0

01
1
0

11
1
1

Y2=x.y1+x.y2

y1y2
x
00
0 00
1 01

y1y2
x

y1y2
x
00
0 0
1 1

10
0
1

00
00
00

01

01
11
01

01

11
11
10

11
1
0

10
0
0

10
00
10

10

11

11
11
11

01
01

10

10
10

Transition Table

01
1
1

00

Stable States

Flow table
A flow table is similar to transition table except that the internal states are symbolized
with letters rather than binary no.s. The flow table also includes the output values of the
circuit for each stable state.
Examples
x
x1x2

00

01

11

10

a,0

b,0

a a,0

a,0

a,0

b,0

c,0

b,0

b a,0

a,0

b,1

b,0

c,0

d,0

a,0

d,1

Two inputs two states

DrOdayA.L.ARidha

One inputs four states

90

Race Condition
A race is said to exist in an asynchronous sequential circuit when two or more binary
state variables change value in response to a change in an input variable. When unequal
delays are encountered, a race condition may cause the state variables to change in an
unpredictable manner. For example, if the state variables must change 00 to 11, the
difference in delays may cause the variable to change faster than the second, with the result
that the state variables change in sequence from 00 to 10 and then to 11. If the second
variable changes faster than the first, the state variables will change from 00 to 01 and then to
11. Thus the order by which the state variables change may not be known in advance. If the
final stable state that the circuit reaches does not depend on the order in which the state
variables change, the race is called a noncritical race. If it is possible to end up in two or
more different stable states depending on the order in which the state variables change, then it
is a critical race. For proper operation, critical races must be avoided.
Examples of noncritical race
X
y1y2

00
01
11
10

0
00

1
11

11

11

X
y1y2

00
01
11
10

11

0
00

1
11
01
01
11

001101
0001
00101101

0011
000111
001011

Examples of critical race

y 1y 2
x 00
0 00
1 11
0011
0001
0010

DrOdayA.L.ARidha

X
y1y2

01
01

11
11

10
10

00
01
11
10

0
00

1
11
11
11
10

0011
000111
0010

91

Race condition may be avoided by

1) Making a proper binary assignment to the state variable. They must be assign in such a
way that one state variable can change at any time when a state transition occurs in the
flow table.
2) Directing the circuit through intermediate unstable state with a single state variable
change.

Cycles
When a circuit goes through a unique sequence of unstable states, it is said to have a cycle.
X
y1y2

00
01
11
10

0
00

X
y1y2

1
01

00
01
11
10

11
10
10

00011110

0
00

1
01
11
11
10

000111

Care must be taken when using a cycle that it terminates with a stable state. If a cycle does
not terminate with a stable state, the circuit will keep going from one unstable state to
another, making the entire circuit unstable. This is demonstrated in the following example.
X
y1y2

00
01
11
10

0
00

1
01
11
10
01

011110

Stability Considerations
Consider the following circuit
Y=(y.X1).X2
x1x2
Y=X1.X2+X2.y
y 00 01 11 10
0 0 1 1 0
1 0 1 0 0
If X1X2=11 => y=0101

DrOdayA.L.ARidha

92

Circuits with latches

The use of SR latches in asynchronous sequential circuits may result in a reduction of
circuit complexity and makes these circuits resemble synchronous circuit.

NOR based latches

S

1
0
0
0
1

0
0
1
0
1

1
1
0
0
0

0
0
1
1
0

after SR=10
after SR=01

SR
y
00
0 0

01
0

11
0

10
1

Y= ((S+y)+R)=> Y=(S+y).R => Y=S.R+Ry... (1)

Since the change of SR=11 to SR=00 produces an unpredictable results (S goes to 0
first) or (R goes to 0 first), therefore we must sure that ANDing R and S always result in 0,
[RS=0].
We know that
S.R+S.R=S => S.R=S since RS=0, therefore we can write excitation function of SR
latch, expression (1), as follow

Y=S+R.y.... (2)
Expression (2) represents reduced excitation function of SR latch.
Now, to analyze a circuit with an SR latch, we must first check that Boolean condition SR=0
holds all times. We then use the reduced excitation function to analyze the circuit. However,
if it is found that both S and R can be equal to 1 at same time, then it is necessary to use the
original excitation function (expression 1).

NAND based latches

S
1
1
0
1
0

DrOdayA.L.ARidha

R
0
1
1
1
0

Q
0
0
1
1
1

Q
1
1
0
0
1

after SR=10
after SR=01

93

SR
y
00
0 1

01
1

11
0

10
0

Y=S+R.y.... (3)
We must have always S.R=0 to avoid critical race condition.

Analysis of Asynchronous circuits (with latches)

The procedure for analyzing an asynchronous sequential circuit with SR| latches can be
summarized as follows:
1. Label each latch output with Yi and its external feedback path (if any) with yi for i=1, 2
k.
2. Drive the Boolean function for Si and Ri inputs in each latch.
3. Check whether SR=0 for each NOR latch or whether SR=0 for each NAND latch. If this
condition is not satisfied, there is a possibility that the circuit may not operate properly.
4. Evaluate Y=S+R.y for each NOR latch or Y=S+R.y for each NAND latch.
5. Construct a map with the ys representing the rows and x inputs representing the columns.
6. Plot the value of Y=Y1Y2Y3Yk in the map.
7. Circle all stable states where Y=y. the resulting map is the transition table.
Example: analyze the circuit shown below

DrOdayA.L.ARidha

94

Solution:
1) Label each latch output with Yi and its external feedback path (if any) with yi for i=1,
2 k.
2) S1=X1y2,
S2=X1.X2,

R1=X1.X2
R2=X2.y1.

3) Check whether the condition SR=0 is satisfied to ensure proper operation

S1.R1=X1.y2.X1.X2. => S1.R1=0;
S2.R2=X1.X2.X2.y1. => S2.R2=0.
The condition is satisfied.
4) Evaluate Ys
Y1=S1+R1.y1 => Y1= X1.y2+ ( X1.X2).y1 => Y1= X1.y2+ X1y1+X2y1;
Y2=S2+R2.y2 => Y2= X1.X2+ (X2.y1).y2 => Y2= X1.X2+ X2y2+y2y1.
5) Constructing a map
X1X2
y1y2

00

01

11

10

00

00

00

01

00

01

01

01

11

11

11

00

11

11

10

10

00

10

11

10

Transition table

From investigation of the transition table we deduce that the circuit is stable. There is a
critical race condition when the circuit is initially in total state y1y2X1X2=1101 and X2
changes from 1 to 0. If Y1 changes to 0 before Y2, the circuit goes to total state 0100 instead
of 0000.

Implementation Example
Implement the following transition table using NOR latch.
X1X2
y
00
0 0

01
0

11
0

10
1

DrOdayA.L.ARidha

95

Solution:
y

Latch excitation table

Map for S is

Map for R is

X1X2
y
00
0 0

01
0

11
0

10
1

X1X2
y
00
0 X

01
X

11
X

10
0

The circuit is

S=X1.X2

R=X1

Debounce circuit
Input binary information in a digital system can be generated manually by means of
mechanical switches. One position of switch produces a voltage equivalent to logic 1, and
the other position equivalent logic 0.
Mechanical switches are also used to start, stop, or reset the digital system. A common
characteristic of mechanical switch is that when arm is thrown from one position to the other,
the switch contact vibrates or bounces several times before coming to a final rest.
Vout

Vcc
Vout

DrOdayA.L.ARidha

96

In a typical switch, the contact bounce may take several milliseconds to die out. This may
cause the signal to oscillate between 1 and 0 because the switch is vibrating.
To overcome this problem, the following circuit is used.

A
B

Hazards
Hazards are unwanted switching transients that may appear at the output of a circuit because
different paths exhibit different propagation delays. Hazards occur in combinational circuits,
where they may cause a temporary false output value. When this condition occurs in
asynchronous sequential circuits, it may result in a transition to a wrong stable state.

Static 1
hazard

Static 0
hazard

Dynamic
hazard
X2X3
X1
00
0

01
1

11

10

Y=X1.X2+X2.X3
To solve hazard problem we must make a connection between all separated adjacent
groups in the K-map.

Y=X1.X2+X2.X3+X1.X3
This will make the circuit a more complex but hazard-free.

DrOdayA.L.ARidha

Hazard-free
circuit

97

Essential Hazard
It is another type of hazard that may occur in asynchronous sequential circuit. An essential
hazard is caused by unequal delays along two or more paths that originate from the same
input. An excessive delay through an inverter circuit in comparison to the delay associated
with feedback path may cause such a hazard. Essential hazard cannot be corrected by adding
redundant gates such as in static hazard. The problem that they impose can be corrected by
adjacent the amount of delay in the effected path. To avoid essential hazard, each feedback
loop must be handled with individual care to ensure that the delay in the feedback path is long
enough compared to delays of other signals that originate from the input terminals.

Exercise: Draw the logic circuit of the function F in such away that circuit is a hazard free
F = (2,5,6,7,10,13,15) .
Solution:

CD
AB

00

00
01
11
10

01

11

10

1
1

1
1

F=B.D+A.C.D+B.C.D+A.B.C
Asynchronous Circuit Design
To demonstrate the procedure of designing asynchronous circuit we use the following
example
Example: Design an asynchronous logic which detects the sequence 00 10 11 on two parallel
inputs lines, X1 and X2, and gives a one output during the final combination.

Step 1: Draw state diagram from design specification then generate primitive flow-table
00
1/0

01
01

00

3/0
11

11

00

01
5/0
10

2/0
01

11

10

10

11
4/1

00
6/0

P.S.

10

11

00
1,0
1,1,-,-,1,-

N.S.
01 11
3,- -,-,- 4,3,0 5,3,- 4,1
3,- 5,0
-,- 5,-

10
2,2,0
-,6,6,6,0

1
2
3
4
5
6
Primitive flow-table

10
DrOdayA.L.ARidha

97

Step 2: The flow table is reduced to a minimum number of states

Before going further with our example, we must explain some principles concerning
table reduction:
The primitive flow table has only one stable state in each row. The table can be
reduced to a smaller number of rows if two rows or more of stable states are placed in same
row of the flow table. The grouping of stable states from separate rows into one common row
is called merging. Merging a number of stable states in the same row means that the binary
variable which ultimately assigned to merged will not change when the input variable change.
Two or more rows in the primitive flow table can be merged into one row if there are
nonconflicting states and outputs in each of the columns. Whenever one state symbol and
dont-care entries are encountered in the same column, the state is listed in the merged row.
Moreover, if the state is circled in one of the rows, it is also circled in the merged row. The
output value is included with each stable state in the merged row.
The process of reduction large primitive tables is based on what are called implication
table and the concept of equivalency. Two states are equivalent if for each possible input they
give the same output and go to the next states or to equivalent next states. The characteristic
of equivalent states is that is (a,b) imply (c,d) and (c,d) imply (a,b), then both pairs of states
are equivalent; that is, a and b equivalent as well as c and d. Implication table structure is
shown in the figure below and constructed as follows: On the left side along the vertical are
listed all the states defined in primitive table except the first, and across the bottom
horizontally are listed all the states except the last. The result is a display of all possible
combinations of two states with a square placed in the intersection of a row and a column
where the two states can be tested for equivalence. Two states that are not equivalent is
marked with a cross () in the corresponding square, while their equivalence is recorded
with a check mark (3). Some of the squares have entries of implied states that must further
investigate to determine whether they are equivalent or not. The step-by-step procedure of
filling in the squares is as follows.
1.
Place a cross in any square corresponding to a pair of states whose outputs are
not equal every input.
2.
Enter in the remaining squares the pairs of states that are implied by the pair of
states representing the squares. We do that starting from the top square in the left
column and going down and then proceeding with next column to the right.
3.
Make successive passes through the table to determine whether any additional
squares should be marked with a cross. A square in the table is crossed out if it contains
at least one implied pair that is not equivalent.
4.
All the squares that have no crosses are recorded with check marks. These
squares define pairs of equivalent states
Now it is possible to combine pairs of states into larger groups of equivalent states. The
procedure of combining pairs into larger groups is based on what are called maximal
compatible. The maximal compatible is a group of compatibles that contains all the possible

DrOdayA.L.ARidha

98

combinations of compatible states. The maximal compatible can be obtained from a merge
diagram. This diagram is a graph in which each state is represented by a dot placed along the
circumference of a circle. Lines are drawn between any two corresponding dots that form a
compatible pair. An isolated dot represents a state that is not compatible to any other state.
The condition that must be satisfied merging is that the set of chosen compatibles must
be cover all the states and must be closed. The set will cover all the states if it includes all the
states of the original state table. The closure condition is satisfied if there are no implied
states or if the implied states are included within the state. To explain the closed covering
condition we use two examples:
Example a:
a

d,e

d,e

c,f

d,e
c,f

c,f

d,e
c,f

f
b

c
d

Merge diagram

Maximal compatibles are (a,c,d) (b,e,f)

We have all states are included in this set. This satisfies the covering condition. There
are no implied states for (a,c), (a,d), (c,d), (b,e),(b,f), and (e,f), as seen from implication table,
so the closure condition is also satisfied. Therefore the primitive flow table can be merged
into two rows, one for each of the compatibles.
a

Example b:
e

b b,c 3
c

d,e 3

d b,c 3

a,d 3

b,c 3

c
d

Merge diagram

The compatible pairs derived from implication table are:

DrOdayA.L.ARidha

99

(a,b) (a,d) (b,c) (c,d) (c,e) (d,e)

From merger diagram we determine the maximal compatibles:
(a,b) (b,c) (a,d) (c,d,e)
If we choose the two compatibles (a,b) (c,d,e), the set will cover all five states of
original table. The closure condition can be checked by means of a closure table as shown
below. The implied pairs listed for each compatible are taken directly from implication table.
The implied states for (a,b) are (b,c). But (b,c) is not included in the chosen set (a,b) (c,d,e),
so this set of compatibles is not closed. A set of compatibles that will satisfy the closed
covering condition is (a,d) (b,c) (c,d,e).
Compatibles

(a,b)

(a,d)

(b,c)

(c,d,e)

Implied states

(b,c)

(b,c)

(d,e)

(a,d)
(b,c)

The set is covered because it contains all five states. Note that the same state can be
repeated more than once. The closure condition is satisfied because the implied states are
(b,c) (d,e) and (a,d), which are included in the set. An alternative satisfactory choice of closed
covered compatibles would be (a,b) (b,c) (d,e). In general there may be more than one
possible way of merging rows.
Coming back to our original example

P.S.

00
1,0
1,1,-,-,1,-

N.S.
01 11
3,- -,-,- 4,3,0 5,3,- 4,1
3,- 5,0
-,- 5,-

10
2,2,0
-,6,6,6,0

1
2
3
4
5
6
Primitive flow-table

4,5

4,5
5 2,6 2,6

4,5
6 2,6 2,6

2
1

Compatibles pairs are:

(1,2) (1,3) (3,5) (3,6) (5,6)
Maximal compatibles are
(1,2) (3,5,6) (4)

3
4

Merge diagram
DrOdayA.L.ARidha

100

Now, primitive flow table can be reduced to merged table which consists of three rows
only. New rows renamed.
P.S.
(1,2)
(3,5,6)
(4)

00
1,0
1,-,-

N.S.
01 11
3,- 4,3,0 5,0
3,- 4,1

P.S.

10
2,0
6,0
6,-

00
a,0
a,-,-

N.S.
01 11
b,- c,b,0 b,0
b,- c,1

a
b
c
Merged flow table

Merged flow table

10
a,0
b,0
b,-

Step 3: State Assignment

Once a reduced flow table has been derived for an asynchronous sequential circuit,
next step in the design is to assign binary variables to each stable state. This assignment
results in transformation of flow table to its equivalent transition table. The primary objective
in choosing a proper binary state assignment is the preventation of critical race conditions.
Critical race condition can be avoided by making a binary state assignment in such a way that
only one variable changes at any given time when state transition occurs in the flow table. To
accomplish this, it is necessary that states between which transitions occur be given adjacent
assignments.
In order to ensure that a transition table has no critical races, it is necessary to test each
possible transition between two stable states and verify that the binary state variables change
one at a time. This is a tedious process, especially when there are many rows and columns in
the table.
A race free assignment can be obtained if we add an extra row to the flow table.
a 00

b 01

0 1
0 a b
1 d c

P.S.

00
a,0
a,-,-,-

N.S.
01 11
b,- d,b,0 b,0
b,- c,1
-,- c,-

d 10
c 11

10
a,0
b,0
b,-,-

a 00
b 01
c 11
d 10
Flow table (race-free)

DrOdayA.L.ARidha

P.S.

00

N.S.
01 11

a 00 00,0 01,- 10,b 01 00,- 01,0 01,0

c 11 -,- 01,- 11,1
d 10 -,- -,- 11,Transition table

10
00,0
01,0
01,-,-

101

care must be taken when a new row is added especially when we use the dont-care condition.
New row must be didnt contain a stable state.

Step 4: Circuit implementation using RS-latches

Transition table can be used directly to derive state variables and the output.
P.N.

00

N.S.
01 11

a 00 00,0 01,- 10,b 01 00,- 01,0 01,0

c 11 -,- 01,- 11,1
d 10 -,- -,- 11,Transition table
X1X2
Y1Y2

00

N.S.
01 11

10

00 00 01 10 00
01 00 01 01 01
11 X 01 11 01
10 X X 11 X
Transition table
X1X2
Y1Y2

00

N.S.
01 11

00
01 0 0 0
11 X 0 X
10 X X X
S1=X1.X2.Y2
0

X1X2
Y1Y2

00

N.S.
01 11

00 0 1 0
01 0 X X
11 X X X
10 X X 1
S2=X1.X2+Y1

DrOdayA.L.ARidha

10
0
0
0
X

10
00,0
01,0
01,-,-

X1X2
Y1Y2

a 00
b 01
c 11
d 10

00

Output
01 11

10

Z=Y1
X1X2
Y1Y2

00
01
11
10

00

N.S.
01 11

10

R1=X1+X2
10
0
X
X
X

X1X2
Y1Y2

00
01
11
10

00

N.S.
01 11

10

R2=X1.X2

102

Integrated circuits (IC)

The components used to construct digital systems are enclosed within
integrated circuit (IC) packages.

Digital Integrated circuit classification

- Small scale integration (SSI) circuits contain several gates or flip-

flops in a single package; < 10 gates

- Medium scale integration (MSI) devices provide specific digital
functions such as decoder, counter, adder,etc; 10-100 gates
- Large scale integration (LSI) devices provide complete computer
modules such as small memory, multiplier, divider,etc; 1001000 gates
- Very large scale integration (VLSI) devices provide more
complex module such processor, large memory. >1000 gates

Special characteristics
Fan-out: specifies the number of standard loads that the output of a gate can
drive without impairing its normal operation. A standard load is usually
defined as the amount of current needed by an input of another gate on the
same IC family.
Noise margin: is the maximum noise voltage added to the input signal of a
digital circuit that does not cause undesirable change in the circuit output.
Propagation delay: The signals through a gate take a certain amount of time
to propagate from the inputs to the output. The average transition delay time

DrOdayA.L.ARidha

103

for a signal to propagate from the input to the output when the binary signals
change in value.
Power dissipation: is the supplied power required to operate the gate.

Digital IC families
Digital ICs are classified not only by their logic operation, but also
by the specific logic circuit family to which they belong. Each family has its
own basic electronic circuit upon which more complex digital circuits and
functions are developed. The basic circuit in each family is either NAND or
a NOR gate. The most popular families are:
- TTL Transistor-transistor logic, has an extensive list of digital
functions, propagation delay 3-10 ns, high level 2.4-5 volt, low level
0-.4 volt, fan-out 10-20 gates, power dissipation 2-22 mW, series
74xx, 54xx;
- ECL Emitter-coupled logic, used in systems required high-speed
operations, propagation delay < 1-2 ns, high level -0.95- -0.72 volt,
low level -1.9 - -1.6 volt, fan-out 25 gates, power dissipation 25 mW,
series 10xxx;
- CMOS Complementary Metal-oxide semiconductor, used in circuit
required low power consumption, propagation delay 25 ns, high level
VDD volt, low level 0 0.5 volt, fan-out 50 gates, power dissipation
0.1 mW, series 4xxx.
- Other families such as Integrated-injection logic (I2L), Diodetransistor logic (DTL), Resistor-transistor logic (RTL).

Comparison between CMOS and TTL families:

CMOS logic gates are made of IGFET (MOSFET) transistors rather
than bipolar junction transistors.
CMOS gate inputs are sensitive to static electricity. They may be
damaged by high voltages, and they may assume any logic level if left
floating.

DrOdayA.L.ARidha

104

 Pull-up and pull-down resistors are used to prevent a CMOS gate

input from floating if being driven by a signal source capable only of
sourcing or sinking current.
CMOS gates dissipate far less power than equivalent TTL gates, but
their power dissipation increases with signal frequency, whereas the
power dissipation of a TTL gate is approximately constant over a
wide range of operating conditions.
CMOS gate inputs draw far less current than TTL inputs, because
MOSFETs are voltage-controlled, not current-controlled, devices.
CMOS gates are able to operate on a much wider range of power
supply voltages than TTL: typically 3 to 15 volts versus 4.75 to 5.25
volts for TTL.
CMOS gates tend to have a much lower maximum operating
frequency than TTL gates due to input capacitances caused by the
MOSFET gates.

DrOdayA.L.ARidha

105

Hardware Description Languages

In electronics, a hardware description language (HDL) is a specialized computer language
used to program the structure, design and operation of electronic circuits, and most
commonly, digital logic circuits.
A hardware description language enables a precise, formal description of an electronic circuit
that allows for the
1) Documentation,
2) Automated analysis,
3) Simulation, and testing of an electronic circuit.
4) It also allows for the compilation of an HDL program into a lower level specification
of physical electronic components, such as the set of masks used to create an
integrated circuit (synthesis).
A hardware description language looks much like a programming language such as C; it is a textual
description consisting of expressions, statements and control structures. Although these languages

look similar as conventional programming languages, there are some important differences. A
hardware description language is inherently parallel, i.e. commands, which correspond to logic
gates, are executed (computed) in parallel, as soon as a new input arrives. A HDL program
mimics the behavior of a physical, usually digital system. It also allows incorporation of timing
specifications (gate delays) as well as to describe a system as an interconnection of different
components.

1. VHDL
VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description
Language. In the mid-1980s the U.S. Department of Defense and the IEEE sponsored the
development of this hardware description language with the goal to develop very high-speed
integrated circuit. It has become now one of industrys standard languages used to describe
digital systems. The other widely used hardware description language is Verilog. Both are
powerful languages that allow you to describe and simulate complex digital systems. A third
HDL language is ABEL (Advanced Boolean Equation Language) which was specifically
designed for Programmable Logic Devices (PLD). ABEL is less powerful than the other two
languages and is less popular in industry.

2. Levels of representation and abstraction

A digital system can be represented at different levels of abstraction. This keeps the
description and design of complex systems manageable. Figure 1 shows different levels of
abstraction.

106

Figure 1: Levels of abstraction: Behavioral, Structural and Physical

The highest level of abstraction is the behavioral level that describes a system in terms of what
it does (or how it behaves) rather than in terms of its components and interconnection between
them. A behavioral description specifies the relationship between the input and output signals.
This could be a Boolean expression or a more abstract description such as the Register Transfer
or Algorithmic level. As an example, let us consider a simple circuit that warns car passengers
when the door is open or the seatbelt is not used whenever the car key is inserted in the ignition
lock At the behavioral level this could be expressed as,
Warning = Ignition_on AND ( Door_open OR Seatbelt_off)
The structural level, on the other hand, describes a system as a collection of gates and
components that are interconnected to perform a desired function. A structural description
could be compared to a schematic of interconnected logic gates. It is a representation that is
usually closer to the physical realization of a system. For the example above, the structural
representation is shown in Figure 2 below.

Figure 2: Structural representation of a buzzer circuit.

VHDL allows one to describe a digital system at the structural or the behavioral level. The
behavioral level can be further divided into two kinds of styles: Data flow and Algorithmic.
The dataflow representation describes how data moves through the system. This is typically
done in terms of data flow between registers (Register Transfer level). The data flow model
makes use of concurrent statements that are executed in parallel as soon as data arrives at the
107

input. On the other hand, sequential statements are executed in the sequence that they are
specified. VHDL allows both concurrent and sequential signal assignments that will determine
the manner in which they are executed. Examples of both representations will be given later.
3. Basic Structure of a VHDL file
A digital system in VHDL consists of a design entity (circuit) that can contain other entities
(sub circuits) that are then considered components of the top-level entity. Each entity is
modeled by an entity declaration and an architecture body. One can consider the entity
declaration as the interface to the outside world that defines the input and output signals, while
the architecture body contains the description of the entity and is composed of interconnected
entities, processes and components, all operating concurrently, as schematically shown in
Figure 3 below. In a typical design there will be many such entities connected together to
perform the desired function.

Figure 3: A VHDL entity consisting of an interface (entity declaration) and a body

(architectural description).
VHDL uses reserved keywords that cannot be used as signal names or identifiers. Keywords
and user-defined identifiers are case insensitive. Lines with comments start with two adjacent
hyphens (--) and will be ignored by the compiler. VHDL also ignores line breaks and extra
spaces. VHDL is a strongly typed language which implies that one has always to declare the
type of every object that can have a value, such as signals, constants and variables.

a. Entity Declaration
The entity declaration defines the NAME of the entity and lists the input and output ports.
The general form is as follows,
entity NAME_OF_ENTITY is [ generic generic_declarations);]
port (signal_names: mode type;
signal_names: mode type;
:
signal_names: mode type);
end [NAME_OF_ENTITY] ;

108

An entity always starts with the keyword entity, followed by its name and the keyword
is. Next are the port declarations using the keyword port. An entity declaration always
ends with the keyword end, optionally [] followed by the name of the entity.

The NAME_OF_ENTITY is a user-selected identifier

signal_names consists of a comma separated list of one or more user-selected
identifiers that specify external interface signals.
mode: is one of the reserved words to indicate the signal direction:
o in indicates that the signal is an input
o out indicates that the signal is an output of the entity whose value can
only be read by other entities that use it.
o buffer indicates that the signal is an output of the entity whose value can
be read inside the entitys architecture (feedback)
o inout the signal can be an input or an output.
type: a built-in or user-defined signal type. Examples of types are bit, bit_vector,
Boolean, character, std_logic, and std_ulogic.
o bit can have the value 0 and 1 (single wire)
o bit_vector is a vector of bit values (multiple wires)
o std_logic, std_ulogic, std_logic_vector, std_ulogic_vector: can have 9
values to indicate the value and strength of a signal. Std_ulogic and
std_logic are preferred over the bit or bit_vector types.
o boolean can have the value TRUE and FALSE
o integer can have a range of integer values
o real can have a range of real values
o character any printing character
o time to indicate time
generic: generic declarations are optional and determine the local constants used
for timing and sizing (e.g. bus widths) the entity. A generic can have a default
value. The syntax for a generic follows,
generic (
constant_name: type [:=value] ;
constant_name: type [:=value] ;
:
constant_name: type [:=value] );

For the example of Figure 2 above, the entity declaration looks as follows.
-- comments: example of the buzzer circuit of fig. 2
entity BUZZER is
port (DOOR, IGNITION, SBELT: in std_logic;
WARNING: out std_logic);
end BUZZER;

The entity is called BUZZER and has three input ports, DOOR, IGNITION and SBELT and
one output port, WARNING. Notice the use and placement of semicolons! The name BUZZER
109

is an identifier. Inputs are denoted by the keyword in, and outputs by the keyword out. Since
VHDL is a strongly typed language, each port has a defined type. In this case, we specified the
std_logic type. This is the preferred type of digital signals. In contrast to the bit type that
can only have the values 1 and 0, the std_logic and std_ulogic types can have nine values.
This is important to describe a digital system accurately including the binary values 0 and 1, as
well as the
1. unknown value X;
2. the uninitialized value U;
3. - for dont care;
4. Z for high impedance;
5. L for weak 0;
6. H for weak 1;
7. W for weak unknown;
8. 0 strong 0;
9. 1 strong l .
The std_logic type is defined in the std_logic_1164 package of the IEEE library. The type
defines the set of values an object can have. This has the advantage that it helps with the
creation of models and helps reduce errors. For instance, if one tries to assign an illegal value
to an object, the compiler will flag the error.

Example1:Four-to-one multiplexer of which each input is an 8-bit word.

entity mux4_to_1 is
port (I0,I1,I2,I3: in std_logic_vector(7 downto 0);
SEL: in std_logic_vector (1 downto 0);
OUT1: out std_logic_vector(7 downto 0));
end mux4_to_1;

Example2:An example of the entity declaration of a D flip-flop with set and reset inputs is
entity dff_sr is
port (D,CLK,S,R: in std_logic;
Q,Qnot: out std_logic);
end dff_sr;

b.

Architecture body

The architecture body specifies how the circuit operates and how it is implemented. As
discussed earlier, an entity or circuit can be specified in a variety of ways, such as behavioral,
structural (interconnected components), or a combination of the above.

110

The architecture body looks as follows,

architecture architecture_name of NAME_OF_ENTITY is
-- Declarations
-- components declarations
-- signal declarations
-- constant declarations
-- function declarations
-- procedure declarations
-- type declarations
:
begin
-- Statements
:
end architecture_name;

Behavioral model
The architecture body for the example of Figure 2, described at the behavioral level, is given
below,
architecture behavioral of BUZZER is
begin
WARNING <= (not DOOR and IGNITION) or (not SBELT and
IGNITION);
end behavioral;

The header line of the architecture body defines the architecture name, e.g. behavioral, and
associates it with the entity, BUZZER. The architecture name can be any legal identifier. The
main body of the architecture starts with the keyword begin and gives the Boolean expression
of the function. We will see later that a behavioral model can be described in several other
ways. The <= symbol represents an assignment operator and assigns the value of the
expression on the right to the signal on the left. The architecture body ends with an end
keyword followed by the architecture name.
Example3: The behavioral description of a two-input AND gate.
entity AND2 is
port (in1, in2: in std_logic;
out1: out std_logic);
end AND2;
architecture behavioral_2 of AND2 is
begin
out1 <= in1 and in2;
end behavioral_2;

111

Example4: a two-input XNOR gate.

entity XNOR2 is
port (A, B: in std_logic;
Z: out std_logic);
end XNOR2;
architecture behavioral_xnor of XNOR2 is
-- signal declaration (of internal signals X, Y)
signal X, Y: std_logic;
begin
X <= A and B;
Y <= (not A) and (not B);
Z <= X or Y;
End behavioral_xnor;

The statements in the body of the architecture make use of logic operators. Logic operators
that are allowed are: and, or, nand, nor, xor, xnor and not. In addition, other
types of operators including relational, shift, arithmetic are allowed as well.
Concurrency
It is worth pointing out that the signal assignments in the above examples are concurrent
statements. This implies that the statements are executed when one or more of the signals on
the right hand side change their value (i.e. an event occurs on one of the signals). For instance,
when the input A changes, the internal signals X and Y change values that in turn causes the
last statement to update the output Z. There may be a propagation delay associated with this
change. Digital systems are basically data-driven and an event which occurs on one signal will
lead to an event on another signal, etc. The execution of the statements is determined by the
flow of signal values. As a result, the order in which these statements are given does not matter
(i.e., moving the statement for the output Z ahead of that for X and Y does not change the
outcome). This is in contrast to conventional, software programs that execute the statements in
a sequential or procedural manner.

112

Structural description
The circuit of Figure 2 can also be described using a structural model that specifies what
gates are used and how they are interconnected. The following example illustrates it.

architecture structural of BUZZER is

-- Declarations
component AND2
port (in1, in2: in std_logic;
out1: out std_logic);
end component;
component OR2
port (in1, in2: in std_logic;
out1: out std_logic);
end component;
component NOT1
port (in1: in std_logic;
out1: out std_logic);
end component;
-- declaration of signals used to interconnect gates
signal DOOR_NOT, SBELT_NOT, B1, B2: std_logic;
begin
-- Component instantiations statements
U0: NOT1 port map (DOOR, DOOR_NOT);
U1: NOT1 port map (SBELT, SBELT_NOT);
U2: AND2 port map (IGNITION, DOOR_NOT, B1);
U3: AND2 port map (IGNITION, SBELT_NOT, B2);
U4: OR2 port map (B1, B2, WARNING);
end structural;

Following the header is the declarative part that gives the components (sub circuits, gates,)
that are going to be used in the description of the circuits. In our example, we use a two- input
AND gate, two-input OR gate and an inverter. These gates have to be defined first, i.e. they
will need an entity declaration and architecture body (as shown in the previous example). These
can be stored in one of the packages (like include in C language) one refers to in the header of
the file. The declarations for the components give the inputs (e.g. in1, in2) and the output (e.g.
out1). Next, one has to define internal nets or wires (signal names). In our example these
signals are called DOOR_NOT, SBELT_NOT, B1, B2 (see the figure above). Notice that one
always has to declare the type of the signal.
The statements after the begin keyword gives the instantiations of the components and
describes how these are interconnected. A component instantiation statement creates a new
level of hierarchy. Each line starts with an instance name (e.g. U0) followed by a colon and a
component name and the keyword port map. This keyword defines how the components are
113

connected. In the example above, this is done through positional association: DOOR
corresponds to the input, in1 of the NOT1 gate and DOOR_NOT to the output. Similarly, for
the AND2 gate where the first two signals (IGNITION and DOOR_NOT) correspond to the
inputs in1 and in2, respectively, and the signal B1 to the output out1. An alternative way is to
use explicit association between the ports, as shown below.
label: component-name port map (port1=>signal1, port2=> signal2, port3=>signaln);
U0:
U1:
U2:
U3:
U4:

NOT1
NOT1
AND2
AND2
OR2

port
port
port
port
port

map
map
map
map
map

(in1
(in1
(in1
(in1
(in1

=>
=>
=>
=>
=>

DOOR, out1 => DOOR_NOT);

SBELT, out1 => SBELT_NOT);
IGNITION, in2 => DOOR_NOT, out1 => B1);
IGNITION, in2 => SBELT_NOT, B2);
B1, in2 => B2, out1 => WARNING);

Notice that the order in which these statements are written has no bearing on the execution
since these statements are concurrent and therefore executed in parallel. Indeed, the schematic
that is described by these statements is the same independent of the order of the statements.
Structural modeling of design lends itself to hierarchical design, in which one can define
components of units that are used over and over again. Once these components are defined they
can be used as blocks, cells or macros in a higher level entity. This can significantly reduce the
complexity of large designs. Hierarchical design approaches are always preferred over flat
designs.
To illustrate the use of a hierarchical design approach for a 4-bit adder shown in Figure 4 below.
Each full adder can be described by the Boolean expressions for the sum and carry out signals,
sum = (A B) C
carry = AB + C(A B)

Figure 4: Schematic of a 4-bit adder consisting of full adder modules.

In the VHDL file, we have defined a component for the full adder first. We used several
instantiations of the full adder to build the structure of the 4-bit adder. We have included the
library and use clause as well as the entity declarations.

114

Four Bit Adder Illustrating a hierarchical VHDL model

-- Example of a four bit adder
library ieee;
use ieee.std_logic_1164.all;
-- definition of a full adder
entity FULLADDER is
port (a, b, c: in std_logic;
sum, carry: out std_logic);
end FULLADDER;
architecture fulladder_behav of FULLADDER is
begin
sum <= (a xor b) xor c ;
carry <= (a and b) or (c and (a xor b));
end fulladder_behav;
-- 4-bit adder
library ieee;
use ieee.std_logic_1164.all;
entity FOURBITADD is
port (a, b: in std_logic_vector(3 downto 0);
Cin : in std_logic;
sum: out std_logic_vector (3 downto 0);
Cout, V: out std_logic);
end FOURBITADD;
architecture fouradder_structure of FOURBITADD is
signal c: std_logic_vector (4 downto 0);
component FULLADDER
port(a, b, c: in std_logic;
sum, carry: out std_logic);
end component;
begin
FA0: FULLADDER
port map (a(0), b(0), Cin, sum(0), c(1));
FA1: FULLADDER
port map (a(1), b(1), C(1), sum(1), c(2));
FA2: FULLADDER
port map (a(2), b(2), C(2), sum(2), c(3));
FA3: FULLADDER
port map (a(3), b(3), C(3), sum(3), c(4));
V <= c(3) xor c(4);
Cout <= c(4);
end fouradder_structure;

Notice that the same input names a and b for the ports of the full adder and the 4-bit adder were
used. This does not pose a problem in VHDL since they refer to different levels. However, for
readability, it may be easier to use different names. We needed to define the internal signals
c(4:0) to indicate the nets that connect the output carry to the input carry of the next full adder.
For the first input we used the input signal Cin. For the last carry we defined c(4) as an internal
signal since the last carry is needed as the input to the xor gate. We could not use the output
signal Cout since VHDL does not allow the use of outputs as internal signals! For this reason
we had to define the internal carry c(4) and assign c(4) to the output carry signal Cout.
115

H/W: Describe the following circuit using VHDL

I0
I1

Inputs
I3

0
1
.
.
.
3

161
MUX
BA

Select
hint: make use of the following circuit

116

Y1

Solution:

a) MUX4_1 using behavioral description

--------------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
entity MUX4 is
port (a, b, I0,I1,I2,I3: in std_logic;
Y: out std_logic);
end MUX4;
architecture MUX4_behav of MUX4 is
begin
Y <= ((not a)and (not b) and I0) or
((not a)and (b) and I1)
or
((a)and (not b) and I2)
or
((a)and (b) and I3);
end MUX4_behav;
--------------------------------------------

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117

b) MUX4_1 using structural description

-------------------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
entity AND3 is
port (in1, in2, in3: in std_logic;
out1: out std_logic);
end AND3;
architecture behavioral_3 of AND3 is
begin
out1 <= in1 and in2 and in3;
end behavioral_3;
--------------------------------------------entity OR4 is
port (in1, in2, in3, in4: in std_logic;
out1: out std_logic);
end OR4;
architecture behavioral_4 of OR4 is
begin
out1 <= in1 or in2 or in3 or in4;
end behavioral_4;
--------------------------------------------entity NOT1 is
port (in1: in std_logic;
out1: out std_logic);
end NOT1;
architecture behavioral_1 of NOT1 is
begin
out1 <= not in1;
end behavioral_1;
---------------------------------------------entity MUX4 is
port (a, b, I0,I1,I2,I3: in std_logic;
Y: out std_logic);
end MUX4;
architecture MUX4_str of MUX4 is
signal c: std_logic_vector (3 downto 0);
signal AN,BN: std_logic;
--------------------------------------component AND3
port(a, b, c: in std_logic; d: out std_logic);
end component;
--------------------------------------component OR4
port(a, b, c, d: in std_logic; e: out std_logic);
end component;
---------------------------------------component NOT1
port(a: in std_logic; b: out std_logic);
end component;
begin
A0: AND3 port map (AN,BN, I0, C(0));
A1: AND3 port map (AN,B, I1, C(1));
A2: AND3 port map (A,BN, I2, C(2));
A3: AND3 port map (A,B, I3, C(3));
O0: OR4 port map (C(0), C(1), C(2), C(3),Y);
N0: NOT1 port map (A,AN);
N1: NOT1 port map (A,AN);
end MUX4_str;

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Process in VHDL
A process statement is the main construct in behavioral modeling that allows you to use
sequential statements to describe the behavior of a system over time. The syntax for a process
statement is
[process_label:] process [ (sensitivity_list) ] [is]
[ process_declarations]
begin
list of sequential statements such as:
signal assignments
variable assignments
case statement
exit statement
if statement
loop statement
next statement
null statement
procedure call
wait statement
end process [process_label];

An example of a positive edge-triggered D flip-flop with asynchronous clear input follows.

---------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
entity DFF_CLEAR is
port (CLK, CLEAR, D : in std_logic;
Q : out std_logic);
end DFF_CLEAR;
architecture BEHAV_DFF of DFF_CLEAR is
begin
DFF_PROCESS: process (CLK, CLEAR)
begin
if (CLEAR = 1) then
Q <= 0;
elsif (CLKevent and CLK = 1) then
Q <= D;
end if;
end process;
end BEHAV_DFF;

------------------------------------------------------------------------------------------------A process is declared within an architecture and is a concurrent statement. However, the
statements inside a process are executed sequentially. Like other concurrent statements, a
process reads and writes signals and values of the interface (input and output) ports to
communicate with the rest of the architecture. One can thus make assignments to signals that
are defined externally (e.g. interface ports) to the process, such as the Q output of the flip- flop

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119

in the above example. The expression CLKevent and CLK = 1 checks for a positive
clock edge (clock event AND clock high).
The sensitivity list is a set of signals to which the process is sensitive. Any change in the value
of the signals in the sensitivity list will cause immediate execution of the process. If the
sensitivity list is not specified, one has to include a wait statement to make sure that the process
will halt. Notice that one cannot include both a sensitivity list and a wait statement. Variables
and constants that are used inside a process have to be defined in the process_declarations part
before the keyword begin. The keyword begin signals the start of the computational part of the
process. The statements are sequentially executed, similarly as a conventional software
program. It should be noted that variable assignments inside a process are executed
immediately and denoted by the := operator. This is in contrast to signal assignments denoted
by <= and which changes occur after a delay. As a result, changes made to variables will be
available immediately to all subsequent statements within the same process.
The previous example of the D flip-flop illustrates how to describe a sequential circuit with the
process statement. Although the process is mainly used to describe sequential circuits, one can
also describe combinational circuits with the process construct. The following example
illustrates this for a Full Adder, composed of two Half Adders. This example also illustra tes
how one process can generate signals that will trigger other processes when events on the
signals in its sensitivity list occur. We can write the Boolean expression of a Half Adder and
Full Adder as follows:
S_ha = (AB)

and C_ha = AB

For the Full Adder:

Sum = (AB)Cin = S_ha Cin
Cout = (AB)Cin + AB = S_ha.Cin + C_ha
Figure 5 illustrates how the Full Adder has been modeled.
FullAdder

Figure 5: Full Adder composed of two Half Adders, modeled with two processes P1 and P2.

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120

----------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
entity FULL_ADDER is
port (A, B, Cin : in std_logic;
Sum, Cout : out std_logic);
end FULL_ADDER;
architecture BEHAV_FA of FULL_ADDER is
signal int1, int2, int3: std_logic;
begin
-- Process P1 that defines the first half adder
P1: process (A, B)
begin
int1<= A xor B;
int2<= A and B;
end process;
-- Process P2 that defines the second half adder and the OR -gate
P2: process (int1, int2, Cin)
begin
Sum <= int1 xor Cin;
int3 <= int1 and Cin;
Cout <= int2 or int3;
end process;
end BEHAV_FA;

--------------------------------------------------------------------------------------------One could simplify the behavioral model significantly by using a single process.

H/W: write VHDL code to model full adder using single process

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121

a. Signal assignment
Signal assignments are event triggered and executed as soon as an event on one of the
signals occurs. There are three types of signal assignment
1) Simple Concurrent signal assignments.
The syntax is as follows:
Target_signal <= expression;
Examples
Sum <= (A xor B) xor Cin;
Carry <= (A and B);
Z <= (not X) or Y after 2 ns;

2) Conditional Signal assignments

The syntax for the conditional signal assignment is as follows:
Target_signal <= expression when Boolean_condition
else expression when Boolean_condition
else expression;

The target signal will receive the value of the first expression whose Boolean condition is
TRUE. If no condition is found to be TRUE, the target signal will receive the value of the
final expression. If more than one condition is true, the value of the first condition that is
TRUE will be assigned.
Example: 4-to-1 multiplexer using conditional signal assignments
entity MUX_4_1_Conc is
port (S1, S0, A, B, C, D: in std_logic;
Z: out std_logic);
end MUX_4_1_Conc;
architecture concurr_MUX41 of MUX_4_1_Conc is
begin
Z <= A when S1=0 and S0=0 else
B when S1=0 and S0=1 else
C when S1=1 and S0=0 else
D;
end concurr_MUX41;

The conditional signal assignment will be re-evaluated as soon as any of the signals in the
conditions or expression change. The when-else construct is useful to express logic function in
the form of a truth table.

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122

Example: 4_to_1 multiplexer using a more compact form.

entity MUX_4_1_funcTab is
port (A, B, C, D: in std_logic;
SEL: in std_logic_vector (1 downto 0);
Z: out std_logic);
end MUX_4_1_ funcTab;
architecture concurr_MUX41 of MUX_4_1_ funcTab is
begin
Z <= A when SEL = 00 else
B when SEL = 01 else
C when SEL = 10 else
D;
end concurr_MUX41;

3) Selected Signal assignments

The selected signal assignment is similar to the conditional one described above. The syntax
is as follows,
with choice_expression select
target_name <= expression when choices,

target_name <= expression when choices;

The target is a signal that will receive the value of an expression whose choice includes the
value of the choice_expression. The expression selected is the first with a matching choice.
The choice can be a static expression (e.g. 5) or a range expression (e.g. 4 to 9). The
following rules must be followed for the choices:

No two choices can overlap

All possible values of choice_expression must be covered by the set of choices, unless
an others choice is present.

Example:4-to-1 multiplexer is given below.

entity MUX_4_1_Conc2 is
port (A, B, C, D: in std_logic;
SEL: in std_logic_vector(1 downto 0);
Z: out std_logic);
end MUX_4_1_Conc2;
architecture concurr_MUX41b of MUX_4_1_Conc2 is
begin
with SEL select
Z <= A when 00,
B when 01,
C when 10,
D when 11;
end concurr_MUX41b;

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123

The equivalent process statement would make use of the case construct. Similarly to the whenelse construct, the selected signal assignment is useful to express a function as a truth table, as
illustrated above.
The choices can express a single value, a range or combined choices as shown below.
target <= value1 when 000,
value2 when 001 | 011
value3 when others;

| 101 ,

In the above example, all eight choices are covered and only once. The others choice must the
last one used.

b. wait statements
The wait statement will halt a process until an event occurs. There are several forms
of the wait statement,
a)
b)
c)
Examples
wait
wait
wait
wait

wait until condition;

wait for time expression;
wait on signal;

until
until
until
until

CLK=1;
CLK=0;
CLKevent and CLK=1;
not CLKstable and CLK=1;

For the first example the process will wait until a positive-going clock edge occurs, while for
the second example, the process will wait until a negative-going clock edge arrives. The last
two examples are equivalent to the first one (positive-edge or 0-1 transitions). The hardware
implementation for these three statements will be identical.
It should be noted that a process that contains a wait statement can not have a sensitivity list.
If a process uses one or more wait statements, the Foundation Express synthesizer will use
sequential logic. The results of the computations are stored in flip-flops.

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124

c. If Statements
The if statement executes a sequence of statements whose sequence depends on one or more
conditions. The syntax is as follows:
if condition then
sequential statements
[elsif condition then
sequential statements ]
[else
sequential statements ]
end if;

Each condition is a Boolean expression. The if statement is performed by checking each

condition in the order they are presented until a true is found. Nesting of if statements is
allowed. An example of an if statement was given earlier for a D Flip-flop with asynchrono us
clear input. The if statement can be used to describe combinational circuits as well. The
following example illustrates this for a 4-to-1 multiplexer with inputs A, B, C and D, and select
signals S0 and S1. This statement must be inside a process construct. We will see that other
constructs, such as the Conditional Signal Assignment (When-else) or Select construct
may be more convenient for these type of combinational circuits.
Example: 4_1 multiplexer
entity MUX_4_1a is
port (S1, S0, A, B, C, D: in std_logic;
Z: out std_logic);
end MUX_4_1a;
architecture behav_MUX41a of MUX_4_1a is
begin
P1: process (S1, S0, A, B, C, D)
begin
if (( not S1 and not S0 )=1) then
Z <= A;
elsif (( not S1 and S0) = 1) then
Z<=B;
elsif ((S1 and not S0) =1) then
Z <=C;
else
Z<=D;
end if;
end process P1;
end behav_MUX41a;

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A slightly different way of modeling the same multiplexer is shown below,

if S1=0 and S0=0 then
Z <= A;
elsif S1=0 and S0=1 then
Z <= B;
elsif S1=1 and S0=0 then
Z <= C;
elsif S1=1 and S0=1 then
Z <= D;
end if;

If statements are often used to implement state diagrams.

d. Case statements
The case statement executes one of several sequences of statements, based on the value of a
single expression. The syntax is as follows,
case expression is
when choices =>
sequential statements
when choices =>
sequential statements
-- branches are allowed
[ when others => sequential statements ]
end case;

The expression must evaluate to an integer, an enumerated type of a one-dimensional array,

such as a bit_vector. The case statement evaluates the expression and compares the value to
each of the choices. The when clause corresponding to the matching choice will have its
statements executed. The following rules must be adhered to:

no two choices can overlap (i.e. each choice can be covered only once)
if the when others " choice is not present, all possible values of the expression must
be covered by the set of choices.

Example

An example of a case statement using an enumerated type follows. It gives an output D=1 when
the signal GRADES has a value between 51 and 60, C=1 for grades between 61 and 75, B=1
for grades between 76 and 85, A=1 for grades between 86 and 100, the when others covers all
the other grades and result in an F=1.
entity GRD_201 is
port(VALUE: in integer range 0 to 100;
A, B, C, D: out bit);
end GRD_201;
architecture behav_grd of GRD_201 is
begin
process (VALUE)
A <= 0;
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126

B <= 0;
C <= 0;
D <= 0;
F <= 0;
begin
case VALUE is
when 51 to 60 =>
D <= 1;
when 61 to 70 | 71 to 75 =>
C <= 1;
when 76 to 85 =>
B <= 1;
when 86 to 100 =>
A <= 1;
when others =>
F <= 1;
end case;
end process;
end behav_grd;

We used the vertical bar ( | ) which is equivalent to the or operator, to illustrate how to
express a range of values. This is a useful operator to indicate ranges that are not adjacent
(e.g. 0 to 4 | 6 to 10).

Example: using the case construct is a 4-to-1 MUX.

entity MUX_4_1 is
port ( SEL: in std_logic_vector(2 downto 1);
A, B, C, D: in std_logic;
Z: out std_logic);
end MUX_4_1;
architecture behav_MUX41 of MUX_4_1 is
begin
PR_MUX: process (SEL, A, B, C, D)
begin
case SEL is
when 00 => Z <= A;
when 01 => Z <= B;
when 10 => Z <= C;
when 11 => Z <= D;
when others => Z <= X;
end case;
end process PR_MUX;
end behav_MUX41;

The when others covers the cases when SEL=0X, 0Z, XZ, UX, etc. It should be
noted that these combinational circuits can be expressed in other ways, using concurrent
statements such as the With Select construct. Since the case statement is a sequential
statement, one can have nested case statements.

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127

e. Loop statements
A loop statement is used to repeatedly execute a sequence of sequential statements. The
syntax for a loop is as follows:
[ loop_label :]iteration_scheme loop
sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop [loop_label];

Labels are optional but are useful when writing nested loops. The next and exit statement are
sequential statements that can only be used inside a loop.

The next statement terminates the rest of the current loop iteration and execution will
proceed to the next loop iteration.
The exit statement skips the rest of the statements, terminating the loop entirely, and
continues with the next statement after the exited loop.

There are three types of iteration schemes:

1) basic loop
2) while loop
3) for loop

1)

Basic Loop statement

This loop has no iteration scheme. It will be executed continuously until it encounters an exit
or next statement.
[ loop_label :] loop
sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop [ loop_label];

The basic loop (as well as the while-loop) must have at least one wait statement. As an
example, lets consider a 5-bit counter that counts from 0 to 31. When it reaches 31, it will start
over from 0. A wait statement has been included so that the loop will execute every time the
clock changes from 0 to 1.

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128

Example: a basic loop to implement a counter that counts from 0 to 31

entity COUNT31 is
port ( CLK: in std_logic;
COUNT: out integer);
end COUNT31;
architecture behav_COUNT of COUNT31 is
begin
P_COUNT: process
variable intern_value: integer :=0;
begin
COUNT <= intern_value;
loop
wait until CLK=1;
intern_value:=(intern_value + 1) mod 32;
COUNT <= intern_value;
end loop;
end process P_COUNT;
end behav_COUNT;

We defined a variable intern_value inside the process because output ports cannot be read
inside the process.

2)While-Loop statement
The while loop evaluates a Boolean iteration condition. When the condition is TRUE, the
loop repeats, otherwise the loop is skipped and the execution will halt. The syntax for the
whileloop is as follows,
[ loop_label :] while condition loop
sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop[ loop_label ];

The condition of the loop is tested before each iteration, including the first iteration. If it is
false, the loop is terminated.

3) For-Loop statement
The for-loop uses an integer iteration scheme that determines the number of iterations. The
syntax is as follows,
[ loop_label :] for identifier in range loop
sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop[ loop_label ];

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129

The identifier (index) is automatically declared by the loop itself, so one does not need
to declare it separately. The value of the identifier can only be read inside the loop and
is not available outside its loop. One cannot assign or change the value of the index.
This is in contrast to the while-loop whose condition can involve variables that are
modified inside the loop.
The range must be a computable integer range in one of the following forms, in which
integer_expression must evaluate to an integer:
o integer_expression to integer_expression
o integer_expression downto integer_expression

Next and Exit Statement

The next statement skips execution to the next iteration of a loop statement and proceeds with
the next iteration. The syntax is
next [label] [when

condition];

The when keyword is optional and will execute the next statement when its condition evaluates
to the Boolean value TRUE.
The exit statement skips the rest of the statements, terminating the loop entirely, and continues
with the next statement after the exited loop. The syntax is as follows:
exit [label] [when

condition];

The when keyword is optional and will execute the next statement when its condition evaluates
to the Boolean value TRUE.
Notice that the difference between the next and exit statement, is that the exit statement
terminates the loop.

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130

Example of a Mealy Machine

The sequence following detector recognizes the input bit sequence X: "1011". The machine
will keep checking for the proper bit sequence and does not reset to the initial state after it
recognizes the string. In case we are implementing a Mealy machine, the output is associated
with the transitions as indicated on the following state diagram (Figure 6).

Figure 6: Sequence detector (1011), realized as a Mealy Machine.

The VHDL code is given below.
---------------------------------------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
entity myvhdl is
port (CLK, RST, X: in STD_LOGIC;
Z: out STD_LOGIC);
end;
architecture myvhdl_arch of myvhdl is
-- SYMBOLIC ENCODED state machine: Sreg0
type Sreg0_type is (S0, S1, S2, S3);
signal Sreg0: Sreg0_type;
begin
--concurrent signal assignments
Sreg0_machine: process (CLK)
begin
if CLK'event and CLK = '1' then
if RST='1' then
Sreg0 <= S0;
else
case Sreg0 is
when S0 =>
if X='0' then
Sreg0 <= S0;
elsif X='1' then
Sreg0 <= S1;
end if;
when S1 =>
if X='1' then
Sreg0 <= S1;
elsif X='0' then
Sreg0 <= S2;
end if;
when S2 =>
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131

if X='1' then
Sreg0 <= S3;
elsif X='0' then
Sreg0 <= S0;
end if;
when S3 =>
if X='0' then
Sreg0 <= S2;
elsif X='1' then
Sreg0 <= S1;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
-- signal assignment statements for combinatorial outputs
Z_assignment:
Z <= '0' when (Sreg0 = S0 and X='0') else
'0' when (Sreg0 = S0 and X='1') else
'0' when (Sreg0 = S1 and X='1') else
'0' when (Sreg0 = S1 and X='0') else
'0' when (Sreg0 = S2 and X='1') else
'0' when (Sreg0 = S2 and X='0') else
'0' when (Sreg0 = S3 and X='0') else
'1' when (Sreg0 = S3 and X='1') else
'1';
end myvhdl_arch;
------------------------------------------------------------------------------------------------------

H/W 1: Write necessary VHDL code for describing the synchronous sequential
circuit whose its state diagram is shown below

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132

H/W 2: For the circuit of a multiplier, whose its data processor is shown below,
write necessary VHDL code for describing only the control circuit of it. Use
algorithmic state machine diagram shown below for your answer.

Z
Loa d B

Cout

Register B

Z=1 if P=0
Count

Parallel Adder

Cl ea r E

Register A
Loa d Q

Loa d A

Shi ft ri ght

Data processor subsystem of multiplier

T0

00

S
1

T1

0
01

A0

10

T2
PP-1

Q1

E0

AA+B, ECout

11

T3

Shift right AQ

0
Z

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133

P - down counter,

Q1
Register Q

Cl ea r A

Q - Multiplier

Counter P

Loa d P
Loa d E

B - Multiplicand