Phase locked loop

2014

B M S COLLEGE OF ENGINEERING
(Autonomous Institution under Visvesvaraya Technological University, Belgaum)

Report On
Open End Experiment

Phase locked loop

Submitted in partial fulfilment for the award of degree in

Bachelor of Engineering in Telecommunication Engineering
By

Student Name

USN

SANDEEP KUMAR S

1BM12TE044

SHASHANK K R

1BM12TE050

2014 - 2015
Department of Telecommunication Engineering

B.M SREENIVASAIAH COLLEGE OF ENGINEERING

Bull Temple Road, Basavanagudi, Bangalore - 560019

DEPARTMENT OF
TELECOMMUNICATION,BMSCE

Phase locked loop

2014

PHASE LOCKED LOOP

A phase-locked loop or phase lock loop (PLL) is a control system that
generates an output signal whose phase is related to the phase of an
input signal. It is an electronic circuit with a voltage- or currentdriven oscillator that is constantly adjusted to match in phase (and
thus lock on) the frequency of an input signal.

COMPONENTS

BLOCK DIAGRAM OF A PLL

The basic PLL block diagram is given above. It consists of 4 main parts1. Phase detector - It detects and compares the input frequency and
the VCO frequency. It generates a DC voltage which is proportional
to the phase difference between the 2 frequencies. There are
different circuits employed for this purpose - eg. Double-balanced
mixer, edge triggered, and monolithic phase detectors.
2. Low pass filter - It removes the high frequency components
(including noise) in the output of the phase detector. It controls
dynamic characteristics of the PLL, such as capture and lock ranges,
bandwidth and transient response.
3. Voltage controlled oscillator - It generates an output frequency that
is directly proportional to the input voltage.

DEPARTMENT OF
TELECOMMUNICATION,BMSCE

Phase locked loop

2014

4. Feedback path - Feedback is required to supply the output of the

VCO back to the phase detector.

OPERATING PRINCIPLE
1. Before input is applied, the PLL is in free running mode.
2. The phase detector, or comparator compares the input frequency fIN
with the feedback frequency fOUT. The output is proportional to that
phase difference between fIN and fOUT.
3. The output of the phase detector is supplied to the low pass filter,
which removes the high frequency noise and produces a DC level.
4. The above DC level is given as input to the VCO (voltage controlled
oscillator).
5. The output of the VCO is directly proportional to the input dc level.
The VCO frequency is compared with the input frequency fIN and
adjusted till it is equal to the input frequency. This is the capture
mode of the PLL.
6. When the VCO frequency becomes equal to the input frequency, it is
in the phase locked state.

MONOLITHIC (IC) PLLs

For this experiment, we make use the IC565, which is a monolithic PLL
manufactured by Signetics Corporation. It is available in either a 14 pin
DIP package or a 10 pin metal can.

DEPARTMENT OF
TELECOMMUNICATION,BMSCE

Phase locked loop

2014

The important characteristics of this IC are 1. Operating frequency range: 0.001 Hz to 500 kHz
2. Operating voltage range: +/- 6 V to +/- 12 V
3. Input level for tracking: 10 mV to 3 V (peak-to-peak)
4. Input impedance: 10 k
5. Output sink/source current: 1 mA/10 mA
6. Drift in VCO center frequency: 300 ppm/ C
7. Drift in VCO center frequency with supply voltage: 1.5 %/V

DESIGN
Centre frequency of PLL fOUT = 1.2/4R1C1 Hz i)
Lock frequency fL = +/- 8fOUT/V Hz, where V = +V - (-V) volts (supply
voltages) ii)
DEPARTMENT OF
TELECOMMUNICATION,BMSCE

Phase locked loop

2014

Capture frequency fC = +/- [fL/(2*3.6*1000*C2)]1/2 Hz ..

iii)

From the above circuit diagram,

R1 = 12 k
C1 = 0.01 F
C2 = 10 F

Substituting the above values in equations i, ii, iii, we get the

theoretical values

fOUT = 2.5 kHz, fL = +/- 1 kHz, fC = +/- 66.85 Hz

DEPARTMENT OF
TELECOMMUNICATION,BMSCE

Phase locked loop

2014

We obtain the practical relationship between the 3 frequency

parameters

Where fOUT = 4.1 kHz, fL = 1.5 to 6.2 kHz, fC = 3.5 to 4.7 kHz

APPLICATIONS OF PLL
1. Frequency multiplier - In this application, a frequency divider is
inserted between the VCO and the phase detector. Since the
output of the divider is locked to the input frequency fIN, the VCO
is running at a multiple of the input frequency. Desired amount of
multiplication N can be obtained by inserting a divide-by-N
network in the feedback loop.
2. Frequency shift keying (FSK) modulator
DEPARTMENT OF
TELECOMMUNICATION,BMSCE

Phase locked loop

2014

3. Demodulation of FM The most important application of PLL is in

the demodulation of FM waves. The output of the low-pass filter
is directly proportional to the original modulating signal.

PROGRAM OUTCOMES
PO3 Ability to design solutions for systems/sub-systems that meet
desired specifications
PO5 Ability to design, formulate and conduct experiments using
electronic components,

electronic instruments and/or modern

engineering tools to demonstrate concepts

PO9 Ability to function effectively as an individual, and as a member/
leader in a team
PO10 Ability to communicate effectively, write reports and make
effective presentation
PO12 Ability to engage in independent learning and continuously
upgrade knowledge

COURSE OUTCOMES
CO5, CO6

REFERENCES
Communication systems Simon Haykin
Op-amps and LICs - Ramakant A. Gayakwad

DEPARTMENT OF
TELECOMMUNICATION,BMSCE