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General Description
The 318 encoders are a series of CMOS LSIs for
remote control system applications. They are
capable of encoding 18 bits of information
which consists of N address bits and 18-N data
bits. Each address/data input is externally
trinary programmable if bonded out. It is otherwise set floating internally. Various packages of
the 318 encoders offer flexible combinations of
Selection Table
Function Address Address/
No.
Data No.
Part No.
Data
No.
Dummy
Code No.
Oscillator
Trigger
Package
HT600
RC oscillator
TE
20 DIP/SOP
HT680
RC oscillator
TE
18 DIP/SOP
HT6207
10
RC oscillator
D12~D15
20 DIP/SOP
Note: Address/Data represents addressable pins or data according to the decoder requirements.
HT600/680/6207
Block Diagram
TE trigger
HT600/HT680
O S C 2
O S C 1
O s c illa to r
3 3 D iv id e r
D a ta S e le c t
& B u ffe r
D O U T
T E
A 0
1 8
T r a n s m is s io n
G a te C ir c u it
A 9
A D 1 0
1 8 C o u n te r
& 1 o f 1 8
D e c o d e r
S y n c .
C ir c u it
T r in a r y
D e te c to r
A D 1 7
V D D
V S S
DATA trigger
HT6207
O S C 2
O S C 1
O s c illa to r
3 3 D iv id e r
A 0
1 8
T r a n s m is s io n
G a te C ir c u it
A 1 1
D 1 2
D 1 7
1 8 C o u n te r
& 1 o f 1 8
D e c o d e r
T r in a r y
D e te c to r
D a ta S e le c t
& B u ffe r
D O U T
S y n c .
C ir c u it
L E D
C ir c u it
V D D
V S S
L E D
HT600/680/6207
Pin Assignment
D A T A
T E tr ig g e r ty p e
9 -A d d re s s
5 -A d d r e s s /D a ta
8 -A d d re s s
4 -A d d r e s s /D a ta
A D 1 1
2 0
V D D
A D 1 2
1 9
A 9
A D 1 3
A D 1 4
1 8
A 8
1 7
A 7
A D 1 5
1 6
A 6
D O U T
T E
6
1 5
7
O S C 2
O S C 1
V S S
tr ig g e r ty p e
1 0 -A d d re s s
4 -D a ta
A 1 1
1
2 0
V D D
1 7
V D D
A 9
D 1 2
D 1 3
1 9
A 9
1 8
A 8
1 6
A 8
1 5
A 7
D 1 4
1 7
A 7
D O U T
1 4
A 6
1 6
A 6
T E
1 3
1 5
A 4
A 3
D 1 5
D O U T
1 2
A 2
1 4
A 3
A 1
O S C 2
O S C 1
L E D
1 1
A 1
1 3
A 2
A 0
V S S
1 0
A 0
A D 1 1
A D 1 2
1 8
2
A D 1 4
A D 1 5
1 4
A 4
A 3
1 3
A 2
1 2
1 0
1 1
H T 6 0 0
2 0 D IP /S O P
O S C 2
O S C 1
9
1 2
A 1
1 0
1 1
A 0
V S S
H T 6 8 0
1 8 D IP /S O P
H T 6 2 0 7
2 0 D IP /S O P
Pin Description
Pin Name
I/O
Internal
Connection
Description
A0~A11
AD10~AD17
D12~D15
CMOS IN
Pull-low
DOUT
CMOS OUT
LED
NMOS OUT
TE
CMOS IN
Pull-low
OSC1
OSCILLATOR
OSC2
OSCILLATOR
VSS
VDD
Note: D12~D15 are data input and transmission enable pins of the HT6207.
TE is the transmission enable pin of the HT600/HT680.
HT600/680/6207
Approximate internal connections
T R A N S M IS S IO N
G A T E
C M O S IN
P u ll- lo w
C M O S O U T
N M O S O U T
O S C IL L A T O R
E N
O S C 1
O S C 2
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged
exposure to extreme conditions may affect device reliability.
HT600/680/6207
Electrical Characteristics
Symbol
Parameter
Ta=25C
Test Conditions
Min.
Typ.
Max.
Unit
2.4
12
0.1
mA
mA
250
500
mA
12V
No load
fOSC=100kHz
1200
2400
mA
5V
VLED=0.5V
1.5
mA
5V
VOH=0.9VDD (Source)
-0.6
-1.2
mA
5V
VOL=0.1VDD (Sink)
0.6
1.2
mA
VDD
Conditions
VDD
Operating Voltage
ISTB
Standby Current
IDD
Operating Current
ILED
IDOUT
VIH
H Input Voltage
0.8VDD
VDD
VIL
L Input Voltage
0.2VDD
fOSC
Oscillator Frequency
10V
ROSC=330kW
100
kHz
RTE
TE Pull-low Resistance
5V
VTE=5V
1.5
MW
RDATA
D12~D17 Pull-low
Resistance
5V
VDATA=5V
1.5
MW
3V
12V
5V
Oscillator stops
HT600/680/6207
Functional Description
Operation
The 318 series of encoders begins a three-word transmission cycle upon receipt of a transmission enable (TE for the HT600/HT680 or D12~D15 for the HT6207, active high). This cycle will repeat itself
as long as the transmission enable (TE or D12~D15) is held high. Once the transmission enable falls
low, the encoder output completes its final cycle and then stops as shown below.
T E o r
D 1 2 ~ D 1 5
< 1 w o rd
E n c o d e r
D a ta O u t
T r a n s m itte d
C o n tin u o u s ly
3 w o rd s
3 w o rd s
Transmission timing
Information word
An information word consists of four periods as shown:
1 /6 b it
P ilo t p e r io d
( 6 b its )
A d d r e s s c o d e p e r io d
S y n c . p e r io d
D a ta c o d e p e r io d
Composition of information
Address/data waveform
Each programmable address/data pin can be externally set to one of the following three logic states:
fo s c 3 3
"O n e "
"Z e ro "
"O p e n "
A d d r e s s /D a ta B it
HT600/680/6207
Address/data programming (preset)
The status of each address/data pin can be individually preset to logic high, low, or floating. If a
transmission enable signal is applied, the encoder scans and transmits the status of the 18 bits of address/data serially in the order A0 to AD17 for the HT600/HT680 and A0 to D15 for the HT6207.
There are some packaging limitations. For example t he 18-pin DIP HT680, offers four external data
bits and eight external address bits. The remaining unpackaged bits or dummy codes are treated as
floating for A0~AD17 or as pull-low for D12~D15. During an information transmission these bits are
still located in their original position. But if the trigger signal is not applied, the chip only consumes a
standby current which is less than 1mA.
The address pins are usually preset to transmit data codes with particular security codes by the DIP
switches or PCB wiring, while the data is selected using push buttons or electronic switches.
The following figure shows an application using the HT680:
O S C 1
O S C 2
T r a n s m is s io n
m e d iu m
D O U T
V S S
A 0
A 1
A 2
A 3
A 6
A 7
A 8
V D D
A 9
T E
A D 1 1 A D 1 2 A D 1 4 A D 1 5
D D
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AD10 AD11
Z
Z: floating
HT600/680/6207
Address/Data sequence
The following provides a table of address/data sequence for various models of the 318 series encoders. A
correct device should be selected according to the individual address and data requirementss.
Part No.
Address/Data Bits
0~3
6~9
10
11
12
13
14
15
16
17
HT600
A0~A3 A4
A6~A9
HT680
A0~A3
A6~A9
AD11 AD12
HT6207
A0~A3 A4
A6~A9
A11
D12
D13
AD14 AD15
D14
D15
Note: is a dummy code which is left open and not bonded out.
Transmission enable
For the TE trigger type of encoders, transmission is enabled by applying a high signal to the TE pin.
But for the Data trigger type of encoders, it is enabled by applying a high signal to one of the data
pins D12~D15.
Flowchart
P o w e r o n
S ta n d b y m o d e
N o
T r a n s m is s io n
e n a b le d ?
Y e s
3 d a ta w o rd s
tr a n s m itte d
N o
T r a n s m is s io n
s till e n a b le d ?
Y e s
3 d a ta w o rd s
tr a n s m itte d
c o n tin u o u s ly
HT600/680/6207
Oscillator frequency vs supply voltage
fo s c
(S c a le )
R o s c (W )
3 .0 0
2 .7 5
1 2 0 k
2 .5 0
2 .2 5
1 5 0 k
2 .0 0
1 8 0 k
1 .7 5
1 .5 0
2 2 0 k
1 .2 5
2 7 0 k
3 3 0 k
(1 0 0 k H z ) 1 .0 0
3 9 0 k
4 7 0 k
5 6 0 k
6 8 0 k
8 2 0 k
1 M
1 .5 M
2 M
0 .7 5
0 .5 0
0 .2 5
2
1 0
1 1
1 2
1 2 .5
V
D D
(V D C )
HT600/680/6207
Application Circuits
T r a n s m itte r C ir c u it
V
1
2
A D 1 1
V D D
A D 1 2
3
A 9
A D 1 4
4
A 8
A D 1 5
5
6
7
A 7
D O U T
A 6
T E
A 3
O S C 2
R o s c
8
9
A 2
O S C 1
A 1
V S S
A 0
T r a n s m itte r C ir c u it
D D
1 8
1
1 7
2
1 6
3
1 5
4
1 4
5
1 3
6
1 2
7
1 1
8
1 0
R o s c
H T 6 8 0
9
1 0
A D 1 1
V D D
A D 1 2
A 9
A D 1 3
A 8
A D 1 4
A 7
A D 1 5
A 6
D O U T
A 4
T E
A 3
O S C 2
A 2
O S C 1
A 1
V S S
A 0
D D
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
H T 6 0 0
T r a n s m itte r C ir c u it
V
1
2
3
4
5
6
1 k W
7
8
R o s c 9
1 0
A 1 1
V D D
D 1 2
A 9
D 1 3
A 8
D 1 4
A 7
D 1 5
A 6
D O U T
A 4
L E D
A 3
O S C 2
A 2
O S C 1
A 1
V S S
A 0
D D
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
H T 6 2 0 7
10
HT600/680/6207
11