International Journal of Electronics and Communication Engineering & Technology

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Volume 7, Issue 2, March-April 2016, pp. 09-17, Article ID: IJECET_07_02_002
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AN EFFICIENT ALGORITHM FOR

WRAPPER AND TAM CO-OPTIMIZATION
TO REDUCE TEST APPLICATION TIME IN
CORE BASED SOC
Harikrishna Parmar
ECC Department, Nirma University
Ahmedabad, India
Dr.Usha Mehta
ECC Department, Nirma University
Ahmedabad, India
ABSTRACT
System-on-Chip (SOC) designs composed of many embedded cores are
ubiquitous in todays integrated circuits. Each of these cores requires to be
tested separately after manufacturing of the SoC. Thats why, modular testing
is adopted for core-based SoCs, as it promotes test reuse and permits the
cores to be tested without comprehensive knowledge about their internal
structural details. Such modular testing triggers the need of a special test
access mechanism (TAM) to build communication between core I/Os and
TAM and promises to minimize overall test time. In this paper, various issues
are analyzed to optimize the Wrapper and TAM, which comprises the optimal
partitioning of TAM width, assignment of cores to partitioned TAM width etc.
Key words: TAM; SOC; Core Assignment; Test Bus Architecture, Test
Wrapper
Cite this Article: Harikrishna Parmar and Dr.Usha Mehta. An Efficient
Algorithm For Wrapper and Tam Co-Optimization To Reduce Test
Application Time In Core Based SOC. International Journal of Electronics
and Communication Engineering & Technology, 7(2), 2016, pp. 09-17.
http://www.iaeme.com/IJECET/issues.asp?JType=IJECET&VType=7&IType=2

1. INTRODUCTION
A conceptual modular testing is presented in [1], which includes three structural
elements. 1. Test pattern source, 2. Sink and 3. The TAM and the test wrapper. Now a
day, In large SoC, embedded cores are commonplace. Since embedded cores are not
straight away approachable through chips inputs and outputs, the special TAM is
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Harikrishna Parmar and Dr.Usha Mehta

needed to test the core at the system level [1] [2]. TAM establishes communication
between the cores and chip input-output and does the job of transferring test data from
chip input-output to the core and vice versa. Test wrapper establishes an interface
between the core and its environment. TAM is essential for modular testing, because
it instantly influences testing time of SoC. The present IEEE 1500 standard describes
wrapper design only and leaves optimization of TAM to the system designer.
Therefore, optimization of TAM is a functional area of research.
A number of TAM architectures, which are working on different heuristics and
algorithm, are proposed in [3]-[18]. The main motto of all these TAM architecture is
to reduce testing time of SoC.
Here, in this paper, an improved TAM is presented for the test bus architecture to
get optimal testing time of SoC.
The whole paper is organized as follows. Section II discusses the prior work on
TAM in 2D SoC. The Problem statement is described in section III. Mathemtical
model referred to establish the problem statement is shown in section IV, whereas
section V discusses the experimental result analysis. Finally, section VI draws the
conclusion.

2. PRIOR WORK
Mainly there are three kinds of test access architectures [3]. 1. Multiplexing, 2.
Distribution and 3. Daisychain architecture [4]-[7]. By using these architectures, a test
bus and TestRail architecture were proposed in [8] and [9] respectively.
A novel approach to reduce the test time of SoC is proposed in [10], which is
based on genetic local search algorithm. The proposed method resolves the problem
of TAM under the restriction such as core cluster and core placement cluster. The
method allows the system designer to improve TAM and helps to make appropriate
choices.
Another approach to reduce test time based on the bandwidth matching concept is
shown in [11], which emphasizes the multi-frequency TAM design. Using the method
of serialization and deserialization, a high bandwidth source and sink are connected to
the low bandwidth source and sink until bandwidth matches. In the second approach,
the problem with the post-silicon validation method, which has limited debug access
bandwidth to access internal signals, is described in [12].
The TAM based on flexible width architecture is shown in [13]. In this method,
first lower bound of test time is set which does not depend on TAM structure and then
the test bus assignment is done in such a way that, it achieves that lower bound.
A TAM for the multiple identical cores is shown in [14], which utilize the uniform
nature of the core and applies test simultaneously, which helps to minimize test time
for core under test. In an another approach, testing of multiple identical core is done
in such a way that, instead of taking typical test response data from the core, it takes a
majority based value. The TAM architecture introduced in this paper is based on-chip
comparator and majority analyzer [15] [16]. Reconfiguration of the multiple scan
chain to minimize test application time for SoC is presented in [17].
Here, the whole paper is designed for the optimization of TAM for the test bus
architecture. The architecture and results discussed in [18] and [19] is taken as a
reference. The algorithm described to optimize Wrapper and TAM in test bus
architecture is again developed and improved to get a further reduction in the test
application time.

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An Efficient Algorithm For Wrapper and Tam Co-Optimization To Reduce Test Application
Time In Core Based SOC

3. PROBLEM STATEMENT
For the given NC number of cores for the SoC, including ni number of inputs, mi
number of outputs, TAM width W, SC number of scan chain and length of scan chain
lik for each core and Pi number of test patterns, determine (i) The improved width of
TAM bus (ii) ideal partition for TAM bus (iii) The assignment of cores to the
partitioned TAM bus and (iv) The test schedule for the entire SoC, such that overall
test application time is minimized.

4. MATHEMATICAL MODEL
Initialization
Let the total number of cores are NC
Total number of input for a particular core is - n
Total number of output for a particular core is m
Number of test pattern given in a particular core is - P
TAM width allocated is W
Number of partition taken for TAM width W is B
So, Width distribution is taken as if partition factor is two
W1(i) = i
W2(i) = W- i

Where i varies from 1 to W/2

Here, a new variable is defined as
(i) = max(n(i),m(i))
Where i varies from 1 to NC

Balance Wrapper Scan Chin

Lets number of scan chain inside a particular core is Sc.
Length of each scan chain is given as l1,l2..lsc
Number of scan chain of length l1,l2lsc is Z1,Z2.Zsc
Now divide number of scan chain Z1,Z2..Zn by width W and find quotient an
remainder.
Q1=Z1/W

R1 = Z1%W

Q2=Z2/W

R2= Z1%W

Qn=Zn/W

Rn=Zn%W

Here, Quotient indicates that these many scan chain can be equally distributed on
TAM width W.
Remainder indicates that these many scan chains are needed to be distributed
separately.
Now take the sum of the remainder
Rsum=

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Harikrishna Parmar and Dr.Usha Mehta

If Rsum<W, Then
Sum2(i)=

+ R(i)

Now, distribute and add number of I/O to sum2(i) such that the balance wrapper
scan chain is formed.
Sum3(i) =

+ m/W

Now find longest and shortest scan chain length

Simax = max(Sum3(i))
Where i varies from 1 to Sc
Simin = min(Sum3(i))
Where i varies from 1 to Sc
If Rsum>W, Then

Now, distribute and add remainders and number of Inputs to sum2(i) such that the
balance wrapper scan chain is generated.
Sum3(i) =

+ m/W + R(i)

Now find longest and shortest scan chain length

Simax = max(Sum3(i))
Where i varies from 1 to Sc
Simin = min(Sum3(i))
Where i varies from 1 to Sc
Simax and Simin is the balance input wrapper scan chain
Repeat this procedure for Balance output wrapper scan chain to find out So max and
Somin

Test Time Calculation

Calculate test application time of each core for width W1 as per the equation given
below and store it in array A
A(i) = (1+max(Simax,Somax))*P + min(Simin,Somin)

Where i varies from 1 to NC

Calculate test application time of each core for width W1 as per the equation given
below and store it in array B
B(i) = (1+max(Simax,Somax))*P + min(Simin,Somin)

Where i varies from 1 to NC

Test Scheduling
Sort array A and array B in Descending order.
Calculate cumulative test time of all cores from array A
P1 =

Calculate cumulative test time of all cores from array

P2 =

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An Efficient Algorithm For Wrapper and Tam Co-Optimization To Reduce Test Application
Time In Core Based SOC
P=min(P1,P2)

Take P as a upper bound for further procedure

Now, add array A and B
C(i)=

If number of cores is greater than 10 then distribute cores into number of

segments. The first segment must contain 10 cores. The succeeding each segment may
contain up to 10 cores.
Here, the model is shown for 3 segments with assumption that there are 30 cores
in a SoC.
Store the test time for the first 10 core in an array X
X1(k)=C(i)
Where i and k varies from 1 to 10
X2(k)=C(i)
Where i varies from 11 to 20 and k varies from 1to 10
X3(k)=C(i)
Where i varies from 21 to 30 and k varies from 1to 10

Test scheduling for segment 1:

Upper bound for test time is PH = P
Lower bound of the test time is given as
PL =

Find the sum of the test time of the cores in array X1 for a given limit of upper
and lower bound and store it in array D1.
Find the sum of the test time of the cores in array X1a for a given limit of upper
and lower bound and store it in array D2.
Find the sum of the test time of the cores in array X1b for a given limit of upper
and lower bound and store it in array D3.
Find the length of D1.
L1=length(D1)
Find maximum from array D1, D2 and D3
EH1 = max(D1)
EH2 = max(D2)
EH3 = max(D3)

Test scheduling for segment 2:

Upper bound = EH1
Lower bound = EL =
Where i varies from 21to 30
Find the sum of the test time of the cores in array X2 for a given limit of upper
and lower bound and store it in array F1.
Find the sum of the test time of the cores in array X2a for a given limit of upper
and lower bound and store it in array F2.

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Harikrishna Parmar and Dr.Usha Mehta

Find the sum of the test time of the cores in array X2b for a given limit of upper
and lower bound and store it in array F3.
Find the length of F1.
L1=length(F1)

Test scheduling for segment 3:

Initialize a variable k1=1
Upper bound = F1(i)
Where i varies from 1to L2
Lower bound = EL = C(Nc)
Find the sum of the test time of the cores in array X3 for a given limit of upper
and lower bound and store it in array G1(k1) and update array for every iteration from
i =1 to L2. Also update k1.
Find the sum of the test time of the cores in array X3a for a given limit of upper
and lower bound and store it in array G2(k1) and update array for every iteration from
i =1 toL2. Also update k1.
Find the sum of the test time of the cores in array X3b for a given limit of upper
and lower bound and store it in array G3(k1) and update array for every iteration from
i =1 toL2. Also update k1. Find the length of G1 and update the values of last array.
L3=length(G1)
H1(j)=
H2(j)=
H3(j)=
Update j and H1,H2,H3 for every iteration.
Now, take P, EH2 and EH3 from segment 1
J1(i) =
)
J2(i)=PFind maximum from two array J1 and J2
J(i)= max(J1(i),J2(i))
Where i varies from 1 to L3
Find Minimum value fro array J
Q=min(J(i))
Where i varies from 1 to L3
Find Minimum value fro array J
Q=min(J(i))
Where i varies from 1 to L3
Q is the final answer

5. EXPERIMENTAL RESULT ANALYSIS

Here SoC d695 and P93791 is taken as a running example throughout this paper to
understand the fundamental of test optimization methodology.
Here the experimental results are shown in table I, II and III when TAM bus width
is partitioned by 2. Also, the proposed method is compared with the reference

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An Efficient Algorithm For Wrapper and Tam Co-Optimization To Reduce Test Application
Time In Core Based SOC

approach [18] and [19] which shows the optimality of the proposed method.
Simulation results achieved in this paper are done in MATLAB.

6. CONCLUSION
In this paper, an improved algorithm for the test bus architecture is presented and the
simulation is done on SoC d695 and P93791. Through extensive simulation on given
SoC, it is observed that with the proposed algorithm, the testing time is reduced
significantly as compared to the approach given in the reference. It has also been
noticed that the achieved TAM bus width distribution and core assignment is an
optimum value for the testing time earned with the proposed algorithm.
Table I Simulation results for SoC D695
Total TAM
Width

Optimal Width
Distribution

From ref paper

[18]
(No. of clocks)

From proposed
algo
(No. of clocks)

Difference
(No. of clocks)

16
20
24
28
32
36
40
44
48
52
56
60
64

(7,9)
(4,16)
(5,19)
(8,20)
(12,20)
(16,20)
(8,32)
(9,35)
(10,38)
(18,34)
(20,36)
(20,40)
(20,44)

45055
34444
29501
26964
25442
25312
21359
20883
19938
19087
18434
18205
18205

44116
34437
29240
26828
24779
23193
21314
20232
19707
18783
18130
18019
17946

939
7
261
136
663
2119
45
651
231
304
304
186
259

Table II Simulation results for SoC P93791 (Comparision with ref paper [18])
Total TAM
Width

Optimal Width
Distribution

From ref
paper[18]
(No. of clocks)

From proposed
algo
(No. of clocks)

Difference
(No. of clocks)

16
20
24
28
32
36
40
44
48
52
56
60
64

(8,8)
(8,12)
(12,12)
(5,23)
(9,23)
(12,24)
(16,24)
(17,27)
(23,25)
(6,46)
(9,47)
(13,47)
(16,48)

1806550
1453170
1217630
1031200
899807
820232
751345
711256
634488
600218
533752
505885
475598

1683418
1356828
962058
868112
867746
781852
707549
694132
589031
534109
505877
483857
464905

123132
96342
255572
163088
32061
38380
43796
17124
45457
66109
27875
22028
10693

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Harikrishna Parmar and Dr.Usha Mehta

Table III Simulation results for SoC P93791 (Comparision with ref paper [19])
Total TAM
Width

Optimal Width
Distribution

16
24
32
40
48
56
64

(8,8)
(12,12)
(9,23)
(16,24)
(23,25)
(9,47)
(16,48)

From ref
paper[19]
(No. of clocks)
1854566
1272220
940318
765715
640488
551849
473726

From proposed
algo
(No. of clocks)
1683418
1134381
868112
706617
587775
494999
449967

Difference
(No. of clocks)
171148
137839
72206
59098
52713
56850
23759

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