ISDRS 2007, December 12-14, 2007, College Park, MD, USA

Device and Circuit Modeling using Novel 3-State Quantum Dot Gate FETs
F. C. Jain, E. Heller*, S. Karmakar, and J. Chandy
Department of Electrical and Computer Engineering, University of Connecticut,
Storrs, CT 06269; * RSoft Design Group, Ossinings, NY 10562
Abstract: This paper presents simulation of three-state behavior recently reported in quantum dot
gate field-effect transistor (FET) structures. The model self-consistently solves Schrdinger and
Poisson equations with built-in transfer of carriers from the inversion channel to two layers of
cladded SiOx-Si quantum dots (QDs) forming the gate, predicting the intermediate state in the
transfer Id-Vg characteristic. Circuit model and simulations for a 3-bit ADC are also presented.
I. Introduction: Quantum dot (QD) gate memories have been fabricated in a number of ways
since the first reporting by Tiwari et al. [1]. During the fabrication of self-assembled quantum dot
gate nonvolatile memories, it was observed that certain FET structures exhibit a novel
intermediate state in the transfer (drain current Id-gate voltage Vg) as well as output (Id-Vd)
characteristics, not observed in conventional FETs. That is, the transfer characteristics show
three stable states ("0", "1" and "i"), where the low-current saturation state "i" is manifested over
a range of gate voltages which can be utilized for various circuit applications. These novel
bistable characteristics provide new versatility in designing multiple-valued logic [2] CMOS
circuits with significantly reduced FET counts as well as advanced analog circuit building blocks
such as comparators for designing analog-to-digital converters (ADCs).
II. FET structure with two layers of SiOx-cladded Si quantum dots: Fig. 1(a) shows a typical
QD FET structure consisting of two layers of self-assembled SiOx-Si quantum dots between the
source and drain regions above the p-doped channel hosting the inversion electron channel [3].
Figure 1(b) shows the three energy band diagrams at different gate voltages and a plot of
inversion layer carrier concentration as a function of gate voltage. Note that the carriers are first
transferred to the second quantum dot layer near the gate (see Fig. 1b top right), and as the gate
voltage is further increased, the charge is located in the first quantum dot layer near the inversion
channel (see Fig. 1b bottom left). The tunneling transition rate from the channel to the

quantum dot layers is expressed by Hamiltonian in Eq.1 following Chuang et al. [4].
Pwd =

4
h

d Ht w

( f w f d ) ( Ed Ew )

(1)

w, d

Two layers of SiOx-coated Si quantum dots

Gate
Source Contact

Drain Contact

Field
Oxide

n+ Source

n+ Drain

L
p-Si

Gate Insultaor

(b)

ID

ON "High-Current
Saturation"

124

Drain
Current

Intermediate state "i"

(Low-Current Saturation)

0.84
-10

OFF
1.2 Volts/Div

VG

Gate Voltage

(a)

Fig. 1. (a) Cross-sectional schematic of a SiOx-Si quantum dot gate FET with transfer characteristics
shown in inset. (b) Simulated energy band diagrams and transfer (Id-Vg) characteristic.

ISDRS 2007 http://www.ece.umd.edu/ISDRS

978-1-4244-1892-3/07/$25.00 2007 IEEE

ISDRS 2007, December 12-14, 2007, College Park, MD, USA

In quantum dot gate FETs, the gate insulator charge is composed of discrete values as
expressed in Eq. 2 (the conventional interface charge Qox at SiOx-Si interface is not shown
as it does not relate to bistability). Thus, the threshold voltage increases in the gate voltage
range exhibiting the intermediate state i, keeping the drain current constant.
xg

x ( x )
q
dx =
xg
Cox

xQD1n1 N QD1
x nN
+ QD 2 2 QD 2 (2)

xg
xg

0
III. Circuit Model and 3-Bit ADC Simulation:
VFB = VTH

q
=
Cox

We have developed an empirical model for the QDFET that accounts for the intermediate
state i in the range of gate voltages (Vg1 and Vg2). The effective threshold voltage is
divided into three ranges corresponding to the three regions of the transfer characteristics
(see Fig. 1(a) bottom): region 1, intermediate state i, and the regular saturation part.
Using this model we have simulated a 3-bit ADC circuit in which the comparators are
comprised of a 3-state QDFET, an adjustable threshold QD gate FET, and a conventional
p-MOS. The ADC schematic is shown in Fig. 2(a) and the CADENCE simulation results
are shown in Fig. 2(b). The QDFET parameters are: L=600 nm and W=15 m with a
W/L ratio ~ 24. The crossover voltage range of the comparator can be increased by
adjusting the threshold voltage of the adjustable threshold QDFET.
A 3-bit flash ADC with Tri-state CMOS inverters replacing
Comparators and Reference resistors

(a)

(b)

CLK

Vin

QD CMOS Inverter
Vin

Over
Range

20
QDM
VTH-1

WL-1

VDD
N-MOS

VTH-1

21
QDM
VTH-2

P-MOS

Vout1

N digital
outputs
(1, i)
(1, i,
0)

WL-2

N-MOS

P-MOS VDD

NAND
Gate 1

(2N-1)
to N
encoder

Vout2

2n
QDM
VTH-3

WL-3

VDD
N-MOS
Vout3

P-MOS
(to NAND
gate)

Priortity Encoder (PE)

Fig. 2. Cadence simulation of 3-bit ADC: (a) Circuit block diagram with comparator comprised of
3-state QDFET and adjustable threshold QD FET, and a p-MOS ; and (b). ADC output waveform.
This work is supported by ONR Contracts N00014-02-1-0883 and N00014-06-1-0016, and NSFGrant ECS 0622068. Discussions with Dr. D. Purdy (ONR) and Dr. R. Khosla (NSF), and
technical assistance in processing by Dr. R. Velampati and Dr. A. Rodriguez are gratefully
acknowledged.
[1] S. Tiwari, F. Rana, K. Chan, H, Hanafi, W. Chan and D. Buchanan, Volatile and non-volatile
memories in silicon with nano-crystal storage, IEDM, pp. 521-525, Dec. 1995.
[2] T. Hanyu, M. Kameyama, A 200 MHz pipelined multiplier using 1.5 V-supply multiple valued MOS
current-mode circuits with dual-rail source-coupled logic, IEEE Journal of Solid-State Circuits vol. 30,
no. 11, (1995).
[3] F. Jain, R. Velampati, A. Rodriguez, E. Heller, E-S. Hasaneen, J. Chandy, B. I. Miller, F.
Papadimitrakopoulos, Quantum dot gate 3-state field-effect transistors and nonvolatile memory devices for
millimeter wave circuits, Int. J. Millimeter Waves and Infrared (submitted).
[4] S. Chuang, N. Holonyak, Efficient quantum well to quantum dot tunneling: Analytical
solutions, Appl. Phys. Lett., 2002; 80: 1270-1272.

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