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# LINEAR INTEGRATED CIRCUITS (VTU) - 10EC46

UNIT - 6
Non-linear circuit applications: crossing detectors, inverting Schmitt trigger circuits, Monostable
& Astable multivibrator, Active Filters-First and second order Low pass & High pass filters.
6 Hours
TEXT BOOKS:
1. Operational Amplifiers and Linear ICs, David A. Bell, 2 nd edition, PHI/Pearson, 2004.
2. Linear Integrated Circuits, D. Roy Choudhury and Shail B. Jain, 2 nd edition, Reprint 2006,
New Age International.
Special Thanks To:
Faculty (Chronological): Rajappa H S (Dept ECE, GMIT)
BY:
RAGHUDATHESH G P
Asst Prof
ECE Dept, GMIT
Davangere 577004
Cell: +917411459249
Mail: datheshraghubooks@gmail.com
Website: raghudathesh.weebly.com

Quotes:

If you really think your teacher is tough, wait until you get a boss. He does not have tenure.
Success is never final. Failure is never fatal. Its courage that counts.

## A happy family is but an earlier heaven.

Happiness is nothing more than good health and a bad memory.

Introduction:

Op-amps are widely used in circuits in which the output is switched between the +ve and
ve saturation levels as Op-amp in open loop configuration produces the output voltage
which is very either at its +ve and ve saturation level since the open loop gain of op-amp
is very large.

## These output saturation voltages are given as below

-------- (1)
--------- (2)

For very small change in input voltage, the op-amp output switches from +Vsat to Vsat
and vice-versa.

The above property is not suitable for linear applications, is very much suitable for non
linear applications of op-amp like comparators, crossing detectors, Schmitt triggers and
so on.

In all the above applications a positive feedback is employed and most of the time no
frequency compensation is needed as in non-linear application the feedback is usually
provided is a DC quantity.

## Zero Crossing Detectors:

Definition: Zero Crossing Detector (ZCD) is a voltage comparator that switches the
output between +Vsat and Vsat (Vsat: Saturation voltage almost equal to 14V) when the
input crosses zero reference voltage.

## Comparator Definition: Comparators are basic operational amplifier circuits that

compare two voltages simultaneously and switch the output according to the comparison.

## We can say zero crossing detection circuit is a comparator example.

There are 3 types of zero crossing detectors based on the input applied they are:
1. Non-inverting zero crossing detector
2. Inverting zero crossing detector
3. Capacitor coupled crossing detector

## An op-amp connected to function as a non-inverting zero crossing detectors is shown in

figure 6.1 (a) as below

## Figure 6.1(a): Non-Inverting Zero Crossing Detector

In the above circuit inverting input terminal is grounded and the input voltage is directly
connected to the non-inverting terminal.

When the input goes above ground level say by about 300 V, the output immediately
switches to the op-amp positive saturation voltage.

When the input is below ground level, the output immediately switches to the op-amp
negative saturation voltage.
Each time the input voltage crosses the zero level, the output switches from one
saturation level to the other.

The output waveforms that result for various inputs to a zero-crossing detector are
illustrated in figure. 6.1(b).

## Regardless of the type of input waveform, the output is a rectangular waveform.

There is no design calculations involved in using an op-amp as a crossing detector.
However, the op-amp input voltage range must be large enough to handle the signal and
the slew rate must be enough to avoid unacceptable output distortion.

6.2 (a) as below

## Figure 6.2(a): Inverting Zero Crossing Detector

In the above circuit non-inverting input terminal is grounded and the input voltage is
directly connected to the inverting terminal.

When the input goes above ground level say by about 300 V, the output immediately
switches to the op-amp negative saturation voltage.

When the input is below ground level, the output immediately switches to the op-amp
positive saturation voltage.

Each time the input voltage crosses the zero level, the output switches from one
saturation level to the other.

The output waveforms that result for various inputs to a zero-crossing detector are
illustrated in figure. 6.2(b).

## Regardless of the type of input waveform, the output is a rectangular waveform.

When the input voltage crosses the zero line going in a positive direction, the output goes
negative, and vice versa. Hence, this circuit is called as an inverting zero-crossing
detector, sometimes termed an inverter.

## Voltage Level Detector:

In the above case Instead of being biased to ground level, the non-inverting input
terminal of the op-amp could be biased to a positive or negative dc voltage level as
shown in the figure 6.3 for inverting zero crossing detector as below

## Figure 6.3: inverting Voltage Level Detector

Thus, the circuit output would change when the input arrives at the bias voltage level.
Hence this circuit is known as voltage level detector.

## Figure 6.4: Capacitor-Coupled Crossing Detector

In the above circuit the op-amp non-inverting input terminal connected to ground via
resistor R1 to provide a DC bias current path to the op-amp.

The inverting input terminal is biased to a DC voltage level slightly above ground using
potential divider. This is required to ensure that the output is saturated in a negative
direction when no input signal is present.

The output switches to +Vo(sat) when the capacitor-coupled signal drives the non-inverting
input terminal above VB, and falls back to -Vo(sat) when the input drops below VB.

Design:
R1 = R(max) should be calculated using the specified I B(max) for that particular opamp. The general expression is given as,

The potential divider current (I2) should be much larger than the op-amp
maximum input bias current. This is to ensure that I B, and any bias current
variation, has a negligible effect upon the bias voltage level.
Usually I2 is made 100 or more times IB. Thus,

## The determination of capacitance C1 depends upon the type of input waveform

involved.
With a sinusoidal input, phase shift error is normally to be avoided. So, XC1
should be much smaller than R1 at the minimum signal frequency, assuming that
the input impedance of the op-amp is much larger than R1, XC1 is given as

## When a square wave is applied as an input to a capacitor-coupled crossing

detector, the waveform at the op-amp input terminal can develop considerable tilt,
as shown in figure 6.4.
As long as the op-amp output remains saturated at the required level, the tilt at the
input is not important.

## A suitable capacitance for C1, can be determined by first estimating an acceptable

tilt voltage V and noting the time duration t of the input. Then, the current is
calculated as

## It is also called as regenerative comparator.

Circuit Operation:
An operational amplifier connected to function as a Schmitt trigger circuit is as
shown in figure 6.5(a) below

## Figure 6.5(a): Op-amp Inverting Schmitt Trigger Circuit

In the above circuit the input is applied to the inverting input terminal and the
feedback from the output is connected to non-inverting input terminal.
The voltage at non-inverting input terminal is given as

## When the output voltage is saturated in a positive direction at +V o(sat), VR2 is a

positive quantity then the voltage at the non-inverting terminal is a positive
quantity i.e. +VR2 as

## As Vo is saturated in a positive direction thus,

The output will switch from the positive saturation level to the negative saturation
voltage only when the inverting input terminal is raised above the voltage at noninverting input terminal (VR2). When the input level is raised just slightly (V)
above VR2, the op-amp output begins to move in a negative direction, causing VR2
to decrease, thus making the inverting input terminal more positive with respect to
the non-inverting input terminal.
The differential input voltage causing the output to switch from positive
saturation to negative saturation is increased by the movement of the output in the
negative direction. This is positive feedback and it causes the output to move
rapidly from one saturation level to the other.

## As Vo is saturated in a negative direction thus,

In the above figure, the voltage at point +VR2 on the waveform at which output
shifts from +Vsat to Vsat is called Upper Triggering Point (UTP).
In the above figure, the voltage at point -VR2 on the waveform at which output
shifts from -Vsat to +Vsat is called Lower Triggering Point (LTP).
A Schmitt trigger circuit can be designed for virtually any desired trigger point
voltages.
The voltage waveforms in figure 6.5(b) below show the Schmitt trigger circuit
response to various inputs.

## Transfer or Input/output Characteristics:

Figure 6.6 shows the graph of output voltage against input voltage, and this is
called as transfer characteristics of Schmitt trigger.

## Figure 6.6: Transfer or Input/output Characteristics or Hysteresis curve of Schmitt Trigger

The output voltage remains in a given state until the input voltage exceeds the
threshold voltage either in positive or negative direction.

Above graph indicates that once the output changes its state, it remains there
indefinitely until the input voltage crosses any of the threshold voltage levels.
This is called as Hysteresis of Schmitt trigger. Hysteresis is also known as Dead

## Description of Hysteresis Curve:

Starting with, say let the output be at +Vo(Sat) and the input at zero, when Vi is
raised to the UTP, the output switches from +Vo(sat) to -Vo(sat), (point a to point b).
Any further increase in Vi above the UTP maintains the output at -Vo(sat), (point b
to point c).
Now say, the input is being reduced from UTP to the LTP (point b to point d), the
output remains at -Vo(sat). When Vi equals the LTP, the output rapidly switches
from -Vo(sat) to +Vo(sat) (point d to point e). Now, any further decrease in V i below
the LTP maintains the output voltage at +Vo(sat).
The voltage difference between the upper and lower trigger points is referred to as
Hysteresis.
Difference between the Upper Trigger Points (UTP) and Lower Trigger Points
(LTP) is referred to as width of Hysteresis and is given as

Summarizing the above all the related equation are given below

If input applied is sinusoidal, the input and output waveforms for inverting Schmitt
trigger is as below

## Figure 6.7: Input and Output Waveform

Design Steps:
To design an op-amp Schmitt trigger circuit using a bipolar op-amp, the current
through resistors R1 and R2 is first selected to be much larger than the op-amp
bias current.
R2 is then calculated as the trigger point voltage divided by I 2.

And R1 is

When using a BIFET op-amp, it is best to follow the usual procedure of selecting the
largest of the two resistors as 1 M, and then calculate the resistance of other one.

## Adjusting the Trigger Points (UTP & LTP):

Inverting Schmitt Trigger With +ve UTP & LTP = 0:
This can easily be achieved by including a diode in series with R1, as shown in figure 6.8
below

Figure 6.8: Inverting Schmitt trigger circuits with +VE UTP & LTP=0

When the output is positive, D1 is forward-biased, and the UTP is the voltage drop across
R2.

When the output goes negative, D1 is reverse-biased, only the op-amp input bias current
flows in R2, and the op-amp non-inverting input terminal is held close to ground level
thus, LTP = 0.

The output will go positive once again when the input voltage is reduced below ground
level. Thus, the lower trigger point is effectively zero volts.

Diode D1 must be selected to have a maximum reverse voltage greater than the circuit
supply voltage. Its maximum reverse recovery time (t rr) should be much smaller than the
minimum pulse width of the input signal. Typically,

Design:

As,

Here,

then,

## Inverting Schmitt Trigger With Different UTP & LTP:

This can easily be achieved by using two diodes D1 and D2 and three resistors R1, R2 and
R3 as shown in figure 6.9 below

Figure 6.8: Inverting Schmitt trigger circuits with Different UTP & LTP

When the output is positive, D1 is forward biased and D2 is reversed. The upper trigger
point is

When the output is negative, D2 forward-biased and D1 is reversed, giving the lower
trigger point as

## Here, VF = forward voltage drop of D1

Different resistance values for R1 and R3 give different trigger point voltages.

Design:
Here UTP and LTP will be given. Hence
Voltage drop across resistor R2 is given as

Also,

## In the above equation, we solve for Resistor R1 to determine its value.

Since LTP is Known, Resistor R3 is given as,

## In the above equation, we solve for Resistor R3 to determine its value.

Astable Multivibrator:

## The circuit has no inputs.

The output continuously switches between high and low output voltage levels.

Circuit Operation:
An astable multivibrator is a circuit that is continuously switching its output
voltage between high and low levels. It has no stable state.
An astable multivibrator using an operational amplifier is shown in figure 6.9

## The op-amp together with resistors R2 and R3 constitute an inverting Schmitt

trigger circuit.
The input voltage to the Schmitt circuit is the voltage across capacitor C1, which
is charged from the op-amp output via resistor R1.
Initially let capacitor voltage Vc = 0 and output voltage is at the positive
saturation level Vo = + Vsat then current flows into the capacitor, capacitor charges
exponentially with time constant equal to R1C1 charging it positive at the top
(+Vsat), as illustrated, until V C, reaches the Upper Trigger Point (UTP) of the
Schmitt circuit and is given as,

At this point (UTP) the output then rapidly switches to the op-amp negative
saturation level (-Vsat). Now current flows from the capacitor, removing its
positive charge and recharging it with the opposite polarity. This continues until
VC1 arrives at the Schmitt Lower Trigger Point and is given as,

This procedure continues and producing a symmetrical Square wave. The circuit
is a square wave generator with an output that swings between the op-amp
positive and negative saturation levels. The frequency of the output depends on
the capacitance of C1 and the resistance of R1.

Design:
The Schmitt portion of the circuit can be designed in the usual way for any
convenient trigger point levels.
The minimum current through R1 is selected to be much larger than the op-amp
input bias current and is given as

R1 is calculated as
------- (1)
Once R1 is determined, C1 can be calculated from the capacitor charging equation
and the desired half-cycle time of the output.
If the Schmitt UTP and LTP are selected to be much smaller than the op-amp
output voltage, the voltage drop across R1 will not change very much.
Consequently, the capacitor charging current (I 1) can be treated as constant and
the simple constant current capacitor equation can be used to determine the
capacitance of C1 as

Here,
------ (2)
If a BIFET op-amp is used, the capacitance of C 1 should be first selected to be
much larger than stray capacitance. Then, I 1 is determined from equation (2) and
R1 is calculated using equation (1).

Monostable Multivibrator:

## A monostable multivibrator has one stable output state.

Its normal output voltage may be high or low, and it stays in the normal state until
triggered.

When triggered, the output switches to the opposite state for a time dependent on the
circuit components.

below

## figure 6.10(a): Monostable Multivibrator Circuit & Waveform

The DC conditions of the circuit are that the op-amp inverting input terminal is grounded
via resistor R3, and the noninverting input terminal is biased positively by resistors R1
and R2.
The op-amp output is normally at its positive saturation level, and capacitor C 2 is charged
with the polarity shown in figure 6.10(a).
If C2 was not present, the circuit would be similar to a capacitor-coupled voltage level
detector that switches its output from + Vo(sat) to - Vo(sat) when V1 exceeds VR2.

## An input pulse (Vi) applied to C1 is differentiated by R3 and C1 to produce positive and

negative spikes (VR3) at the op-amp inverting input terminal, as illustrated.

The negative spike is clipped at - 0.7 V by diode D1, so that it has no effect on the circuit.
The positive spike lifts the inverting input terminal above the bias level at the
noninverting input, and thus causes the op-amp output to switch to the negative saturation
level.
The spike has relatively short time duration, so the inverting input terminal quickly
returns to the zero voltage level.

when the output goes to -Vo(sat), the charge on C2 drives the noninverting input voltage
(V+) down to,

This holds the noninverting input terminal below ground level after the input triggering
spike has disappeared, thus keeping the output at the negative saturation level.

With the output at - Vo(sat), C1 discharges via R1 and R2, thus gradually raising the
noninverting input terminal toward ground level.

When the noninverting terminal goes slightly above ground, the op-amp output
immediately switches back to the positive saturation level once again, and the circuit is
returned to its original state.

The circuit produces a negative going output pulse each time it is triggered. The pulse
width (PW) of the output depends on the capacitance of C2, the bias voltage VR2, and the
resistance of R1 and R2.

Figure 6.10(b) shows an adjustable resistor R4 included in the circuit. The total resistance
in series with the capacitor is now (R4 + R1 || R2).

## Usually, R4 is selected to be much larger than RI || R2, so that the capacitor

charge/discharge resistance is effectively R4. Adjusting R4 alters the capacitor
charge/discharge time, thus con-trolling the output pulse width.

Design:
Current I2 is considered very much larger than IB(max)

The voltage VR2 is chosen to be in the range of 0.5 to 1 Volts, thus, R2 is given as

## To design a differentiator circuit, the time constant R3C1 is assumed to be 10% of

input pulse width t to generate suitable spikes from the pulse

C1 is first selected much larger than stray capacitor then R3 is calculated as,

## The capacitor C2 is given by

Here,
PW Desired output pulse width
E Capacitor charging voltage and is given as below

## Eo Initial Capacitor voltage before triggering

The final capacitor voltage e c is the voltage at which the op-amp output switches
back from -Vo(sat) to +Vo(sat). This is the voltage across C2 when the
noninverting input terminal is at ground level and the output is still at -V0(sat)
Therefore

Filters:

Definition: Filters are circuits that pass only a certain range/Band of signal frequencies
while attenuating all the signals outside that band.
It is frequency selective circuit.

## Based on the frequency these filters pass they are classified as

1. low-pass
2. high-pass
3. band-pass
4. band-stop

Based on the types of elements these filters use they are classified as
1. Passive Filters: These filters/networks/circuits use only passive elements such as
resistors, inductors and capacitors.

2. Active Filters:
These filters/networks/circuits use the active elements such as op-amps,
transistors along with the resistors, inductors and capacitors.
Modern active filters do not use inductors as the inductors arc bulky,
heavy and nonlinear.

Based on the rate at which the output falls off at the edge of the frequency range they are
classified as
1. First-order filters: These have a fall-off rate of 20 dB per decade.
2. Second-order filters: These have a fall-off rate of 40 dB per decade.
3. Third-order filters: These have a fall-off rate of 60 dB per decade.

Analysis of filter circuits can be extremely complex, but the behavior of the commonly
used filters can be readily understood and many simple design technique are available.

## Frequency Response Characteristics of Filters:

1. Low-Pass Filter:

The figure 6.11 below shows the frequency response of low pass filter.

## figure 6.11: Low-pass Filter Response Ideal & Practical

A low pass filter has a constant gain from 0 Hz to a high cut-off frequency, fH. Hence, the
bandwidth of this filter is also fH.

The circuit allows the range of frequencies from 0 to fH. This range is known as the pass
band.

The range of frequencies beyond fH is completely attenuated and hence called as stop
band. Practically, the gain of the filter decreases as the frequency increases and at f = fH,
the gain is down by 3 dB and after fH, it decreases at a higher rate. After the end of
transition band, the gain becomes zero.

Using proper design techniques, precision component values and high speed op-amps, the
practical response can be obtained very close to the ideal response.

2. High-Pass Filter:

The figure 6.12 below shows the frequency response of high pass filter.

## For a high pass filter, fL is the lower cut-off frequency.

The range of frequency 0 < f < fL is the stop band where f is the operating frequency.

## While the range of frequency f > fL is the pass-band.

The transition band is practically not shown in the characteristics as it is very small.
Hence, practically, also range upto fL is called as stop band and f > fL as pass band. The
range upto fL is completely attenuated by high pass filter.

1. All the elements along with op-amp can be used in the integrated form. Hence there is
reduction is site and weight.
2. In large quantities, the cost of the integrated circuit can be much lower than its equivalent
passive network.
3. Due to availability of modern ICs, varieties of cheaper op-amps are available.
4. The op-amp gain can be easily controlled in the closed loop fashion. Hence active filter
input signals is not attenuated.
5. Due to flexibility in gain and frequency adjustments, the active filters can be easily tuned.
6. The op-amp has high input impedance and low output impedance. Hence the active filters
7. The inductors are absent in the active filters. Hence the modern active filters are more
economical.

8. Active filters can be realized under number of class of functions such as Butterworth,
Thomson, Chebyshev, Cauer etc.
9. The response is improved as compared to passive filters due to ready availability of high
quality components.
10. The design procedure is simpler than that for the passive filters.
11. Active filters can provide voltage gains. In contrast the passive filters often show a
significant voltage loss.

## First-Order Low-Pass Active Filter:

A passive low-pass filter circuit consisting of a resistor and a capacitor is shown a figure
6.13(a) as below

## The filter load (ZL) is connected in parallel with capacitor C1.

Unless ZL is much larger than XC1 the load is likely to affect the filter performance.

Connecting a voltage follower to the circuit as shown in figure 6.13(b) eliminates the
load problem and converts the circuit into an active filter. This circuit is also known as a
first-order low-pass filter.

## Taking only the magnitude we get,

--------- (1)

The active filter frequency response shown in figure 6.13 (c) is exactly the same as that

## figure 6.13(c): Frequency response of Low Pass Filter

Scenarios:
Case 1:
At low frequencies XC1 >> R1. Hence, equation (1) gives the gain as
approximately 1.
Case 2:
At higher frequencies, as XC1 R1, the gain decreases.
The frequency at which the output voltage is down by 3 dB from its passfrequency level is defined as the cutoff frequency (fc) of the filter. Here, fc
is the frequency at which XC1 equals R1. This can be proved by
substituting XC1 = R1 into equation 1.

Case 3:
At frequencies higher than fc the gain of the circuit falls off at a rate of 20
dB per decade, a fall of 20 dB each time the frequency is increased by a
factor of 10. This rate can also be expressed as -6 dB per octave, which
means a fall of 6 dB each time the frequency is doubled.

Design:
R1 = R(max) should be calculated using the specified I B(max) for that particular opamp and it is also desirable to keep R1 as large as possible for maximum filter
input impedance. The general expression is given as,

## Capacitor C1 is determined as,

The capacitance of C1 must be much larger than stray capacitance. This, points to the
usual approach of selecting C1 first when using BIFET op-amps.

## Second-Order Low-Pass Filter:

Figure 6.14(a) shows a filter circuit, known as a second-order low pass filter, which has a
frequency response that falls off at the rate of 40 dB per decade above the upper cutoff
frequency.

figure 6.14(a): Second Order Low-Pass Filter Having a Roll off of -40 dB Per decade

This steeper roll-off rate is achieved by using the C1R2 section together with feedback
from the output via capacitor C2 to the junction of R1 and R2.

Scenario:
Case 1:
At low frequencies, XC1 and XC2 are much larger than R1 and R2 and
consequently, they have no significant effect on the circuit. So, the output
voltage is equal to the input, giving a voltage gain of 1.
Case 2:
At high frequencies, the effect of C1 and R2 causes the output to fall off at
a rate of 20 dB per decade as the frequency increases.
There is no phase shift from the input of the voltage follower to its output.
However, there is a phase lag introduced by C1 and R2, and there is a
phase lead generated by C2 combined with R1 and R2. The result of these
phase differences is that the feedback via C2 produces a further fall off (or
roll off) of 20 dB per decade.
The two gain reducing effects combine to produce a fall-off rate of 40 dB
per decade, as illustrated by the frequency response in figure 6.14(b).

## figure 6.14(b): Frequency Response of Butterworth and Chebyshev Low-pass Filters

Design:
Circuit is designed using Butterworth low-pass filter having a roll off factor of 40
The resistance of R1 + R2 is first determined as,

## First-Order High-Pass Filter:

The first-order high-pass filter circuit in is as shown in the figure 6.15(a) below

## Figure 6.15(a): first-order high-pass filter

The above circuit is made up of a passive high-pass circuit, C1 and R1, and a voltage

Scenario:
Case 1:
At high frequencies, XC1 is very much smaller than R1, there is virtually
zero attenuation, and the circuit voltage gain is 1.
Case 2:
When the frequency drops to the point at which X C1 equals R1, the voltage
gain drops by 3 dB as shown in figure 6.15(b).
As the frequency decreases further, the voltage gain rolls off at 20 dB per

## Figure 6.15(b): Frequency response of High Pass Filter

Design:
R1 = R(max) should be calculated using the specified I B(max) for that particular opamp and it is also desirable to keep R1 as large as possible for maximum filter
input impedance. The general expression is given as,

## Figure 6.16(a): Second Order High Pass Filter

Scenario:
Case 1:
At high frequencies, XCl and XC2 are much smaller than R1 and R2,
consequently, C1, C2, R1 and R2 have no significant effect on the circuit.
The output voltage is then equal to the input, giving a voltage gain of 1.
Case 2:
At low frequencies, the effect of C2 and R2 causes the output to fall off at a
rate of 20 dB per decade as the frequency decreases. A phase lead is
produced by C2 and R2, and a phase lag is generated by R1 combined with
C1 and C2. So, feedback via R1 produces a further roll-off of 20 dB per
decade and the total roll-off rate is 40 dB per decade, as illustrated in
figure 6.16(b)

## Figure 6.16(b): Frequency response of Second Order High Pass Filter

Design:
R2 = R(max) should be calculated using the specified I B(max) for that particular opamp and it is also desirable to keep R1 as large as possible for maximum filter
input impedance. The general expression is given as,

## Capacitor C1 is selected to be equal as that of C2,

Above design values are selected such that impedance XC1 satisfy the equation,

VTU Question:
1. With a neat circuit diagram, transfer characteristics and waveforms, explain the circuit
operation of an OP-amp inverting Schmitt trigger circuit. December 2015 (10 M),
December 2014 (08 M), June 2014 (07 M), June 2015 (08 M)
2. With a neat circuit diagram and waveforms, explain the circuit operation of an OP-amp
astable multivibrator. December 2014 (06 M)
3. Using a 741 Op-Amp, design a second order active high pass filter for a cut off frequency
of 4.5 kHz. December 2014 (06 M)
4. Sketch the circuit of a second order low pass filter and explain its working. June 2014
(07 M)
5. An INV Schmitt trigger circuit is to have UTP = 0 V and LTP = 2.5 V. Design a suitable
circuit using a bipolar Op-amp with 15 V supply. June 2014 (06 M)
6. Sketch the circuit of an Op-amp astable multivibrator and show the voltage waveforms at
various points and explain its operation. June 2014 (07 M)
7. With a neat circuit diagram, waveform and expressions, explain the capacitor coupled
non-inverting cross detector. December 2012 (08 M), December 2013 (08 M)
8. With a neat circuit diagram, explain how diodes may be used to select the trigger points
of an inverting Schmitt trigger circuit. December 2013 (06 M)
9. Design a second order low pass filter circuit to have a cutoff frequency of 1 kHz(for 741
frequency extends upto 800 kHz with Av = 1) December 2013 (06 M), June 2014 (07
M)
10. Explain how Op-amp can be used as inverting and non-inverting comparator. What is its
limitation? Explain how the limitations can be overcome using a Schmitt trigger. June
2013 (10 M)
11. An inverting Schmitt trigger circuit is to have UTP = 0 V, LTP = -1 V. Design a suitable
circuit using bipolar opamp with 15 V supply. June 2013 (05 M)
12. Design a second order active low passs filter for a cutoff frequency of 70 kHz. June 2013
(05 M)
13. Explain opamp inverting Schmitt trigger for adjustable UTP and LTP. December 2012
(08 M)
14. Using a741 opamp design a first order active low pass filter to have a cut off frequency of
1 kHz. December 2012 (04 M)
15. Design a opamp based monostable multivibrator to generate a pulse of width PW = 2ms.
The trigger is a pulse of amplitude 3V and duration 150 s. Use a bipolar opamp and a
supply of 12 V. December 2012 (08 M)
16. With a relevant diagrams, explain basic inverting and non-inverting comparator circuit
with V ref = 0 V. December 2015 (06 M)

17. Using 741 op-amp, design the first order active low pass filter to have a cutoff frequency
of 1.2 kHz. December 2015 (05 M)