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Voltage Scaling
Seungyong Oh, Jungsoo Kim, Seonpil Kim and Chong-Min Kyung
Dept. of Electrical Engineering & Computer Science
KAIST (Korea Advanced Institute of Science and Technology)
Email: {syoh, jskim, spkim} @vslab.kaist.ac.kr, kyung@ee.kaist.ac.kr
I. I NTRODUCTION
Power-efciency is one of the biggest concerns in modern
embedded system design. Many techniques have been developed to reduce the energy consumption of the microprocessor
which is one of the major contributors to energy consumption
of embedded system. Dynamic voltage scaling (DVS) reduces
the power consumption of a processor using a quadratic
dependence of active power consumption on supply voltage.
DVS can be classied into two different methods according
to its scaling granularity. The rst one is inter-task DVS which
adjusts the voltage/frequency level between tasks. The task in
this context means the independent software which can be
scheduled by an operating system. The second one is intratask DVS which adjusts the voltage/frequency level a number
of times in a single task boundary. This method is based on the
fact that the execution cycle of the software is not deterministic
but has a prole of large variation. Hence, it can utilize the
time slack caused by run-time variation of execution cycle
efciently.
The effectiveness of intra-task DVS method has been studied throughout many researches. In most cases, intra-task DVS
method outperforms the inter-task DVS. However, it also has a
limitation. The main drawback comes from the fact that a large
number of voltage switching should be executed to achieve
a large energy reduction. Because the intra-task DVS has to
adjust its supply voltage level dynamically during the tasks
execution, the overhead which comes from voltage switching
is unavoidable. In fact, it has been shown that intra-task DVS
becomes more powerful when the number of voltage switching
increases [3] [7].
This voltage switching overhead becomes a main bottleneck
in its practical implementation. Even a current state-of-theart DC-DC converter takes tens of sec in voltage switching
[1]. As the number of voltage switching increases, the time
consumed for voltage switching also increases, thus the time
for execution of real application decreases. Hence, the voltage
switching has to be performed very efciently to minimize
this switching overhead in intra-task DVS.
The goal of our research is to maximize the effectiveness of
intra-task DVS by minimizing the voltage switching overhead
for hard real-time application. More specically, we propose
an algorithm which partitions the program into number of code
sections in a way that voltage switching is only performed
when it is necessary. In our experiment, it is shown that the
number of voltage-switching can be reduced drastically while
keeping the same amount of energy reduction. Furthermore,
additional energy reduction is also achievable by proposed
method.
The rest of paper is organized as follows. In section II,
we present related works on intra-task DVS. Section III describes the details of proposed method called task partitioning
algorithm. Next, Section IV shows the experimental result of
proposed method. Finally, we draw our conclusions in section
V.
II. R ELATED WORK
Lee and Sakurai [3] proposed an idea of the intra-task DVS
method. A. Azevedo et al. [4] used the program check point
to apply intra-task DVS. Their works utilized the time slack
by analyzing the worst-case execution cycle of remaining task.
However, the variation of remaining workload and execution
path was not considered. Seo et al. [5] proposed the virtual
execution path. In this work, they tried to nd the optimal
execution path among many paths caused by branches. As in
[4], they also took the worst-case execution cycle as a remaining workload of each path. Hong et al. [7] proposed prolebased remaining workload predicting method. In this work,
statistically-optimal remaining workload was determined using
each performance regions prole information.
All these previous works have been focused on which level
the voltage has to be adjusted to. However, no work has been
done on at which points of the programs execution the DVS
should be applied considering voltage switching overhead.
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B. Motivation
A. Preliminary
Task 1
WR1
Code Section 1
WR2
Code Section 2
Fig. 1.
...
WRN
Code Section N
Intra-task DVS
1) Intra-task Dynamic Voltage Scaling: In intra-task Dynamic Voltage Scaling, the task is divided into a number of
code sections as shown in Fig.1. This code section becomes
the basic unit of voltage scaling. In the same code section, the
voltage is maintained at the same level and the voltage can be
switched to a different level between code sections. If we can
estimate the remaining workload (how many cycles are left)
exactly, it would be possible to lower the frequency as much
as possible for each section by using this simple equation.
wRi
(1)
fi =
ti
(2)
C ase A
n1
P r o b a b ility
n1
(3 0 0 )
(1 5 0 )
100
(A -2 )
n2
300
50 150 300
600
(A -3 )
n2
(1 5 0 )
(4 0 0 )
50 150 300
400
PE
(B -3 )
(7 0 0 )
300
A -1
(B -2 )
n3
n3
(3 0 0 )
n2
n1
f1 = 1 0 0 H z
A -2
PE
n1
X VZ
f1 = 1 0 0 H z
A -3
PE
Y
f1 = 1 0 0 H z
E x e c u tio n
c y c le
f2 = 1 0 0 H z
n2
f2 = 7 7 .8 H z
n1
f2 = 1 7 5 H z
n3
f3 = 1 0 0 H z
n3
f3 = 7 7 .8 H z
n2
n3
f3 = 1 7 5 H z
1 0 0 .0 0
5 2 .3 8
X 1 /3
2 7 4 .3 8
x2
< E n e r g y c o n s u m p tio n (n o m a liz e d ) >
700
B -1
PE
n2
n1
f1 = 1 0 0 H z
B -2
X VZ P E
n n2
1
f1 = 1 0 0 H z
B -3
PE
Y
n3
f2 = 1 0 0 H z
n1
f1 = 1 0 0 H z
n3
f2 = 8 9 .5 H z
n2
f2 = 1 2 1 .4 H z
f3 = 1 0 0 H z
f3 = 7 8 .3 H z
n3
f3 = 1 5 4 .5 H z
1 0 0 .0 0
5 1 .9 3
X 1 /3
2 4 1 .2 6
x2
< E n e r g y c o n s u m p tio n (n o m a liz e d ) >
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C ase B
C ase A
n1
n2
(5 0 0 )
(5 0 0 )
n1
n2
(7 0 0 )
(3 0 0 )
x 10
3
RXWW
n 1 (5 0 0 )
f1 = 1 0 0 H z
PE
n 1 (6 0 0 )
f1 = 1 0 0 H z
PE
n 2 (5 0 0 )
f2 = 1 0 0 H z
RXWW
n 2 (5 0 0 )
1 0 0 .0 0
1 3 8 .1 3
+100
PE
n 2 (3 0 0 )
f2 = 1 5 0 H z
1 0 0 .0 0
1 4 7 .5 0
+100
2.5
f2 = 1 0 0 H z
n 1 (8 0 0 )
f1 = 1 0 0 H z
f2 = 1 2 5 H z
n 2 (3 0 0 )
n 1 (7 0 0 )
f1 = 1 0 0 H z
Energy penalty
PE
2
1.5
1
0.5
10000
1000
20000
0
30000
Remaining workload
1
(X 1 )
0
(X 0 )
PE
n 0 (X 0)
n 1 (X 1)
{
R PE
n 0 (X 0 +X)
n 1 (X 1)
Fig. 4.
Emiss
= (
Fig. 6.
Static simulation
( profiling info. )
Task partitioning
Complete
2
x1
x0 + x1 2
]
) (x0 + x) + [
x1
= (
x
+x
T
T ( x00 +x1 )T
2
x1
x0 + x1 2
] x1
) x0 + [
x0
T ( x0 +x1 )T
T
Misprediction penalty
E pnt.
n>
E th
Merging nodes
D. Feasibility check
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1 When
TABLE I
C OMPARISON OF ENERGY CONSUMPTION
:
# code sections
1
30
60
120
180
210
270
300
E
Fig. 7.
Reduction(%)
0.00
6.69
14.70
23.27
23.72
27.61
13.83
0.00
ZWGG
w
n0
n78
n119 n150
(78)
(41)
(31)
(24)
(33)
(21)
(19)
238
n n n n n n n n n n n n n n n n n n n n n n n n n n n n
j n0 n
10 20 30 40 50 60 70 80 90 100 120 120 130 140 150 160 170 180 190 200 210 220 230 240 250 260 270 280 290
Fig. 8.
proposed
122.16
93.64
75.17
56.10
51.55
50.31 *
63.17
77.35
Hong[7]
122.16
100.35
88.12
73.11
67.58 *
69.50
73.31
77.35
[1] O. Trescases and W. Ng. Variable Output, Soft-Switching DC/DC Converter for VLSI Dynamic Voltage Scaling Power Supply Applications,
PESC, 2004
[2] T.Simunic, L.Benini and G. DeMicheli Cycle-accurate simulation of
energy consuption in embedded systems,DAC,1999
[3] S.Lee and T.Sakurai. Run-time Voltage Hopping for Low-power RealTime Systems, DAC, 2000
[4] A. Azevedo, I. Issenin, R. Cornea, R. Gupta, N. Dutt, A. Veidenbaum, and
A. Nicolau, Profile-Based Dynamic Voltage Scheduling Using Program
Checkpoints, DATE, 2002.
[5] J. Seo, T. Kim, and K. Chung, Profile-Based Optimal Intra-Task Voltage
Scheduling for Hard Real-Time Applications, DAC, 2004.
[6] D. Shin, S. Lee, J. Kim Intra-Task voltage scheduling for low-energy
hard real-time applications, IEEE Design & Test of computers.2001.
[7] S. Hong, S. Yoo, H. Jin, K. Choi, J. Kong, S. Eo, Runtime DistributionAware Dynamic Voltage Scaling, ICCAD, 2006.
[8] ARM SoC Designer, available at http://www.arm.com/product/DevTools
/MaxSim.html
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