SoC Design

Lecture 1: Introduction

Shaahin Hessabi
Department of Computer Engineering
Sharif University of Technology

System--on
System
on--Chip

System: a set of related parts that act as a whole to achieve

a given goal.
A system is a set of interacting components, which has
inputs and outputs, and exhibits specific behavior.

System: an entity consisting of hardware and software

Behavior: a function that translates inputs into outputs

H d
Hardware:
hi
high
h speed,
d llow power consumption,
ti
lless price
i
(probably)
Software: flexibility,
y, ease of modification and upgrade
pg

Hardware system: a system whose physical components

are electronic blocks

Analog
Digital
Mi d signal
Mixed
i
l

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SoC: Introduction

Slide 2 of 32

Digital vs. Analog Systems

The critical advantage of digital systems is their ability to

deal with electrical signals that have been degraded.

Due to the discrete nature of the outputs, a slight variation in an

input is still interpreted correctly.

In analog circuits, a slight error at the input generates an

error att the
th output.
t t
The simplest form of a digital system is binary.
A binary
bi
signal
i
l iis modeled
d l d as taking
t ki on only
l ttwo di
discrete
t
values (0
(0 or 1, LOW or HIGH, False or True).

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SoC: Introduction

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Advantages of Digital Systems

1.
2
2.
3.
4.
5.
6
6.
7.
8
8.
9.

High noise immunity

Adjustable precision
Less sensitivity to variations in components and
environmental parameters (especially temperature)
Ease of design (
( automation) and fabrication, and
therefore, low cost
Better reliability
Less need to calibration and maintenance
Ease of diagnosis and repair
Easy to duplicate similar circuits
Easily controllable by computer
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SoC: Introduction

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Disadvantages of Digital Systems

1.
2.

Lower speed
N d analog
Need
l tto di
digital
it l (A/D) and
d di
digital
it l tto analog
l (D/A)
converters to communicate with real world; therefore,
more expensive or less precise

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SoC: Introduction

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Contemporary Digital Design

Major changes in digital design in recent years:

Scale

Pervasive use of computercomputer-aided design tools over hand methods

M lti l llevels
Multiple
l off d
design
i representation
t ti

Time

More complex designs New methodologies and techniques required,

like SoC
Shorter timetime-to
to--market (TTM)
Cheaper
p p
products

Emphasis
p
on abstract design
g representations
p
Programmable rather than fixed function components
Automatic synthesis techniques
Importance of sound design methodologies

Cost

higher levels of integration

use of simulation to debug designs

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SoC: Introduction

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Software Tools

Digital design need not involve any software tools; however,

Software tools are nowadays an essential part of digital design.

design
HDLs (Hardware
(Hardware Description Languages)
Languages) and the corresponding simulation
and synthesis tools are widely used.

In a CAD (Computer(Computer-Aided Design) environment, the tools improve

the productivity and help in correcting errors and predicting behavior
behavior..

Schematic entry;
HDLs compilers, simulators and synthesis tools;
Timing analysers;
Simulators
Test benches.

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SoC: Introduction

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Integrated Circuits (ICs)

An IC is a collection of gates/blocks/... fabricated on a single silicon

chip.
chip
ICs are classified by their size:

SSI ((small scale integration):

g
) 1 to 30 ggates
- a small number of gates.
MSI (medium scale integration): 30 to 300 gates
- decoder,
decoder register,
register counter
counter.
LSI (large scale integration): 300 to 300
300,,000 gates
- small memories, PLDs.
VLSI (very large scale integration): > 1,000
000,,000 transistors
- microprocessors, memories.

The Core 2 Extreme QX9650

QX9650 Quad Core Processor (Intel 2008
2008,, 45
nm technology) has 820 million transistors (420
(420 M transistors per die)

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SoC: Introduction

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Implementation Technologies

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SoC: Introduction

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Modern Systems

Basic elements:

Microprocessors,
p
, buses and ASICs.

Basic problems:

HW/SW partitioning.
HW/SW coco-simulation
i l ti (including
(i l di communication
i ti modeling).
d li )
Different design tradetrade-offs.
Separate HW and SW design
g flows.

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SoC: Introduction

Slide 10 of 32

What is an SoC?
SoC Concept in the past simply implied higher levels of
integration (Moores law):
A single
i l chip
hi replaces
l
the
h whole
h l multichip
l i hi systemsystem-on
on-board
Different chips on PCB (Printed Circuit Board) are now
building blocks (cores) of SoC chip
Advantages:

On-chip interconnects are man

Onmany times faster than off
off--chip wires
ires
Get a compact system with the same functionality
Reduces pin overhead
Saves much power
Reduces noise in the mixedmixed-signal/analog circuits
Lower overall cost

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SoC: Introduction

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What is an SoC? ((contd))

Todays concept: gaining overall productivity gains through
reusable design
g and integration
g
of components
p

Complex
p
IC that
integrates the major
functional elements of a
complete endend-product
into a single chip using
intellectual property (IP)
blocks.

IPs: p
pre-designed
preg
and
pre--verified
pre
Also called: virtual
components

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SoC: Introduction

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Proceeedings of the
t IEEE,,
June 20006

Design
g Productivityy Gap
p

SoC/IP approach improves the situation

Platform--Based Design improves it further
Platform
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SoC: Introduction

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Inside an SoC

An SoC usually contains:

Reusable IP

Requires connecting computational units to communication medium

Embedded processor, memory

Real--world interface (wireless receiver/transmitter
Real
receiver/transmitter, ))
Sensor
Mixed--signal blocks
Mixed
Programmable hardware
RTOS and embedded software, device drivers

Has more than 500 K gates,

gates
Uses .25
.25 m technology or below
Is not an ASIC

Primary difference from ASIC: in SOC design, the goal is to

maximize reuse of existing blocks or cores

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SoC: Introduction

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Whyy SoC ?

Increased functionality/performance in reduced footprint

Tighter design schedule
Bandwidth and performance
Simplified PCB design
Increased product mechanical robustness
Lower power consumption
Technology scaling
Lower system cost

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SoC: Introduction

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System--in
System
in--a-Package (SIP)

SoC technology a great success, EXCEPT for radio

receiver/transmitters

Can sustain mixed analog/digital hardware together on one chip,

provided that:
Analog
A l h
hardware
d
iis iin th
the llowlow-frequency
f
band
b d
Digital clocks & their harmonics are carefully chosen to avoid
polluting key parts of the spectrum with noise
Key result: Still unable to integrate radio frequency (RF)
hardware into SoC
Substrate coupling between digital and analog parts causes
digital clock noise to destroy the signalsignal-toto-noise ratio of RF
part
RF tuners still require precision inductors
inductors, but onon-chip
inductors are expensive and inadequate

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SoC: Introduction

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System
Systemy
-in
in--a-Package
g (SIP)
(
)

Interim solution: Combine separate digital & analog chips

and passive components into a single package (SIP
(SIP, or
MCM= Multi
Multi--Chip Module)

Common 2-D or 3-D substrate

May contain SoC as one of the chips

Proceedings of the IEEE,

JJune 2006

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SoC: Introduction

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SoC Challenges

Increasing complexity

Integration
g

Time--to
Time
to--market pressure
Verification bottleneck
Hardware v.s.
v.s. software
Digital circuits v.s
v.s.. analog circuits
Testing issues

Deep submicron effects

Ti i closure
Timing
l
problem
bl
Signal integrity problem
Reliability problem

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SoC: Introduction

Slide 18 of 32

Time--to
Time
to--Market Pressure
Pressure from shorter product lifespan

An additional key factor in TTM, specific for SoC: System

integration
g
= integrating
g
g different silicon IPs on the same IC
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SoC: Introduction

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Time--toTime
to-Market Pressure (contd)

Profit model showing the value of TTM:

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SoC: Introduction

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Verification Bottleneck

Verification becomes the major bottleneck of the modern

design flows

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SoC: Introduction

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SoC Challenges

Increasing complexity

Integration
g

Time--to
Time
to--market pressure
Verification bottleneck
Hardware v.s.
v.s. software
Digital circuits v.s
v.s.. analog circuits
Testing issues

Deep submicron effects

Ti i closure
Timing
l
problem
bl
Signal integrity problem
Reliability problem

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SoC: Introduction

Slide 22 of 32

HW/SW Integration

Integrating HW/SW at the final step may require high

cost.

Early integration (HW/SW codesign)

Trend toward increasing design

complexity due to integration

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SoC: Introduction

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Challenges for Mixed Signal Designs

Design challenges

Chip-level
Chi
Chipl
l simulation
i l ti ttakes
k ttoo much
h ti
time
Design budgets are not distributed in a wellwell-defined manner
Too much time is spent on lowlow-level iterations
Design is not completely systematic
There is limited or no use of HDL

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SoC: Introduction

Slide 24 of 32

SoC Testing Challenges

Distributed design and test

Core
C
provider
id d
does nott kknow th
the ttargett environment
i
t
System integrator is responsible for manufacturing testing

Test access

Bed-of
Bedof--nails (decomposition) system testing is not possible
Most of the cores are surrounded by many other cores

R
Results
lt iin very poor controllability
t ll bilit and
d observability
b
bilit
Need electronic test hardware to access these blocks during testing
Bandwidth, I/O pin count limitations

Test optimization

Minimizing test cost while satisfying constraints such as power,

resources coverage
resources,
coverage, etc
etc.

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SoC: Introduction

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SoC Challenges

Increasing complexity

Integration
g

Time--to
Time
to--market pressure
Verification bottleneck
Hardware v.s.
v.s. software
Digital circuits v.s
v.s.. analog circuits
Testing issues

Deep submicron effects

Ti i closure
Timing
l
problem
bl
Signal integrity problem
Reliability problem

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SoC: Introduction

Slide 26 of 32

Timing Closure Problem

Traditional silicon design flows: used statistical wirewire-load

models to estimate metal interconnects for prepre-layout timing
analysis
l i

Wire delay starts to dominate total delay in DSM process

Lack of physical information about wire length

load on a specific node: estimated by the sum of the input

capacitances of the gates being driven
statistical wire estimate based on the size of the block and the
number of gates being driven
Correct for 250 nm and above, because the gate propagation
delays and gate load capacitances dominate

Only statistical wire delay model can be used at design phase

Inaccurate because they represent a statistical value based on the
block si
size
e

Incorrect estimations require long iterations to meeting timing

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SoC: Introduction

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Signal Integrity, Reliability

Feature size subsub-wavelength lithography (impacts

of process variation), noise, crosscross-talk, SEU, reliability
Frequency , dimension interconnect delay,
electromagnetic
l t
ti field
fi ld effects,
ff t timing
ti i closure
l
Supply voltage signal integrity (noise, IR drop,
etc)
Wiring level manufacturability
Power consumption
power & thermal issues

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SoC: Introduction

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General Architecture of CoreCore-Based SoC

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SoC: Introduction

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Design Flow
1
1.

Traditional Design Flow:

Front--end design
Front

2.

Back--end design
Back

Begins with system definition in behavioral or algorithmic form

and ends with floor planning
Begins with placement/routing through layout release (tape(tape-out)

Engineers in either phase dont know much about the

other phase

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SoC: Introduction

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Design Flow (contd)

Vertical Integrated Design Environment:

E i
Engineers
h
have ffullll responsibility
ibilit ffor a bl
block
k ffrom system
t
design specifications to physical design prior to chipchiplevel integration

Necessary for functional verification of complex blocks with postpostlayout timing

Avoids last minute surprises related to block aspect ratio, timing,
routing, or architectural and area/performance tradetrade-offs
Must be familiar with several CAD tools in a complex EDA
environment

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SoC: Introduction

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Task responsibilities of an engineer in a

vertical
rti l d
design
i n environment
n ir nm nt

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SoC: Introduction

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