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L4
L5
XTAL2
32kHz
22pF
RTXI
100nF
22pF
RTXO
CLKIN
100nF
100nF
100nF
CP1
RSET
C10
+VDD
100nF
RLNA
D1
100nF
CP2
XTAL1
OSC1
OSC2
L2
VRO
VDD INT
10nF
CONTROLLER/PERIPHERALS
100F
100nF
ADSP-BF531
400MHz
52KB SRAM
FL0
SLE
FL1
SDATA
FL4
SREAD
FL3
UART
FL5
MUXOUT
FL6
CE
C7
R12
C13
22nF
VREG1
R11
C12
C11
VCO_IN
CVCO
C1
SERIAL
EEPROM
(BOOT)
RFINB
RxCLK
RCLKO
EXTERNAL BUS
L3
Tx/Rx DATA
SPORT0
SPI
C6
RFIN
CPOUT
DTOPRI
BF
FILTER
RFIN
ISM
TRANSCEIVER
433/868/915MHz
INT/LOCK
DROPRI
SPORT1
ADF702x
SCLK
RFSO
L1
C5
ADC_IN
VREG2
C2
VREG3
C3
VREG4
C4
OPTIONAL
SDRAM
VE
http://www.analog.com/analogdialogue
A Versatile Transceiver
RLNA
RSET
CREG(1:4)
BIAS
LDO(1:4)
LNA
RFIN
ADC INPUT
TEMP
SENSOR
OFFSET
CORRECTION
TEST MUX
LPF
BB
FILTER
RFINB
MUX OUT
MUX
RSSI
7-BIT ADC
FSK/ASK
DEMODULATOR
DATA
SYNCHRONIZER
GAIN
LPF
OFFSET
CORRECTION
CE
AGC
CONTROL
FSK MOD
CONTROL
PA OUT
DIVIDERS/
MUXING
GAUSSIAN
FILTER
DIV P
-
MODULATOR
Tx/Rx
CONTROL
RxCLK
Tx/Rx DATA
XCLK OUT
AFC
CONTROL
INT/LOCK
N/N+1
SLE
SERIAL
PORT
VCO
CP
SDATA OUT
SCLK
PFD
DIV R
VCO IN CP OUT
SDATA IN
RING
OSC
CLK
DIV
XTAL
CLK OUT
DSP_Tx
INPUT OR
JPEG SOURCE
CODING
PACKETIZATION
CRC
RF TRANSMITTER
CONVOLUTIONAL
ENCODER
BLOCK
INTERLEAVING
+
RATE CONTROL
MODULATION
(GFSK)
CHANNEL CODING
NOISE DISTURBANCES
TRANSMISSION
CHANNEL
FEEDBACK/QoS
DSP_Rx
DATA
OUTPUT OR
JPEG SOURCE
DECODING
DE-PACKETIZATION
CRC
VITERBI
DECODER
BLOCK
DEINTERLEAVER
SYNC
DEMODULATION
(GFSK)
SYNCHRONIZATION
RF RECEIVER
CHANNEL DECODING
CMOS
VIDEO
SENSOR
ADSP-BF531
ENCODE BOARD
DECODE BOARD
LCD
DISPLAY
ADSP-BF531
MJPEG
ENCODER
+
FEC
ADF7020
ADF7020
ISM
TRANSCEIVER
ISM
TRANSCEIVER
MJPEG
ENCODER
+
FEC
AUDIO
CODEC
BATTERY CELL
POWER
MANAGEMENT
BATTERY CELL
POWER
MANAGEMENT
AUDIO
CODEC
RANGE FROM
FEW TO TENS
OF METERS
A very low BER does not ensure that all the data packets will be
entropy-decoded correctly. To improve the image quality, it is
necessary to provide some mechanism to conceal part of an image
if too many important bits in a packet are corrupted. For this
purpose, every packet is segmented and entropy-coded separately.
After the detection of an erroneous segment or block, its content is
discarded. Depending upon the information lost, the dc and first
two ac coefficients of the discrete cosine transform (DCT) of the
corresponding image block are estimated from the coefficients of
the neighboring blocks. The final low-pass 2D 3 3 de-blocking
filter stage, designed to remove DCT blocking artifacts, helps to
smooth resulting distortion.
The ADSP-BF531 has more than enough power to handle
both the MJPEG encoding or decoding and the channel FEC
processing. No external memory is required for frame sizes up to
QCIF (176 pixels by 144 pixels) with a 4:2:2 video format. Larger
frames are possible at the cost of an external SDRAM, which
can also be used to store compressed video. This very low-cost
processor can interface directly to CCIR-656-compatible low-cost
CMOS image sensors or TFT displays via its parallel peripheral
interface (see Blackfin Processors Parallel Peripheral Interface
Simplifies LCD Connection in Portable Multimedia).10 Standard
low-cost, low-power PCM audio codecs can be connected to the
available serial port, SPORT1, to support digital transmission
of speech or audio. Or, the processor can provide speech coding
and decoding with moderate delay by executing a software codec
similar to the FR-GSM (13 kbps).
With a raw data rate of 200 kbps it is possible to achieve baseline
MJPEG transmission over ISM at a rate of about four QCIF
4:2:2 color-frames per second (fps), while leaving 20 kbps
for speech. This is acceptable for simple low-cost consumer
appliances, such as video baby monitors, video door phones, or
wireless home-security cameras. The functional block diagram
of such a point-to-point video transmission system (baby monitor)
CONCLUSION
http://www.bluetooth.com
http://grouper.ieee.org/groups/802/11/main.html
3
http://www.analog.com/en/prod/0,2877,ADF7020,00.html
4
http://www.analog.com /processors /processors /blackf in/
index.html
5
http://www.analog.com/en/prod/0,2877,ADSP-BF531,00.html
6
http://www.linxtechnologies.com/documents/EN3002201_2000.pdf
7
http://www.fcc.gov/oet/info/rules
8
http://www.analog.com/en/prod/0,2877,ADF7025,00.html
9
http://www.analog.com/en/content/0,2886,770_850_
16127,00.html
10
http://www.analog.com/library/analogdialogue/archives/39-01/
lcd_drive.html
11
http://www.arbos-dsp.com
2