801

Noveel Tran
nsistorr Levell Realiizationn of Ulltra Loow
Pow
wer High-speeed Ad
diabatiic Veddic Muultiplieer
M. Ch
handa1, S. Baanerjee2, D. Saha3, S. Jaain4
ECE
E Dept.1&4, VD
DTT Dept.2 andd ETCE Dept.3
Meg
ghnad Saha Insstitute of Techn
nology1&4, IIT D
Delhi2, Jadavppur University3
1
2
manassh.bst@gmail.ccom , suvadip192@gmail.co
om , deepon.sahha@gmail.com
m2, sankalp.00001@gmail.com
m4

AbstraactIn this paper,

p
we desccribe an energy
y-efficient Ved
dic
multiiplier structuree using Energy Efficient Adiabatic
A
Log
gic
AL). The powerr consumption of the propossed multiplier is
(EEA
signifficantly low because the en
nergy transferrred to the loa
ad
capaccitance is mosttly recovered. The
T proposed 8x8 CMOS an
nd
adiab
batic multiplier structure havee been designed
d in a TSMC 0.1
18
m C
CMOS process technology an
nd verified by Cadence Desig
gn
Suite.. Both simula
ation and meeasurement ressults verify th
he
functiionality of such logic, makin
ng it suitable for
fo implementin
ng
energgy-aware and performancee- efficient very-large
v
sca
ale
integrration (VLSI) circuitry.
c

Thhe rest of the paper is orgaanized as folloows. Section II

describbes the operatiion of EEAL innverter and also addresses thee
issue oof power dissiipation of thiss proposed loggic. Section III
shows the general implementatioon of NN Vedic multiplier
based on Urdhvaa-Tiryakbhyam
m sutra or Vertical and
d
wise algorithhm. Implemenntation of connventional and
d
Crossw
adiabaatic 88 multipplier, experimeental results aand comparison
n
of perrformance off our energy recovery loggic with other
imperaative logic styyles are also deetailed in sectiion IV. Finally
y
concluusions are givenn in section V..
II. EEAL LOGIC

Keywoords: adiabatic;; single phase; lo

ow power, multiiplier.

I.INTRODU
UCTION
A plethora of multiplication algorithm hass been proposeed
recenntly in literatu
ure [1]-[8]. In
I this paper we present a
system
matic design methodology
m
for
f fast and areea efficient dig
git
multiiplier based on
o Vedic math
hematics [3],[4
4],[9]-[12]. Th
he
Multiiplier Architeccture is based on the Urdhv
va-Tiryakbhyam
[9], ssutra or Verttical and Crosswise algoriithm of ancient
Indiaan Vedic Mathematics. Conv
ventional, as well
w as, adiabattic
88 Vedic multip
plier structure have been implemented
i
in
MC 0.18m CM
MOS technolog
gy, using CAD
DENCE Desig
gn
TSM
suite..
A
Adiabatic swittching [13]-[15
5] has recentlly become of a
certaiin interest, and
d is being impleemented in maany systems. Th
he
approoach is based on
o a slow charg
ging of the capacitive nodes by
b
time--varying clock
ked ac power and a partial recovery of th
he
energgy used by slow
wly decreasing
g the supply witthout sacrificin
ng
noisee immunity an
nd driving ab
bility. In this paper, Energ
gy
efficiient adiabatic logic (EEAL) based
b
on DCVS
S logic [16], haas
been introduced as an adiabatic lo
ogic style. EEA
AL requires on
nly
wer clock supplly, has simple implementation,
one ssinusoidal pow
and iis geared towarrd high-speed and low-energ
gy VLSI desig
gn.
In E
EEAL, high speed
s
operatio
on as well as low energ
gy
consuumptions are ensured by using a paralleel resistive paath
betweeen the outpu
ut nodes and clock supply
y. EEAL log
gic
featurres simplicity and static log
gic resembled
d characteristiccs,
whichh substantially
y decreases transistor
t
overrheads and th
he
circuiit complexity.

EE
EAL is a duall-rail adiabaticc logic which cconsists of two
o
DCVS
S network and a pair of crosss-coupled PM
MOS devices in
n
each sttage, as illustraated by figure 1(a).

Figuree 1. EEAL logic (aa) Block diagram ((b) Inverter/Bufferr circuit (c)Power
supply (dd) Cascading of Invverter/Buffer circuuits

EE
EAL requires only one sinuusoidal powerr clock supply
y,
has siimple implem
mentation, andd performs better than thee
previoously proposedd adiabatic logiic families [133]-[15] in terms
of eneergy consumptiion. As single--clock circuit rrequires simplee
clock scheme [16], this logic stylle can enjoy m
minimal contro
ol
overheeads. figure 1 ((b) and (c) shoows the EEAL buffer/Inverter
circuitt and supply cloock () respecctively.

978-1-4673-5090-7/13/$31.00 2013 IEEE

802
T
The operation of EEAL inverter/buffer can
n be summarizeed
usingg figure 1 (b). Assuming thee complementaary output nodes
(outt and outb) are initially low
w and supply clock
c
() ramp
ps
up froom logic 0 ( 0
0 ) to logic 1 ( VDD) statee. Now if in =
0 aand inb= 1; N1, M1 will be turned off and
a M2, N2 an
nd
P1 w
will be turned ON. The ou
ut node is th
hen charged by
b
follow
wing the supp
ply clock () closely throu
ugh the paralllel
combbination of PM
MOS (P1) and NMOS (M2), whereas outb
b
node is kept at grround potentiaal, as N2 is On. When th
he
gs from VDD
D to ground, out node is
supplly clock swing
dischharged through
h the same charging
c
path and un-driveen
outbb is kept at saame ground po
otential. Resulttantly full swin
ng
can bbe obtained in out node an
nd ground pottential at outb
b
node.. Output voltaage swing for an adiabatic inverter at 10
00
MHzz frequencies with
w 20 fF capaccitive load is sh
hown in fig. 2.

So thhe adiabatic ggain can be improved drramatically by

y
prolonnging T. Hencee, the turn-on reesistance (RP) of the charging
g
or disscharging patth consists oof parallel coombination of
PMOS
S/NMOS transiistors and can bbe expressed aas,
R={n Cox(W/L)n(V
VDD-Vtn)+pCoxx(W/L)p(VDDD-Vtp)}1

={nC ox(W/L)n(VDDD-2VT)}-1

(5))

where (W/L)n ((W//L)p), n (p), Vtn (Vtp) are the aspecct

mobility and tthe threshold vvoltages of NM
MOS (PMOS)
ratio, m
respecctively; all the other terms hhave the usuall meaning. For
0.18m
m CMOS process, connsidering VDDD=1.8V and
d
(W/L)p =2(W/L)n, thee above expresssion gives R=11.02K.

T
The energy ad
dvantage of EEAL
E
circuit can be readily
underrstood by assu
uming a ramp
p type voltagee source whicch
ramps up between
n 0 and V
VDD and deliv
vers the charg
ge
me period T. The dissipation through th
he
CLVDDD over a tim
channnel resistance R is,
Ediss=
={(CLVDD)/T}2RT = {(RCL)/T
T}CL(VDD)2

(1)

Simillarly, energy consumption

c
during charging
g or dischargin
ng
proceess of the EEAL inverter/bufffer can be exprressed as,
2
E = {{(RPCL)/T} CL(V
( DD)2 + CL(V)
(

(2)

n-on resistancee of the paralleel path, CL is th

he
Hencce RP is the turn
outpuut load capacittances, T is thee charging tim
me and V is th
he
voltagge drop acrosss the resistive path. Though V depends on
o
time, yet due to very
v
small magnitude ( few
w millivolt) th
he
param
meter is treated as constant. In equation (2),
(
(CL(V))2)
measures the thresh
hold loss whicch is negligiblly small indeeed.
EEAL as charrging and disscharging proccesses consum
me
In E
almost similar amo
ount of energy,, total energy dissipation
d
forr a
a
compplete cycle can be expressed as,
Eload = 2{(RCL)/T} CL(VDD)2 + CL (V)2

(3)

nventional CM
MOS logic, which
w
consumees
Comppared to con
CLVDDD2 energy in
n a full cyclee (CL is load
d capacitancess),
adiabbatic gain (G) of
o EEAL becom
mes,
Adiabbatic Gain (G) in (%)
Energy comsum
mption by EEAL peer cycle
x100
Enerrgy Consumption by
b conventional CM
MOS per cycle

= [{22RPCL/T} + {(
V)/VDD}2] 100
1
= 2{R
RPCL/T}100 (as V<<VDD, {(V)/VDD}2<<1)
<

(4
4)

Figure 2. Output wavefoorms of EEAL inverter at 100 MHz ffrequencies with a

load of 100fF

IIII.IMPLEMENTA
ATION OF NN MULTIPLIER ST
TRUCTURE
3.1 U
Urdhva Tiryakbbhyam sutra
Thhe proposed m
multiplier is baased on an alggorithm Urdhvaa
Tiryakkbhyam (Verrtical & Crrosswise) [9]], a generaal
multipplication formuula of anciennt Vedic mathhematics. The
paralleelism in genneration of ppartial produccts and their
summaation is obtainned using Urddhva Tiryakbhhyam explained
d
later. S
Since the partiaal products andd their sums arre calculated in
n
paralleel, the multipliier is independdent of the clocck frequency of
the proocessor. It is ddemonstrated tthat this archittecture is quitee
efficieent in terms of silicon area/speed.
Thhe 22 or 444 multiplicaation utilizingg conventionaal
mathem
matical methoods (successivve additions w
when used on
n
compuuters) needs noo explanation. Hence, the Veedic method for
44 m
multiplication iss illustrated in the example below, shown in
n
Figuree 3. Hence digits of multiiplier and muultiplicands aree
placedd in two conseecutive sides ((along row andd column) of a
squaree. In case of NN multiplication (hencee N=4), wholee

803
squarre will be divid
ded into N2 (=16) no. of squ
uares, which wiill
be paartitioned again by crosswise line, as show
wn in Figure 3.
Each digit of the multiplier is then
t
independeently multiplieed
nd and the two
o-digit product is
with every digit of the multiplican
x. All the dig
gits lying on a
writteen in the smaall square box
crosswise dotted lin
ne are added to
o the previous carry. The leaast
n
acts ass the result dig
git
signifficant digit of the obtained number
and thhe rest as the carry
c
for the neext step. In thiss above examp
ple
initiaal carry is taken
n as logic 0.

So, X and Y can be represented ass XH XL and YHYL . Now the

steps aare given bellow
w,
multiplication between XL ((N/2 bits) and
d
1) Fiirst vertical m
Y L(N/2 bits) wiill produce totaal N no. of bitts. Out of thesee
..SLL(N/2)} aree taken as firsst
firrst N/2 bits {SLL(1) SLL(2)
N
N/2 outputs {S1 S2 .SN}. Lasst N/2 bits willl be used for NN
biit in next steps..
H
2) Inn next steps crooss-multiplicattions have done between (XH
,Y
YL) and (XL ,Y
YH)to producee two sets of N no. of bitss,
{S
SHL(1) SHL(2) SHL(3)..SHL(N)} aand {SLH(1) SLLH(2) SLH(3) ...
SLLH(N)} respectivvely. These tw
wo sets of N nno. of bits are
addded up to prodduce another N no. bits,S11 too S1N and C1 as
caarry.

Figure 3. Mu
ultiplication using UrdhvaTiryakbhy
U
am Sutra

3.2 Implementatio
on of general Vedic
V
multiplierr structure
IIn this section
n we first disccuss the organ
nization of 2
2
multiiplier block, which
w
will be further
f
used to
o configure 4
4
and 88 multiplier structurees. In 22 multiplication,
nputs (X and Y) having two
t
digits eacch
consiidering two in
(XX1X0 and Y
Y1Y0), we get four outputs (SS4S3S2S1) as
a
a resuult, by doing vertical and cross-multiplication and addition.
The ssteps are:
i) S1 iis the result of Vertical multip
plication betweeen X0 and Y0.
ii) S2 is the addition of crosswiree bit multiplicaation of (X1 an
nd
Y0) aand (X0 and Y1).
)
iii) S3 is the vertiical product of
o X1 and Y1, if no carry is
generrated from thee previous step
ps, otherwise carry
c
bit will be
b
addedd with the vertiical product to generate S3 as a sum.
iv) S4 is the carry geenerated during
g addition of S3.
B
By using this 22 multiplieer block 44, 88, 1616 etc
e
multiiplier block caan be implemen
nted. For NN
N multiplication,
show
wn in figure 4, N-bit
N
multiplier and multipliccand first will be
b
dividded into two eq
qual halves, co
onsisting of N//2 no. of bits in
each halve. Assum
ming N-bit mulltiplication bettween X and Y,
Y
a XH= {X (NN/2+1) X (N/2+2) X
we get XL= {X1 X2 X3.XN/2} and
o halves will be
b
(N/2+3)).XN}as two halves of X. For Y, its two
YL={{Y1 Y2 Y3YN/2
Y(N/2+1) Y(N/2+2) Y(N/2+3) .YN}.
N } and YH={Y

Figure 4. Geneeral block diagram

m of NxN Vedic Multiplier

Vertical multipllication betweeen XH (N/2 bitts) and YH (N/2

2
3) V
biits) also producces N no. of bbits, {SHH(1) SHHH(2) ..SHH(N)}.
O ut of these N bits, first N//2 bits, SHH(1) to SHH(N/2) are
caascaded with the last N/22 bits, {SLL((N/2+1) SLL(N/2+22)

..SLL(N)}, of vvertical multiplication betweeen XL and YL.

Thhese total N noo. bits will be added with thee output of firsst
N bit adder, S11 to S1N, to prodduce total N noo. of bits (from
m
multiplier. Thiss second N biit
S((N/2+1) to S(3N/22)) of NN m
adddition also prooduces a carry,, C2.
d
4) C 1 and C2 are ssent to the hallf adder to gennerate sum and
y
caarry bits. (N/2--2) no. of zeross will be insertted before carry
annd sum to prodduce a set of N
N/2 bits, as shoown in figure 4.
4
Thhese N/2 bits w
will be added uup by a N/2 bitt adder with the
laast N/2 bits of vvertical multipplication betweeen XH and YH,
which are {SHH((N/2+1) SHH(N/2+22) ..SHH(N)} . The outputs of
w
m
thhese N/2 bits adddition will prroduce the last N/2 bits (from
S((3N/2+1) to S(2N)) of NN multipplier.

804

S
So in a NN
N multiplicatio
on, we need four N/2N/2
multiipliers, two N bit
b adders, a haalf adder and a N/2 bit adder.

been ccompared. Perfformances of adiabatic 88 V

Vedic multiplier
are allso compared with the CM
MOS counterppart. Extensivee
simulaations have beeen done to veriify the functionnality of the alll
the mu
multiplier circuuits using CAD
DENCE Spicee Spectra. Thee
minim
mum transistor w
width in the 0.18m CMOS n-well process
is 180nnm.

Figuree 5. DCVS networrk (a) Sum block (b

b) Carry block (c) AND NAND blocck

S
Static conventiional CMOS lo
ogic style is used to implement
the conventional Vedic multip
plier. In case of adiabattic
w
impleementation, firrst we describee the EEAL gaates and then we
preseent the design
n of adiabatic 8x8 Vedic multiplier
m
usin
ng
EEAL
L logic. Com
mplex gates caan be easily implemented by
b
usingg simple NMO
OS based DC
CVS network. In Fig. 1, by
b
replaccing the DCV
VS network we
w can implem
ment the AND
DNAN
ND gate with EEAL
E
circuit topology. DCV
VS network for
fo
sum and carry block of Full add
der circuits, allong with AN
ND
blockk are shown in
n figure 5. We
W have design
ned an adiabattic
standdard-cell library
y, consisting of
o common diigital gates succh
as buuffer/inverter, two
t
inputs and
d three-input functions,
f
add
der
and multiplier blo
ock of varyin
ng bit length using Cadencce
ulator in 0.18m
m technology. W/L ratio of th
he
specttre circuit simu
PMO
OS and NMOS
S are taken witth W/L = 12 /2 and 6 /2
2
where =0.9 m.
3.3 Results and Siimulations
ge.
All ssimulations haave been donee under 1.8V supply voltag
Durinng simulation we
w apply {A} = {A7, A6, A5,A4, A3, A2, A1
and A0} and {B} = {B7, B6, B5,B4, B3, B2, B1 an
nd B0} as inputts.
Hencce random patteerns consist off four bits are assigned for eacch
inputt bit (Ai or Bi, where i = 0 to 7). The asssigned bits arre;
{A}=
={01010101, 00001111,
0
00110011,00010101, 00010101,
00001111, 001100
011 and 00010101} and {B}={01110011,
011, 01110011, 00010101,
00010101, 00001111, 001100
110011}. The simulated waaveform of 8
8
00001111 and 001
OS and Vedic multiplier are also shown in
n Figure 6 & 7
CMO
respeectively. Perforrmance measu
urement of 88
8 CMOS Ved
dic
multiiplier circuit along
a
with Carrry-Save, Arraay, Wallace treee
multiipliers with vaarying bit-sizes (2-bit, 4-bit,, and 8-bit) haas

Figurre 6. Output wavefform of 88 Conventional(CMOS) V

Vedic Multiplier

805

Vedic multiplier iss considerablyy faster comppared to other

existinng multiplier, as the speeed improvemeents of Vedicc
multipplier are gainedd by parallelizzing the generation of partiaal
produccts with their concurrent summations. Inn case of 22
2
multipplications thouugh the otherr multiplier ciircuits achievee
almostt same speed yyet the Vedic m
multiplier is alm
most two times
faster than the otherrs. Due to sim
mplicity, delayy of 22 Vedicc
multipplier is reportedd as 230 ps onlly. However onn increasing biit
lengthh, delay of 444 (88) Vedic multiplier is 888% (82%) and
d
wn by carry-savve and Bit array
y
69% (551%) of the tootal delay show
multipplier circuit undder same bit lenngth conditionn.
Hence we also comparee the energy--delay producct
(EDP)) which shouldd combine a m
measure of peerformance and
d
energyy is more rellevant metric than Power-delay productt.
Table 2 shows that tthough the eneergy-delay prooduct of Vedicc,
2
carry save and Bit-aarray multiplieers are almostt same for 22
4
operattion yet deviattions occur in 44 and 88 operation. 44
(88) Vedic multipplier achieves almost 11.11% (11.3 %)),
% (33.4 %) andd 20% (28.6%)) of total EDP
P shown by Biit
16.9%
array, Wallace tree and carry save multipliers. From Table 2,
2
mmarized, thee power delay
y
the foollowing resullts can be sum
producct (PDP) of tthe 8x8 conveentional Vedicc multiplier is
worse than the PDP of the fully addiabatic Vedic 8x8 multipliers
d
due too the negligiblee amount of noon-adiabatic looss of proposed
L logic. Thouggh adiabatic coounterpart is liittle bit slower
EEAL
yet duue to very low ppower consum
mption, power ddelay product is
reduceed significantlly. 8x8 (2x2) adiabatic Veedic multiplier
saves almost 16.5% (57.1%) of tootal energy consumed by thee
convenntional 8x8 (2xx2) Vedic multtiplier.
Tablle 1. Power dissip ation, delay and E
Energy-delay of CM
MOS multiplier
circuits with varyying bit lengths forr 180nm CMOS T
Technology

Bit L
Length

Power consumption (W)) of different type off Multiplier units

oof
Conveentional
Vedic

Carry-save

Bit-array

222

27

81

92

185

444

104

427

449

389

888

892

2060

2090

2172

Figure 7. Outpu
ut waveform of 8
8 Adiabatic Vedicc Multiplier

Delay (ns) of different type of Multipllier units

Bit L
Length

T
Table 1 showss that Vedic multiplier
m
sho
ows least pow
wer
consuumption comp
pared to other optimized mu
ultiplier circuitts.
Sincee greater num
mbers of addeer cells are used
u
for larger
multiipliers, the pow
wer savings forr smaller operaand sizes can be
b
directtly extrapolateed to higher op
perand multipllier modules. In
I
10MH
Hz 22, 44 an
nd 88 Vedic multiplier consume only 33%
%,
30% and 41% of th
he total powerr consumed by
y carry save an
nd
vely. Table 1 also shows th
hat
Wallaace tree multiplier respectiv

Wallace Tree [5]

Multtiplier

oof
Conveentional
Multtiplier

Vedic

Carry-save

Bit-array

222

0.23

0.46

0.45

444

0.58

0.66

0.84

888

1.38

1.68

2.69

Wallace Tree
0.42
0.73
1.53

806
REFERENCES
Energy-Delay Product (10-25 Js) comparison of different type
Bit Length

[1]

of Multiplier units

of
Conventional
Multiplier

Vedic

Carry-save

Bit-array

22

0.14

0.17

0.17

44

3.50

18.80

30.50

88

169.80

589.60

1505.10

Wallace Tree
3.20

508.40

Conventional Vedic

Adiabatic Vedic

Savings (%)

22

27

9.64

64.3

44

104

45.76

56.0

88

892

526.28

41

Adiabatic Vedic

Savings (%)

22

0.23

0.25

-8.0

44

0.58

0.67

-15.5

88

1.38

1.87

-35.5

Multiplier

22

[5]

[7]
[8]

[9]

Propagation Delay (ns) of Multiplier

Conventional Vedic

Bit Length of

[4]

[6]

Power consumption (W) of Multiplier

Bit Length of
Multiplier

Multiplier

[3]

20.70

Table 2. Performance comparison of conventional and adiabatic Vedic

multiplier circuits with varying bit lengths at 10 MHz for 180nm Technology

Bit Length of

[2]

[10]
[11]
[12]

Energy-Delay Product (10-25 Js) comparison of Multiplier

[13]
Conventional Vedic

Adiabatic Vedic

Savings (%)

0.14

.06

57.1

[14]
[15]

IV.CONCLUSION
An energy efficient new adiabatic multiplier structure
based on Urdhva Tiryakbhyam sutra of Vedic mathematics has
been proposed using EEAL style. On basis of Cadence spectre
simulations, it can be concluded that this Vedic multiplier is
more efficient than array multiplier, Booth
multiplier and
Wallace-Tree multiplier, in terms of timing efficiency and
speed. The speed improvements are gained by parallelizing the
generation of partial products with their concurrent
summations. It is also shown that energy efficiency can be
enhanced significantly in low frequency domain using the
newly proposed adiabatic approach.

[16]

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