Professional Documents
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Add Add
Data
Register #
PC Address Instruction Registers ALU Address
Register #
Data
Instruction
memory
memory Register #
Data
Processor Architecture Pipelining Pipeline Hazards
M
u
x
Add M
Add
u
x
ALU operation
Data
MemWrite
Register #
PC Address Instruction Registers ALU Address
Register # M Zero
u Data
Instruction
x memory
memory Register # RegWrite
Data
MemRead
Control
Processor Architecture Pipelining Pipeline Hazards
1
10−12 s = 1ps, one picosecond
Processor Architecture Pipelining Pipeline Hazards
6 PM 7 8 9 10 11 12 1 2 AM
Time
Total of 2 × 20 = 40 hours?
Task
order
Time
Processor Architecture Pipelining Pipeline Hazards
Task
order
The Laundry Room Analogy
A
C
If Dit takes 2 hours to wash, dry, fold and store one set of
clothes, how long will it take for 20 sets?
6 PM 7 8 9 10 11 12 1 2 AM
Time
Task
order
A
Pipeline Overheads
lw $2, 200($0) 800 ps
Instruction
fetch
Reg ALU
Data
access
Reg
Instruction
lw $3, 300($0) 800 ps fetch
800 ps
Program
execution 200 400 600 800 1000 1200 1400
Time
order
(in instructions)
Instruction Data
lw $1, 100($0) fetch
Reg ALU
access
Reg
Instruction Data
lw $2, 200($0) 200 ps fetch
Reg ALU
access
Reg
Instruction Data
lw $3, 300($0) 200 ps fetch
Reg ALU
access
Reg
Obstacles to Pipelining
Structural Hazards
Data Hazards
EX Forwarding
Wasted cycles waiting for previous instruction to complete
Compiler could fill bubbles with independent instructions
Or even the hardware – out-of-order execution
Hard to find useful instructions; happens too often!
Better solution – forward result from EX output
Extra hardware to take result directly from ALU output
Program
execution 200 400 600 800 1000
order Time
(in instructions)
No stalls required
Processor Architecture Pipelining Pipeline Hazards
MEM Forwarding
Reordering Instructions
Branch/Control Hazards
Branch Prediction
Reading Material