SN75176A

DIFFERENTIAL BUS TRANSCEIVER

SLLS100A – JUNE 1984 – REVISED MAY 1995

• Bidirectional Transceiver D OR P PACKAGE

• Meets or Exceeds the Requirements of

(TOP VIEW)

ANSI Standards EIA/TIA-422-B and ITU R 1 8 VCC

Recommendation V.11 RE B
2 7
• Designed for Multipoint Transmission on DE 3 6 A
Long Bus Lines in Noisy Environments D 4 5 GND
• 3-State Driver and Receiver Outputs
• Individual Driver and Receiver Enables logic symbol†
• Wide Positive and Negative Input /Output
Bus Voltage Ranges 3
DE EN1
• Driver Output Capability . . . ± 60 mA Max RE
2
EN2
• Thermal-Shutdown Protection
•
6
Driver Positive- and Negative-Current 4 1 A
D 7
Limiting 1 B

• Receiver Input Impedance . . . 12 kΩ Min

•
1
Receiver Input Sensitivity . . . ± 200 mV R 2

• Receiver Input Hysteresis . . . 50 mV Typ

• Operates From Single 5-V Supply † This symbol is in accordance with ANSI/IEEE Std 91-1984

• Low Power Requirements and IEC Publication 617-12.

logic diagram (positive logic)

description
3
DE
The SN75176A differential bus transceiver is a 4
monolithic integrated circuit designed for D
bidirectional data communication on multipoint 2
RE
bus-transmission lines. It is designed for balanced 6
1 A
transmission lines and meets ANSI Standard R 7 Bus
B
EIA/TIA-422-B and ITU Recommendation V.11.
The SN75176A combines a 3-state differential line driver and a differential input line receiver, both of which
operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables,
respectively, that can be externally connected together to function as a direction control. The driver differential
outputs and the receiver differential inputs are connected internally to form differential input /output (I/O) bus
ports that are designed to offer minimum loading to the bus whenever the driver is disabled or VCC = 0. These
ports feature wide positive and negative common-mode voltage ranges making the device suitable for party-line
applications.
Function Tables

DRIVER RECEIVER
INPUT ENABLE OUTPUTS DIFFERENTIAL INPUTS ENABLE OUTPUT
D DE A B A–B RE R
H H H L VID ≥ 0.2 V L H
L H L H – 0.2 V < VID < 0.2 V L ?
X L Z Z VID ≤ – 0.2 V L L
X H Z
Open L ?
H = high level, L = low level, ? = indeterminate, X = irrelevant, Z = high impedance (off)

PRODUCTION DATA information is current as of publication date. Copyright  1995, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1

SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995

description (continued)
The driver is designed to handle loads up to 60 mA of sink or source current. The driver features positive- and
negative-current limiting and thermal shutdown for protection from line fault conditions. Thermal shutdown is
designed to occur at a junction temperature of approximately 150°C. The receiver features a minimum input
impedance of 12 kΩ, an input sensitivity of ± 200 mV, and a typical input hysteresis of 50 mV.
The SN75176A can be used in transmission-line applications employing the SN75172 and SN75174 quadruple
differential line drivers and SN75173 and SN75175 quadruple differential line receivers.
The SN75176A is characterized for operation from 0°C to 70°C.

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF A AND B I/O PORTS TYPICAL OF RECEIVER OUTPUT

VCC VCC VCC

85 Ω
R(eq) NOM

16.8 kΩ 960 Ω
Input NOM NOM

960 Ω
NOM Output

GND
Driver input: R(eq) = 3 kΩ NOM Input/Output
Enable inputs: R(eq) = 8 kΩ NOM Port
R(eq) = equivalent resistor

2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 10 V to 15 V
Enable input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.

DISSIPATION RATING TABLE

TA ≤ 25
25°C
C DERATING FACTOR TA = 70_C TA = 105_C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING
D 725 mW 5.8 mW/°C 464 mW 261 mW
P 1100 mW 8.8 mW/°C 704 mW 396 mW

recommended operating conditions

MIN TYP MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
Voltage at any bus terminal (separately or common mode), VI or VIC –7 12 V
High-level input voltage, VIH D, DE, and RE 2 V
Low-level input voltage, VIL D, DE, and RE 0.8 V
Differential input voltage, VID (see Note 2) ± 12 V
Driver – 60 mA
High-level output current,
current IOH
Receiver – 400 µA
Driver 60
Low-level output current,
current IOL mA
Receiver 8
Operating free-air temperature, TA 0 70 °C
NOTE 2: Differential-input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3

SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995

DRIVER SECTION

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VIK Input clamp voltage II = – 18 mA – 1.5 V
VIH = 2 V, VIL = 0.8 V,
VOH High-level output voltage 37
3.7 V
IOH = – 33 mA
VIH = 2 V, VIL = 0.8 V,
VOL Low-level output voltage 11
1.1 V
IOH = 33 mA
|VOD1| Differential output voltage IO = 0 2VOD2 V
RL = 100 Ω, See Figure 1 2 2.7
|VOD2| Differential output voltage V
RL = 54 Ω, See Figure 1 1.5 2.4
Change in magnitude of differential output
∆|VOD| ± 0.2
02 V
voltage‡
VOC Common-mode output voltage§ RL = 54 Ω or 100 Ω, See Figure 1 3 V
Change in magnitude of common
common-mode
mode
∆|VOC| ± 0.2
02 V
output voltage‡
Output disabled, VO = 12 V 1
IO Output current mA
See Note 3 VO = – 7 V – 0.8
IIH High-level input current VI = 2.4 V 20 µA
IIL Low-level input current VI = 0.4 V – 400 µA
VO = – 7 V – 250
IOS Short-circuit
Sh i i output
p current VO = VCC 250 mA
A
VO = 12 V 500
Outputs enabled 35 50
ICC Supply current (total package) No load mA
Outputs disabled 26 40
† All typical values are at VCC = 5 V and TA = 25°C.
‡ ∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC respectively, that occur when the input is changed from a high level to a low
level.
§ In ANSI Standard EIA/TIA-422-B, VOC, which is the average of the two output voltages with respect to GND, is called output offset voltage, VOS.
NOTE 3: This applies for both power on and off; refer to ANSI Standard EIA/TIA-422-B for exact conditions.

switching characteristics, VCC = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(OD) Differential-output delay time 40 60 ns
RL = 60 Ω
Ω, See Figure 3
tt(OD) Differential-output transition time 65 95 ns
tPZH Output enable time to high level RL = 110 Ω, See Figure 4 55 90 ns
tPZL Output enable time to low level RL = 110 Ω, See Figure 5 30 50 ns
tPHZ Output disable time from high level RL = 110 Ω, See Figure 4 85 130 ns
tPLZ Output disable time from low level RL = 110 Ω, See Figure 5 20 40 ns

2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995

RECEIVER SECTION

electrical characteristics over recommended ranges of common-mode input voltage, supply

voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VIT + Positive-going input threshold voltage VO = 2.7 V, IO = – 0.4 mA 0.2 V
VIT– Negative-going input threshold voltage VO = 0.5 V, IO = 8 mA – 0.2‡ V
Vhys Input hysteresis voltage (VIT + – VIT –) 50 mV
VIK Enable clamp voltage II = – 18 mA – 1.5 V
VID = 200 mV, IOH = – 400 µA,
VOH High-level output voltage 27
2.7 V
See Figure 2
VID = – 200 mV, IOL = 8 mA,
VOL Low-level output voltage 0 45
0.45 V
See Figure 2
IOZ High-impedance-state output current VO = 0.4 V to 2.4 V ± 20 µA
Other input = 0 V, VI = 12 V 1
II Line input current mA
See Note 3 VI = – 7 V – 0.8
IIH High-level enable input current VIH = 2.7 V 20 µA
IIL Low-level enable input current VIL = 0.4 V – 100 µA
ri Input resistance 12 kΩ
IOS Short-circuit output current – 15 – 85 mA
Outputs enabled 35 50
ICC Supply current (total package) No load mA
Outputs disabled 26 40
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 3: This applies for both power on and power off. Refer to ANSI Standard EIA/TIA-422-B for exact conditions.

switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output 21 35 ns
VID = – 1
1.5
5 V to 1
1.5
5VV, See Figure 6
tPHL Propagation delay time, high-to-low-level output 23 35 ns
tPZH Output enable time to high level 10 30 ns
See Figure 7
tPZL Output enable time to low level 12 30 ns
tPHZ Output disable time from high level 20 35 ns
See Figure 7
tPLZ Output disable time from low level 17 25 ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–5

SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995

PARAMETER MEASUREMENT INFORMATION

RL
2 VID
VOD2
VOH
RL
VOC
2 +IOL – IOH
0V VOL

Figure 1. Driver VOD and VOC Figure 2. Receiver VOH and VOL

3V
Input 1.5 V 1.5 V
CL = 50 pF
0V
RL = 60 Ω (see Note B)
Generator td(OD) td(OD)
50 Ω Output
(see Note A)
≈ 2.5 V
90%
Output 50% 50%
3V 10% 10%
CL ≈ – 2.5 V
tt(OD) tt(OD)
TEST CIRCUIT VOLTAGE WAVEFORMS

Figure 3. Driver Test Circuit and Voltage Waveforms

Output 3V
S1 Input 1.5 V 1.5 V
0 or 3 V 0V
tPZH 0.5 V
CL = 50 pF RL = 110 Ω VOH
Generator (see Note B)
(see Note A) 50 Ω Output 2.3 V
tPHZ Voff ≈ 0 V

TEST CIRCUIT VOLTAGE WAVEFORMS

Figure 4. Driver Test Circuit and Voltage Waveforms

5V
3V
Input 1.5 V 1.5 V
RL = 110 Ω
S1 0V
Output
3 V or 0 tPZL
tPLZ
CL = 50 pF
(see Note B) 5V
Generator
50 Ω 2.3 V 0.5 V
(see Note A) Output
VOL

TEST CIRCUIT VOLTAGE WAVEFORMS

Figure 5. Driver Test Circuit and Voltage Waveforms

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.

2–6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995

PARAMETER MEASUREMENT INFORMATION

3V
Output Input 1.5 V 1.5 V
Generator
(see Note A) 51 Ω
0V
1.5 V
CL = 15 pF tPLH tPHL
(see Note B) VOH
0V
Output 1.3 V 1.3 V
VOL
TEST CIRCUIT VOLTAGE WAVEFORMS

Figure 6. Receiver Test Circuit and Voltage Waveforms

1.5 V S1

2 kΩ S2
–1.5 V 5V

CL = 15 pF 5 kΩ 1N916 or Equivalent
(see Note B)

Generator
(see Note A) 50 Ω

S3

TEST CIRCUIT
3V 3V
Input 1.5 V Input 1.5 V
S1 to 1.5 V S1 to –1.5 V
0 V S2 Open 0 V S2 Closed
tPZH S3 Closed S3 Open
tPZL
VOH
1.5 V ≈ 4.5 V
Output
Output 1.5 V
0V
VOL

3V 3V
S1 to 1.5 V S1 to – 1.5 V
Input 1.5 V S2 Closed Input 1.5 V S2 Closed
S3 Closed S3 Closed
0V 0V
tPHZ
tPLZ
VOH ≈ 1.3 V
0.5 V
Output
Output 0.5 V
≈ 1.3 V VOL

VOLTAGE WAVEFORMS

Figure 7. Receiver Test Circuit and Voltage Waveforms

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–7

SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995

TYPICAL CHARACTERISTICS
DRIVER DRIVER
HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
vs vs
HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
5 5
VCC = 5 V VCC = 5 V
4.5 TA = 25°C 4.5 TA = 25°C
VOH – High-Level Output Voltage – V

VOL – Low-Level Output Voltage – V

4 4

3.5 3.5

3 3

2.5 2.5

2 2

1.5 1.5
VOH

1 1

0.5 0.5

0 0
0 – 20 – 40 – 60 – 80 – 100 – 120 0 20 40 60 80 100 120
IOH – High-Level Output Current – mA IOL – Low-Level Output Current – mA

Figure 8 Figure 9

DRIVER RECEIVER
DIFFERENTIAL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
vs vs
OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
4 0.6
VCC = 5 V VCC = 5 V
3.5 TA = 25°C TA = 25°C
VOD – Differential Output Voltage – V

VOL – Low-Level Output Voltage – V

0.5
3

0.4
2.5

2 0.3

1.5

ÁÁ
0.2

ÁÁ
1
VOD

VOL

ÁÁ
0.1
0.5

0 0
0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30
IO – Output Current – mA IOL – Low Level Output Current – mA

Figure 10 Figure 11

2–8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995

TYPICAL CHARACTERISTICS
RECEIVER RECEIVER
LOW-LEVEL OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
FREE-AIR TEMPERATURE ENABLE VOLTAGE
0.5 5
VCC = 5 V VID = 0.2 V
VID = – 0.2 V Load = 8 kΩ to GND
IOL = 8 mA
VOL – Low-Levcel Output Voltage – V

TA = 25°C
0.4 4 VCC = 5.25 V

O – Output Voltage – V
0.3 3 VCC = 5 V VCC = 4.75 V

0.2 2

ÁÁ ÁÁ
ÁÁ
VO
V
ÁÁ
0.1 1
VOL

0 0
0 10 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 3
TA – Free-Air Temperature – °C VI – Enable Voltage – V

Figure 12 Figure 13

RECEIVER
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
6
VCC = 5.25 V VID = 0.2 V
Load = 1 kΩ to VCC
5 TA = 25°C
VCC = 4.75 V
O – Output Voltage – V

VCC = 5 V
4

ÁÁ
ÁÁ
2
VO
V

0
0 0.5 1 1.5 2 2.5 3
VI – Enable Voltage – V

Figure 14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–9

SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995

APPLICATION INFORMATION
SN65176A SN65176A

RT RT

Up to 32
Transceivers

Figure 15. Typical Application Circuit

NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept
as short as possible.

2–10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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Copyright  1995, Texas Instruments Incorporated