SH2 DMAC and Interrupt

Course Introduction
Purpose:
This course provides an overview of the Direct Memory Access
Controller and the Interrupt Controller on the SH-2 and SH-2A
families of 32-bit RISC microcontrollers, which are members of the
SuperH series
Objectives:
Gain a basic knowledge of the features and operation of the direct
memory access controller
Learn about the features and operation of the interrupt controller
Content:
Learning Time:
27 pages
4 questions
20 minutes
1
2008, Renesas Technology America, Inc., All Rights Reserved
SuperH Peripheral Functions
Microcontrollers for embedded
system applications require

extensive on-chip peripherals to
Minimize system chip count
Reduce overall system cost
Facilitate small system size, etc.
Built-in peripheral functions

must
Provide required capabilities

Deliver needed performance levels
Offer design flexibility
Maintain a basic commonality
within product family, if possible
SH7145 SuperH Series Microcontroller

SH-2 SuperH
32-bit RISC CPU
Flash
RAM
Multi-function Timer
Pulse Unit
Data Transfer
Controller
Compare-Match
Timer
Bus State
Controller
Watchdog Timer
Direct Memory
Access Controller
A/D Converter
Interrupt Controller
High-performance
User Debug Interface
User Break
Controller
Advanced User
Debugger
Serial Communication
Interface
Bus
Interface
Offer an acceptable cost-benefit

compromise, etc.
I/O
Ports
Clock Pulse
Generator
Direct Memory Access Controller
Performs data transfers
External
Memory
between:
External devices with DACK

External memory
On-chip memory
Memory-mapped external I/O
On-chip peripheral modules
DMAC
Frees the CPU from
handling these data

transfers
On-chip
Peripherals
So CPU resources can be

focused on computational
operations
SuperH
CPU
3
External
Devices
with DACK
Memorymapped I/O
On-chip
Memory
Microcontroller
DMAC Features
4 or 8 channels 2 or 4 with external triggering

4GB of address space
Transfers of up to 16,777,216 units
Byte, word, longword, and 16-byte data transfer units
Dual-and single-address modes
Processing of transfer requests from
External devices
On-chip peripherals
SCIF x 8 sources
IIC3 x 2 sources (supported by SH-2A only)
ADC x 2 sources
MTU2 x 5 sources
CMT x 2 sources (supported by SH-2A only)
Software (auto request)
Cycle-steal and burst-bus modes

Fixed and round-robin priority schemes
Interrupts after half or full data transfer
4
Dual-Address Mode
Both source and destination are accessed by internal or external

addresses
Two bus cycles are required for data transfer

First bus cycle
Second bus cycle
5
Single-Address Mode
Both source and destination are external

devices
One source is accessed by the DACK signal

and the other by the address
Transfer can be performed in one cycle

MCU
6
Supported Data Transfers

DMAC Address Mode vs. Transfer Destination
Notes: Dual = Dual-address mode; Single = Single address mode

A 16-byte transfer is available only for on-chip peripherals that support longword access.
7
PROPERTIES
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Channel Priority

When more than one DMAC channel is triggered, channelpriority modes determine the order of transfers.
DMAC has two channel priority modes:
Fixed
The priority among channels remains fixed
Two schemes are available:
CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
Round robin
Priority changes after each unit is transferred
Channel of just-completed transfer moves to the position of lowest priority
Priority after reset:
9
Bus Modes
Two bus modes direct the use of the microcontrollers buses
Cycle-steal mode
Normal
Upon completion of a transfer, the bus is given to another bus master
(CPU, external bus request, etc.)
Bus released for 1 cycle
Intermittent (SH-2A series devices only)

Upon completion of a transfer, the bus is given to another bus master
(CPU, external bus request, etc.)
Bus released for 16 or 64 cycles
DMAC occupies the bus less frequently
Burst mode
Fastest way to transfer data
DMAC doesnt release the bus until all requested transfers have been
completed
10
Interrupt Controller
Controls interrupt
requests to the CPU
Ascertains the priority of

interrupt sources
Provides key features

and functions
16 levels of priority
NMI noise-canceller
function
/IRQOUT pin, which can
signal the occurrence of an
interrupt
Register bank interaction
(in SH-2A devices) to save
and restore CPU registers
at high speed
Interrupt
Source 1
Interrupt
Source 2
Interrupt
Source 3
INTC
Interrupt
Source 4
. .
11
Interrupt
Source n
CPU
Exceptions and Interrupts
Exceptions are unusual and

unexpected occurrences
Time and location generally

cannot be predicted
Example is an Illegal instruction
Exception sources include:

Resets
Address errors
Illegal instructions
TRAPA instructions
Hardware offers methods to

react, recover, and restart
Interrupts are unusual
occurrences that are expected

to occur
Example is data-byte reception by
a serial communications channel
Interrupt sources include:

NMI
User Break
External IRQ
On-chip peripherals
CPU can launch a routine to

handle the event
Interrupt Acceptance & Handling

INTC accepts interrupt requests according to priority

If interrupt request is accepted, interrupt handling process
begins:
31
/IRQOUT driven low

Status Register pushed on stack and
interrupt priority adjusted in CPU status
register
Program counter pushed onto stack
/IRQOUT driven high
Address of interrupt service routine
read from vector table
Interrupt service routine executed
High Address
Stack
grows
down
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
Stack
Low Address
R13
R14
R15
31
Status Register
MQI3I2I1I0ST
Global Base Register
GBR
Vector Base Register
VBR
Jump Table Base Register
TBR
MAC Registers
MAC H
MAC L
Procedure Register
PR
Program Counter
PC
Interrupt Handling Flow
14
PROPERTIES
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SH-2 Series Interrupt Controller
16
SH-2 Interrupt Response Time

Number of States
______________________________________________
NMI, Peripheral Module
IRQ
Remarks
_____________________________________________________________________________________________________________________
DMAC/DTC active judgment
0 or 1
1 state required for interrupt signals for which

DMAC/DTC activation is possible
_____________________________________________________________________________________________________________________
Compare identified interrupt
2
3
priority with SR mask level
_____________________________________________________________________________________________________________________
Wait for completion of
sequence currently being
executed by CPU
X ( 0)
The longest sequence is for interrupt or

address-error processing (X = 4 + m1 + M2 +
m3 + m4). If an interrupt-masking instruction
follows, the time may be longer
_____________________________________________________________________________________________________________________
Time from start of interrupt
5 + m1 + m2 + m3
exception processing until
start of fetch of exception
service routines first instruction
_____________________________________________________________________________________________________________________
Interrupt total:
7 + m1 + m2 + m3
9 + m1 + m3
_________________________________________________________________________________________
Response, minimum:
10
12
0.25s to 0.3s
_________________________________________________________________________________________
Time, maximum:
12 + 2 (m1 + m2 + m3) + m4
13 + 2 (m1 + m2 + m3) + m4
0.48s @ 40MHz
_____________________________________________________________________________________________________________________
Note: m1 m4 are the number of states needed for the following memory accesses:
m1: SR save (longword); m2: PC save (longword write); m3: vector address read (longword write); m4: fetch first ISR instruction
17
PROPERTIES
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SH-2A Interrupt Controller
19
SH-2A Register Banks
SH-2A CPU has

15 register banks, one for
each interrupt priority
Register banks save and

restore CPU register
contents during interrupt
handling
When bank is full and

overflows, the stack can
be used
SH-2A CPU can generate

bank overflow and
underflow exceptions
20
SH-2A Interrupt Latency
21
SH-2A Interrupt Response Times
22
Vector Table
Complete table contains entries for

Exception processing
Interrupt processing
Entries are always 32 bits wide

and longword aligned
Vector table entries point to

functions with no calling
parameters and no return values
Vector base register provides a

location base for the vector table
that helps improve
Interrupt processing speed in ROM-less
systems
Memory access in ROM monitor or
bootloader applications
Interrupt
source
Vector
table
address
Interrupt Source
Vector Vector
Vector
Table
Addressoffset
Offset
0x00000100-0x00000103
IRQ0
64
0x00000104-0x00000107
IRQ1
65
0x00000108-0x0000010B
IRQ2
66
0x0000010C-0x0000010F
IRQ3
67
0x00000110-0x00000113
IRQ4
68
0x00000114-0x00000117
IRQ5
69
0x00000118-0x0000011B
IRQ6
70
0x0000011C-0x0000011F
IRQ7
71
0x00000120-0x00000123
On-chip peripheral modules 72
...
...
0x000003FC-0x000003FF
255
Vector tables can be

0x400 bytes long!
Exception Processing - Resets
CPU reads initial values for PC

and SP from exception vector table
Vector base register is initialized

to 0x00000000
Interrupt mask bits of the SR are set to maximum

(all interrupts masked)
Program execution begins at PC value read from

exception vector table
Two reset types are supported:

Power-on reset
Reset vector from 0x00000000
SP from 0x00000004
Manual reset (/RES=1, /MRES=0)

Reset vector from 0x00000008
SP from 0x0000000C
Exception Processing-Instructions
Exceptions can be triggered by instructions

TRAPA
General illegal (unimplemented) op-code
Illegal slots
General illegal instruction
Instruction that rewrites the PC
PROPERTIES
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Course Summary
Direct memory access controller

Interrupt controller
27

SH2 DMAC and Interrupt

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Course Introduction

SuperH Peripheral Functions

Microcontrollers for embedded

system applications require

Built-in peripheral functions

Provide required capabilities

SH7145 SuperH Series Microcontroller

Offer an acceptable cost-benefit

2008, Renesas Technology America, Inc., All Rights Reserved

Direct Memory Access Controller

Performs data transfers

External devices with DACK

Frees the CPU from

handling these data

So CPU resources can be

4 or 8 channels 2 or 4 with external triggering

Software (auto request)

Cycle-steal and burst-bus modes

Both source and destination are accessed by internal or external

Two bus cycles are required for data transfer

Second bus cycle

Both source and destination are external

One source is accessed by the DACK signal

Transfer can be performed in one cycle

Supported Data Transfers

Notes: Dual = Dual-address mode; Single = Single address mode

Goes to Next Slide

Intermittent (SH-2A series devices only)

Ascertains the priority of

Provides key features

Exceptions and Interrupts

Exceptions are unusual and

Time and location generally

Exception sources include:

Hardware offers methods to

Interrupts are unusual

occurrences that are expected

Interrupt sources include:

CPU can launch a routine to

2008, Renesas Technology America, Inc., All Rights Reserved

Interrupt Acceptance & Handling

INTC accepts interrupt requests according to priority

/IRQOUT driven low

2008, Renesas Technology America, Inc., All Rights Reserved

Interrupt Handling Flow

Goes to Next Slide

SH-2 Series Interrupt Controller

SH-2 Interrupt Response Time

1 state required for interrupt signals for which

The longest sequence is for interrupt or

Goes to Next Slide

SH-2A Interrupt Controller

SH-2A Register Banks

SH-2A CPU has

Register banks save and

When bank is full and

SH-2A CPU can generate

SH-2A Interrupt Latency

SH-2A Interrupt Response Times

Complete table contains entries for

Entries are always 32 bits wide

Vector table entries point to

Vector base register provides a

Vector tables can be