05 Content

vii
TABLE OF CONTENTS
CHAPTER
TITLE
NO.
ABSTRACT
PAGE NO.
iii
LIST OF TABLES
xviii
LIST OF FIGURES
xxi
NOMENCLATURE
xli
INTRODUCTION
1.1
GENERAL
1.2
CONTROL OF DC-DC CONVERTER

WITH RHP ZERO
1.3
SOFT SWITCHED CONVERTERS
1.4
CONTROL OF QUASI-RESONANT
CONVERTERS
12
1.4.1 Analog Resonant Controller
13
1.4.2 Fuzzy Logic Controller
15
1.4.3 Model Based Controllers using

Neural Networks and Fuzzy Logic
17
1.5
OBJECTIVES OF THE THESIS
21
1.6
ORGANISATION OF THE THESIS
22
viii
CHAPTER
TITLE
NO.
PAGE NO.
DESIGN OF LINEAR AND NONLINEAR

CONTROLLERS
CONTROL
OF
FOR
A
VOLTAGE
DC-DC
BOOST
CONVERTER WITH RHP ZERO
27
2.1.
INTRODUCTION
27
2.2.
ANALYSIS OF DC-DC BOOST

CONVERTER
2.3
27
2.2.1 Stage 1 (0 t
D Ts )
29
2.2.2 Stage 2 (D Ts
29
Ts )
CLOSED-LOOP CONTROL OF
DC-DC BOOST CONVERTER
33
2.3.1 Dynamic Behavior of Boost

Converter
36
2.3.2 Design of Conventional PID

Controllers
39
2.3.2.1 Ziegler-Nichols (Z-N)

Tuning by Frequency
Response Method
2.3.2.2 Luyben Method
40
43
2.3.2.3 Internal Model Control

(IMC) Method
2.4
45
2.3.2.4 Synthesis Method
50
2.3.3 Closed-loop Simulation Results
52
DESIGN OF CURRENT MODE

CONTROL USING SMC/FSMC
61
ix
CHAPTER
TITLE
NO.
2.5
DERIVATION OF SLIDING MODE

CONTROL (SMC) LAW
2.6
PAGE NO.
61
ZIEGLER-NICHOLS TUNING BY
PROCESS REACTION CURVE
METHOD
2.7
CLOSED-LOOP SIMULATION
IMPLEMENTING SMC
2.8
2.10
68
DERIVATION OF FUZZY SLIDING

MODE CONTROL LAW
2.9
66
75
IMPLEMENTING FSMC
79
HARDWARE IMPLEMENTATION
85
2.10.1 Driver Circuit
86
2.10.2 Overload Protection Circuit
86
2.10.3 Signal Conditioning Circuit
87
2.10.4 Pulse Generation
87
2.10.5 Voltage Control of Boost Converter

implementing SMC
90
2.10.6 Voltage Control of Boost Converter

implementing FSMC
93
2.11
EFFICIENCY OF BOOST CONVERTER
97
2.12
CONCLUSION
98
CHAPTER
TITLE
NO.
PAGE NO.
ANALYSIS, DESIGN AND CONTROL OF

ZVS QUASI - RESONANT CONVERTERS
USING
AN
ANALOG
RESONANT
CONTROLLER
100
3.1
INTRODUCTION
100
3.2
ANALYSIS OF BUCK-BOOST
ZVS-QRC
101
3.2.1 Linear Capacitor Charging Stage

102
(t0 t < t1)

3.2.2 Resonant Inductor Discharging
Stage (t1
103
t < t2)
3.2.3 Holding Stage (t2
t < t3)
104
3.2.4 Resonant Inductor Charging Stage

(t3
t< t4)
105
3.2.5 Linear Inductor Charging Stage

(t4 t< t5)
106
3.2.6 Constant Current Stage (t5 t<t6)
106
3.3
STEADY STATE CHARACTERISTICS
107
3.4
DESIGN PROCEDURE AND
3.5
SIMULATION RESULTS
111
3.4.1 Simulation Results
113
CLOSED-LOOP OPERATION OF
BUCK-BOOST ZVS-QRC
115
3.5.1 Analog Resonant Controller
116
xi
CHAPTER
TITLE
NO.
PAGE NO.
3.5.1.1 Error Amplifier (E/A) and

Voltage Controlled
Oscillator (VCO)
117
3.5.1.2 One Shot Pulse Generator
119
3.5.1.3 Steering Logic and Output

Drivers
121
3.5.1.4 Under Voltage Lockout

(UVLO), Fault Comparator
and Soft Reference
Generator
122
3.5.2 Implementation of Proto Type

Buck-Boost ZVS-QRC
125
3.5.2.1 Open-Loop Experimental

Results
125
3.5.2.2 Closed-Loop Experimental

Results
3.6
EFFICIENCY OF BUCK-BOOST
ZVS-QRC
3.7
3.8
134
ANALYSIS OF MULTI-OUTPUT
FLYBACK ZVS-QRC
136
139
3.8.1 Control Characteristics

3.9
128
142

SIMULATION OF MULTI-OUTPUT
FLYBACK ZVS-QRC
143
3.9.1 Simulation Results
145
xii
CHAPTER
TITLE
NO.
3.10
PAGE NO.
IMPLEMENTATION OF PROTOTYPE
MULTI-OUTPUT FLYBACK
3.11
ZVS-QRC
147
ANALYSIS OF PUSH-PULL ZVS-QRC
159
3.11.1 Linear Capacitor Charging

Stage (t0
t < t1)
160

Stage (t1
t < t2)
161

(t2 t < t3)
3.11.4 Constant Current Stage (t3 t< t4)
3.12
3.15
167
SIMULATION RESULTS OF
PUSH-PULL CONVERTER
3.14
164
DESIGN PROCEDURE OF PUSH-PULL

ZVS-QRC
3.13
164
167
PUSH-PULL CONVERTER
170
CONCLUSION
176
SIMPLE FUZZY LOGIC CONTROLLER

FOR VOLTAGE CONTROL OF BUCKBOOST EP-ZCS/ZVS AND ZVS-QRC
178
4.1
INTRODUCTION
178
4.2
ANALYSIS OF HALF-WAVE
BUCK-BOOST EP-ZCS/ZVS-QRC
179
xiii
CHAPTER
TITLE
NO.
PAGE NO.

(t0 t < t1)
181
4.2.2 Resonant Capacitor Charging Stage

(t1 t < t2)
4.2.3 Holding Stage (t2 t < t3)
182
183

Stage (t3 t < t4)
183
4.2.5 Linear Capacitor Discharging Stage

(t4 t < t5)
4.2.6 Freewheeling Stage (t5 t < t6)
4.3
185

OF BUCK-BOOST EP-ZCS/ZVS-QRC
4.4
184
187

SIMULATION OF BUCK-BOOST
EP-ZCS/ZVSQRC
192
4.4.1 Design Example
192
4.4.2 Simulation Results of Buck-Boost

EP-ZCS/ZVS-QRC
4.5
193
CLOSED-LOOP SIMULATION OF
BUCK-BOOST EP-ZCS/ZVS-QRC
196
4.5.1 Design of PI Controller
197
4.5.2 Design of CFLC
200
4.5.2.1 Simulation Results of

CFLC
4.5.3 Design of SFLC
206
209
xiv
CHAPTER
TITLE
NO.
PAGE NO.
4.5.3.1 Stability Analysis of SFLC
211
4.5.3.2 Advantages of SFLC
214
4.5.3.3 Simulation Results of

SFLC
4.6
4.7
215
BUCK-BOOST EP- ZCS / ZVS- QRC
218
4.6.1 Open-loop Operation
219
4.6.2 Closed-loop Operation
222
4.6.3 Closed-loop CFLC Results
222
4.6.4 Closed-loop SFLC Results
223
ANALYSIS OF BUCK-BOOST ZVSQRC
228
4.7.1 Steady-State Characteristics of

Buck-Boost ZVS-QRC
228
4.7.2 Design Procedure of Buck-Boost

ZVS-QRC
4.8
231
DESIGN OF CONTROLLERS FOR

BUCK-BOOST ZVS-QRC
232
4.8.1 Design of PI Controller
232
4.8.2 Design of CFLC
234
4.8.3 Design of SFLC
235
4.9
SIMULATION RESULTS
236
4.10
RESULTS
239
xv
CHAPTER
TITLE
NO.
4.11
PAGE NO.
BUCK-BOOST ZVS-QRC
244
4.11.1 Open-loop Experimental Results
246
4.11.2 Closed-loop Experimental Results

with CFLC
247
4.11.3 Closed-loop Experimental Results

with SFLC
4.12
248
CONCLUSION
MODEL BASED
252
CONTROLLERS
FOR
QUASI-RESONANT CONVERTERS USING

NEURAL NETWORK AND FUZZY LOGIC
253
5.1
INTRODUCTION
253
5.2
MODELING OF MULTI-OUTPUT
FLYBACK ZVS-QRC USING GSSA
TECHNIQUE
254
5.2.1 Linear Capacitor Charging Stage

( t0
255
t < t1 )

Stage ( t1
256
t < t2 )
5.2.3 Holding Stage ( t 2
t < t3 )
256
5.2.4 Resonant Inductor Charging Stage

( t3
t< t 4 )
257
xvi
CHAPTER
TITLE
NO.
PAGE NO.

( t4
5.2.6 Constant Current Stage ( t 5

5.3
257
t< t 5 )
t< t 6 )
258
DYNAMIC MODELS USING

NEURAL NETWORK
261
5.3.1 Forward Model of Multi -output

Flyback ZVS-QRC
261
5.3.1.1 Generation of Training

Data
263
5.3.1.2 Levenberg Marquardt

(LM) Algorithm for
Training Neural Model
5.3.1.3 Forward Model Validation
267
272
5.3.2 Inverse Neural Model of

Multi-output Flyback ZVS-QRC
274
5.3.2.1 Training and Model

Validation of Inverse
Neural Model
5.4
276
DESIGN OF INVERSE NEURAL

CONTROL AND IMC BASED
5.5
NEURAL CONTROL
278
5.4.1 Inverse Neural Control
279
5.4.2 Design of IMC
280
MODELING OF BUCK-BOOST
EP- ZCS/ZVS-QRC
283
xvii
CHAPTER
TITLE
PAGE NO.
5.5.1 Generation of Training Data
283
NO.
5.6
LINEAR MODEL USING RLS

ESTIMATION FOR BUCK-BOOST
EP-ZCS/ZVS-QRC
5.7
285
NONLINEAR MODELING
TECHNIQUES
287
5.7.1 ANFIS Modeling
287
5.7.2 Takagi-Sugeno Model using

G-K Fuzzy Clustering
291
5.7.3 Gustafson-Kessel Clustering

Algorithm
5.8
5.9
294
FUZZY MODEL BASED

CONTROLLER
297
CONCLUSION
300
CONCLUSIONS
301
6.1
GENERAL
301
6.2
SCOPE FOR FUTURE WORK
304
REFERENCES
306
LIST OF PUBLICATIONS
318
VITAE
321
xviii
LIST OF TABLES
TABLE NO.
TITLE
2.1
Design parameters of dc-dc boost converter
2.2
PID controller tuning rules for dc-dc boost

converter.
2.3
57
59
PI controller parameters by process reaction

curve method
2.8
56
Performance indices of Synthesis method for

uncertainty in parameter C
2.7
54
Performance indices of Synthesis method for

uncertainty in parameter L
2.6
51
ISE value comparison for load variation and

supply voltage disturbances
2.5
32
Performance indices for servo response of

dc-dc boost converter
2.4
PAGE NO.
68
System parameters and PI controller values of

68
2.9
Fuzzy rule table for FSMC
77
2.10
Performance indices of boost converter based

on simulation studies
2.11
Effects of RHP zero on change in reference

voltage
2.12
84
85
Performance indices of boost converter based

on experimental studies
97
xix
TABLE NO.
TITLE
PAGE NO.
3.1
Design parameters for buck-boost ZVS-QRC
112
3.2
Design parameters for VCO
119
3.3
Design parameters for one-shot pulse generator
120
3.4
Performance measures of buck-boost ZVS-QRC

at nominal operating condition 12V/1A
4.1
Design parameters for buck-boost EP-ZCS/

ZVS-QRC
4.2
193

buck-boost EP-ZCS/ZVS-QRC
4.3
CFLC
control
rules
for
199
buck-boost
EP-ZCS/ZVS-QRC
4.4
SFLC
control
203
rules
for
buck-boost
EP-ZCS/ZVS-QRC
4.5
134
Performance
214
measures
of
buck-boost
EP-ZCS/ZVS-QRC obtained from simulation

results
4.6
Performance
217
measures
of
buck-boost
EP-ZCS/ZVS-QRC obtained from experimental

results
4.7
227

buck-boost ZVS-QRC
234
4.8
CFLC control rules for buck-boost ZVS-QRC
235
4.9
SFLC control rules for buck-boost ZVS-QRC
236
4.10
Performance
measures
of
buck-boost
ZVS-QRC obtained from simulation results

4.11
Performance
measures
of
244
buck-boost
ZVS-QRC obtained from experimental results
252
xx
TABLE NO.
TITLE
5.1
Design parameters for multi-output flyback
PAGE NO.
ZVS-QRC
259
5.2
Data set for training the forward neural model
264
5.3
Performance measure of neural controllers for

set-point tracking
5.4
Performance index of RLS ,ANFIS and G-K

fuzzy models
5.5
297
Performance comparison of fuzzy controllers

for buck-boost EP-ZCS/ZVS-QRC
6.1
281
299
Comparison of control techniques applied for

QRCs
305
xxi
LIST OF FIGURES
FIGURE
TITLE
NO.
2.1
Circuit diagram of dc-dc boost converter
2.2
Equivalent circuit diagrams of boost converter

(a) Stage 1 and (b) Stage 2.
2.3
28
30
Ideal steady-state waveforms of dc-dc boost

converter
2.4
PAGE NO.
31
Characteristics of voltage conversion ratio M

versus duty ratio D of dc-dc boost converter
with different values of Ro
2.5
33
Closed-loop control of dc-dc boost converter

using small signal models
34
2.6
Open-loop step response of boost converter
38
2.7
Root locus plot of Gol (s)
39
2.8
Frequency response of Gol (s) /K
42
2.9
Closed-loop log modulus curve for dc-dc boost

converter
2.10
The internal model control (IMC) scheme for a

2.11
44
46
The equivalent conventional control of IMC

structure for dc-dc boost converter
47
xxii
FIGURE
TITLE
NO.
PAGE NO.
2.12
Closed-loop response for various values of
2.13
Regulated output voltage for step change in

reference voltage from 21 to 24 V
2.14
53
Deviation in controller output for a step

change in reference voltage from 21 to 24 V
2.15
55
Regulated output voltage for 16% step

increase in supply voltage applied at 0.5 sec
2.17
57
Closed-loop output voltage for uncertainty in

C using Synthesis method
2.19
2.20
2.21(a)
55
Closed-loop output voltage for uncertainty in

L using Synthesis method
2.18
53

decrease in load current applied at 0.5 sec
2.16
49
58
Block diagram of the closed-loop current

mode control of dc-dc boost converter
61
Generation of control signal for SMC
66
Process
reaction
curve
of
dc-dc
boost
converter for 42% step increase in reference

inductor current.
2.21(b)
Process
reaction
67
curve
of
dc-dc
boost
converter for 42% step decrease in reference

inductor current.
2.22
67
Dynamic model of dc-dc boost converter using

SIMULINK software
69
xxiii
FIGURE
TITLE
NO.
2.23
PAGE NO.
SIMULINK model implementing sliding mode

control
2.24
70
Regulated output voltage for reference output

voltage change from 24 to 29 V effected at
0.5 sec and from 29 to 24 V effected at 1 sec
2.25(a)
71
Waveforms of switching pulse and sliding

function ( ) for reference voltage change from
71
24 to 29V
2.25(b)
Waveforms of switching pulse and sliding

function ( ) for reference voltage change from
72
29 to 24 V
2.26
Waveforms of a) regulated output voltage and

b) switching pulse and sliding function ( ) for
20% decrease in load current
2.27
73
Waveforms of a) regulated output voltage and

b) switching pulse and sliding function ( ) for
16% increase in supply voltage
74
2.28 (a)
Membership functions for
75
2.28 (b)
Membership function for gain, M fuzzy
76
2.29
Generation of control signal for FSMC
78
2.30
SIMULINK model implementing fuzzy sliding

mode control
and
79
xxiv
FIGURE
TITLE
NO.
2.31
PAGE NO.
Waveforms of regulated output voltage for

boost converter with FSMC for reference
output voltage change from 24 to 29 V
effected at 0.5 sec and from 29 to 24 V
effected at 1 sec
2.32
Waveforms of M, , Vg and
80
, implementing
FSMC for reference voltage change (a) from

24 to 29 V applied at 0.5 sec and (b) from 29
to 24 V applied at 1 sec.
2.33(a)
Waveform of regulated output voltage for a

20% step decrease in load applied at t=0.5 sec.
2.33(b)
81
82
Waveforms of fuzzy output, sliding surface,

derivative of sliding surface and switching
pulse, implementing FSMC for 20% step
decrease in load current
2.34(a)
83
Waveform of regulated output voltage for a

16% step increase in supply voltage applied at
t=0.5 sec.
2.34(b)
83
Waveforms of fuzzy output, sliding surface,

derivative of sliding surface and switching
pulse, implementing FSMC for 16% step
increase in supply voltage
84
2.35
Power circuit diagram of dc-dc boost converter
86
2.36
Optocoupler and driver circuit
88
2.37
Circuit diagram for overload protection
89
xxv
FIGURE
TITLE
NO.
PAGE NO.
2.38
Signal conditioning circuit
89
2.39
Gating pulse to switch S
90
2.40
Transient response of boost converter
90
2.41
Experimental set-up of dc-dc boost converter
91
2.42
Closed-loop control of dc-dc boost converter
92
2.43(a)
Unregulated output voltage for 20% step

decrease in load current
2.43(b)

decrease in load current with SMC
2.43(c)
95

increase in supply voltage with SMC
2.44(c)
95

2.44(b)
94

decrease in load current with FSMC
2.44(a)
94
96

increase in supply voltage with FSMC
96
2.45
Efficiency of dc-dc boost converter
98
3.1
Circuit diagram of buck-boost ZVS-QRC
102
3.2
Equivalent circuit of buck-boost ZVS-QRC in

six topological stages of a switching cycle
3.3
108
Theoretical resonant waveforms of buck-boost

ZVS-QRC
109
xxvi
FIGURE
TITLE
NO.
3.4
PAGE NO.
Characteristics of voltage conversion ratio M

versus fs / f o of buck-boost ZVS-QRC with
different values of R
3.5
Characteristics of M versus Td3 / Ts of buckboost ZVS-QRC with different values of R
3.6
111
Simulated resonant waveforms of buck-boost

ZVS-QRC
3.7
110
114
Simulated open-loop converter output voltage

and load current of buck-boost ZVS-QRC
115
3.8
Block diagram of closed-loop control system
116
3.9
The internal block diagram of UC 3861
117
3.10
Internal circuit diagram of E /A and VCO
120
3.11
One-shot pulse generation based on Zero

detector input, VCO and RC outputs
3.12
121
Internal circuit diagram of steering logic and

output drivers
122
3.13
Output pulses from UC3861
122
3.14
Internal circuit diagram of UVLO, fault

comparator and soft-reference generator
3.15
123
Output waveforms of UVLO, fault comparator

and soft - reference generator
124
3.16
Experimental setup of buck-boost ZVS-QRC.
126
3.17
Output of VCO and RC timing pin of UC3861
126
xxvii
FIGURE
TITLE
NO.
3.18
PAGE NO.
Main switch pulse Vg1 ( Aout ) and auxiliary

switch pulse Vg2 ( Bout ) generated by UC3861
3.19
Resonant capacitor voltage
vC and main
r
127
switch pulse Vg1

3.20
Resonant inductor current i L and auxiliary

r
switch pulse Vg2

3.21
128
Power circuit for closed-loop control of

buck-boost ZVS-QRC
3.22(a)
127
129
Unregulated output voltage for 30% increase

in load current [Ch1 (5V/div) and Ch2 (100
mV/A) waveforms denote output voltage and
load current, respectively]
3.22(b)
Regulated output voltage for 30% increase in

load current
3.23(a)
131
Regulated output voltage for 30% decrease in

load current
3.24(a)
131
Unregulated output voltage for 30% decrease

in load current
3.23(b)
130
131
Unregulated output voltage for 12% decrease

in supply voltage [Ch1 (1V/div) and Ch2
(2V/div) waveforms denote output voltage and
supply voltage respectively]
132
xxviii
FIGURE
TITLE
NO.
3.24(b)
PAGE NO.
Regulated output voltage for 12% decrease in

supply voltage
3.25(a)
132
Unregulated output voltage for 12% increase

in supply voltage
3.25(b)
133
Regulated output voltage for 12% increase in

supply voltage
133
3.26
Efficiency of buck-boost ZVS-QRC
135
3.27
Circuit diagram
of multi-output
flyback
ZVS-QRC
3.28(a)
137
Equivalent circuit with components in the

secondary side of the transformer referred to
the primary
3.28(b)
Modified circuit of the multi-output flyback

ZVS-QRC with single output
3.29
138
139
Equivalent circuit of multi-output flyback

ZVS-QRC in six topological stages of a
switching cycle
3.30
Control characteristics of M1 versus f ns for

multi-output flyback ZVS-QRC
3.31
142
Control characteristics of M2 versus f ns for

multi-output flyback ZVS-QRC
3.32(a)
141
143
Waveforms of the simulated resonant capacitor

voltage vC and the gating pulse Vg1 to switch
r
S1.
146
xxix
FIGURE
TITLE
NO.
3.32(b)
PAGE NO.
Waveforms of the simulated resonant inductor

current iL and the gating pulse Vg2 to switch
r
146
S2 .
3.33
Waveforms of the simulated converter output

voltages.
3.34
146
Experimental setup for multi-output flyback

ZVS-QRC.
3.35
148
Resonant capacitor voltage vC
and main
148
switch pulse Vg1

3.36
Resonant capacitor voltage vC and auxiliary

r
149
switch pulse Vg2

3.37
Resonant inductor current iL
and auxiliary
switch pulse Vg2

3.38
Unregulated output voltage Vo1 of secondary1

for 20% step increase in load current Io1
3.39
150
Unregulated output voltage Vo1 of secondary1

for 20% step decrease in load current Io1
3.40
149
150
Power circuit for closed-loop control of

multi-output flyback ZVS-QRC using gating
pulses from UC3861
3.41
152
Unregulated output voltage Vo1 and Vo2 for

20% step increase in load current Io1
153
xxx
FIGURE
TITLE
NO.
3.42
PAGE NO.
Regulated output voltage Vo1 and crossregulated output voltage Vo2 for 20% step
153
increase in load current Io1

3.43

154
20% step increase in load current Io2

3.44
Regulated output voltage Vo1 and crossregulated output voltage Vo2 for 20% step
155
increase in load current Io2

3.45

155
16.6% step decrease in supply voltage

3.46
Regulated output voltage
Vo1 and
cross-
regulated output voltage Vo2 for 16.6% step

decrease in supply voltage
3.47(a)
Load regulation of output voltage Vo1 with

nominal supply voltage
3.47(b)
156
157
Cross-regulation of output voltage Vo2 with

nominal supply voltage
157
3.48
Efficiency of multi-output flyback ZVS-QRC
158
3.49
Circuit configuration of push-pull ZVS-QRC
159
3.50
Theoretical resonant waveforms of upper part

of the push-pull ZVS-QRC
3.51(a)
162
Circuit configuration for stage1 of push-pull

ZVS-QRC
165
xxxi
FIGURE
TITLE
NO.
3.51(b)
PAGE NO.

ZVS-QRC
3.51(c)
165

ZVS-QRC
3.51(d)
166

ZVS-QRC
3.52
166
Simulated resonant waveforms of upper part of

push-pull ZVS-QRC
3.53
168
Simulated resonant waveforms of lower part of

push-pull ZVS-QRC
3.54
169
Simulated output voltage and load current at

nominal operating point.
170
3.55
Experimental setup of push-pull ZVS-QRC.
171
3.56
Power circuit diagram of push-pull ZVS-QRC
172
3.57
Gating pulses generated by UC3861 for S1 and

S2
3.58
172
Experimental
resonant
capacitor
voltage
173
vC and gating pulse Vg1

r1
3.59
Experimental
resonant
capacitor
voltage
173
vC and gating pulse Vg2

r2
3.60
Experimental
resonant
capacitor
vC and resonant inductor current iL

r1
3.61
Experimental
resonant
174
r1
capacitor
vC and resonant inductor current i L

r2
voltage
r2
voltage
174
xxxii
FIGURE
TITLE
PAGE NO.
Response of output voltage of push-pull
175
NO.
3.62
ZVS-QRC
3.63
4.1
Efficiency of push-pull ZVS-QRC.
175
Circuit diagram of buck-boost EP-ZCS /

ZVS-QRC
4.2
Equivalent
180
circuit
of
buck-boost
EP-ZCS/ZVS-QRC in six topological stages of

a switching cycle
4.3
Theoretical
186
resonant
waveforms
of
EP-ZCS / ZVS-QRC
4.4
Characteristics
of
187
M
versus
switching
189
frequency fs with Td3 set to 2 sec

4.5
Characteristics
of
versus
switching
190
frequency fs with Td3 set to zero

4.6
Characteristics of M versus f ns (fs/fo) of

EP-ZCS/ZVS-QRC with different values of R
4.7
Characteristic
of
versus
Td3 / Ts
of
EP-ZCS/ZVS-QRC with different values of R

4.8
191
Simulated resonant waveforms of buck-boost

EP-ZCS/ZVS-QRC
4.9
191
194

increase in load
195
xxxiii
FIGURE
TITLE
NO.
4.10
PAGE NO.

decrease in load
4.11
Process
reaction
195
curve
of
buck-boost
EP-ZCS/ZVS-QRC for a step change in duty

ratio of +8% and 8% with nominal duty ratio
of S1 set at 39.2%
4.12

decrease in load with PI controller
4.13
200

increase in load with PI controller
4.14
198
200
Closed-loop control of buck-boost

EP-ZCS/ZVS-QRC implementing CFLC
202
4.15
Membership functions of e, ce and u
202
4.16
Inference mechanism of CFLC for buck-boost

EP-ZCS/ZVS-QRC
4.17
Closed-loop SIMULINK model of buck-boost

EP-ZCS/ZVS-QRC implementing CFLC
4.18
207

increase in load with CFLC
4.19
205
208

decrease in load with CFLC
208
4.20
Simplified plot of the CFLC rule table
209
4.21
Plot showing calculation of signed distance

( ds )
211
xxxiv
FIGURE
TITLE
NO.
PAGE NO.
4.22
Membership functions of ds and u
213
4.23
Closed-loop SIMULINK diagram of the

converter implementing SFLC
4.24
216

decrease in load current with SFLC
4.25
216

increase in load current with SFLC
4.26
Power
circuit
diagram
217
of
buck-boost
EP-ZCS/ZVS-QRC
218
4.27(a)
Gating pulses to switches S1 and S2
219
4.27(b)
Resonant capacitor voltage of buck-boost

220
EP-ZCS/ZVS-QRC with Vg2

4.27(c)
Resonant inductor current of buck-boost

220
EP-ZCS/ZVS-QRC with Vg1

4.28
Closed-loop
experimental
setup
of
buck-boost EP-ZCS/ZVS-QRC
4.29
Closed-loop
control
of
221
buck-boost
EP-ZCS/ZVS-QRC
4.30(a)

increase in load
4.30(b)
224

increase in load with CFLC
4.30(c)
221
224

increase in load with SFLC
225
xxxv
FIGURE
TITLE
NO.
4.31(a)
PAGE NO.

4.31(b)

increase in supply
4.31(c)
225
voltage with CFLC
226

increase in supply voltage with SFLC
4.32
226
Characteristics of M versus fs with Td3 set to

229
1.74 sec
4.33
Characteristics of M versus fs with Td3 set to

229
zero
4.34
Characteristics of M versus f s / f o for buck230
boost ZVS-QRC with different values of R

4.35
Characteristics of M versus
Td3 / Ts
for
buck-boost ZVS-QRC with different values of

R
4.36
230
Process reaction curve of buck-boost ZVSQRC for a step change in duty ratio of +5%
and 5% with nominal duty ratio of S1 set at
71.4%
233
4.37
Resonant waveforms of buck-boost ZVS-QRC
237
4.38
Unregulated output voltage of buck-boost

ZVS-QRC for 14% step decrease in load
4.39
238
Unregulated output voltage of buck-boost

ZVS-QRC for 18% step increase in load.
238
xxxvi
FIGURE
TITLE
NO.
4.40(a)
PAGE NO.
Regulated output voltage implementing PI

controller for 18% step increase in load
4.40(b)
Regulated output voltage implementing CFLC

for 18% step increase in load
4.40(c)
241
Regulated output voltage implementing SFLC

for 18% step increase in load
4.41(a)
242
Regulated output voltage implementing PI

controller for 14% step decrease in load
4.41(b)
243
Regulated output voltage implementing SFLC

for 14% step decrease in load
4.42
242
Regulated output voltage implementing CFLC

4.41(c)
241
243
Power circuit diagram of buck-boost ZVSQRC
245
4.43
Experimental setup of buck-boost ZVS-QRC
245
4.44
Resonant capacitor voltage ( vC = VDS) and

r
gating pulse to switch S1 ( Vg1 )

4.45
Resonant inductor current ( i Lr ) and gating

pulse to switch S2 ( Vg2 )
4.46(a)
247

increase in load current
4.46(b)
246
249

increase in load current with CFLC
249
xxxvii
FIGURE
TITLE
NO.
4.46(c)
PAGE NO.
Regulated output voltage for 16% change in

load current with SFLC
4.47(a)
250
Unregulated output voltage for 8% (one volt)

step increase in supply voltage
4.47(b)
250
Regulated output voltage for 8% step increase

in supply voltage with CFLC
4.47(c)
251
Regulated output voltage for 8% step increase

in supply voltage with SFLC
5.1
251
Equivalent circuit of multi-output flyback

ZVS-QRC
5.2
254
Response of main and auxiliary output

voltages of GSSA model
5.3
260
Block diagram of forward dynamic modeling

with neural network
5.4
262
Neural network architecture for forward

dynamic modeling
5.5
263
Switching frequency variation with 20%

perturbation around the nominal operating
point of 100 kHz
5.6
Supply
voltage
264
variation
with
16.6%
perturbation around the nominal operating

point of 12V
5.7
265
Filter current variation with 10% perturbation

around the nominal operating point of 2A.
265
xxxviii
FIGURE
TITLE
NO.
5.8
PAGE NO.
Response of main output voltage Vo1 for

266
20% perturbed switching frequency

5.9
Response of auxiliary output voltage Vo2 for

266
20% perturbed switching frequency

5.10
Variation of MSE of forward neural model

during training
5.11
270
Comparison of MSE during training, testing

and validation
5.12
270
Response of main output voltage for forward

neural model, GSSA model and actual
converter output
5.13
SIMULINK
diagram
271
for
validating
the
forward neural model with GSSA model

5.14
271
Validation of main output voltage Vo1 for step

change in switching frequency (fs) from 100 to
120 kHz applied at 5 msec and from 120 to
80 kHz applied at 10 msec
5.15
272

change in supply voltage (Vs) from 12 to 14 V
applied at 5 msec and from 14 to 10V applied
at 10 msec
273
xxxix
FIGURE
TITLE
NO.
5.16
PAGE NO.

change in filter current from 2A to 1.8 A
applied at 5 msec and from 1.8 to 2.2 A
applied at 10 msec
273
5.17
Block diagram of inverse neural modeling
274
5.18
Neural network architecture for inverse model
276
5.19
Variation of MSE of inverse neural model

during training
5.20
277
Comparison of inverse neural model output

(switching frequency fs) with that of GSSA
model input
278
5.21(a)
Block diagram of inverse model control
279
5.21(b)
Block diagram of internal model control
281
5.22
Response of main output voltage under

i) inverse control and
ii) internal model control for set point tracking
5.23
Response of main output voltage with IMC for

20% step decrease in load current
5.24
Waveform
of
the
perturbed
282
switching
frequency
5.25
284
Waveform of the output voltage of the buckboost
EP-ZCS/ZVS-QRC
for
perturbed
switching frequency
5.26
282
284
RLS estimation of buck-boost EP-ZCS/ZVSQRC
285
xl
FIGURE
TITLE
NO.
5.27
Simulated converter output voltage by RLS

estimation
5.28
PAGE NO.
286
RLS model validation for step changes in

switching frequency
287
5.29
Block diagram of ANFIS modeling
288
5.30
Simulated converter output voltage by ANFIS

model
5.31
ANFIS model validation for step changes in

switching frequency
5.32
296
G-K fuzzy model validation for step changes

in switching frequency
5.36
293
Simulated converter output voltage by G-K

model
5.35
292
Block diagram of G-K fuzzy clustering

technique
5.34
290
Formation of membership functions from

fuzzy clustering
5.33
290
296
Formation of membership functions for the

fuzzy model of buck-boost EP-ZCS/ZVS-QRC
with output voltage
5.37
IMC architecture for control of buck-boost

EP-ZCS/ZVS- QRC
5.38
297
298
Regulated output voltage implementing IMC

299
xli
NOMENCLATURE
ADC
Analog to Digital Converter
S2
Auxiliary switch
COG
Centre of Gravity
Change of switching frequency (kHz)
Zo
Characteristic impedance
Cluster center
CF
Constant Frequency
CFLC
Conventional Fuzzy Logic Controller
Vo ,Vo
1
Constant voltage sinks
CCM
Continuous Conduction Mode
CMC
Current Mode Control
Data vector
DC voltage conversion ratio
KD
Derivative gain
Derivative time (msec)
Cf
Dm
Freewheeling diode
iD m
Freewheeling diode current
FM
Frequency Modulation
Vg1
Gating pulse to switch S1
Vg2
Gating pulse to switch S2
G-K
Gustafson-Kessel algorithm
xlii
KI
Integral gain
ISE
Integral Square Error
Integral time (msec)
IMC
Internal Model Control
LM
Levenberg Marquardt algorithm
Io
Load current (A)
Ro
Load resistance (
Zout
Load-to-output transfer function
Lm
Magnetizing inductance ( H)
iL
Magnetizing inductor current (A)
S1
Main switch
K cu
Maximum controller gain
IM
Maximum magnetizing current (A)
MOM
Mean of Maxima
ce
Membership value of change of error
Membership value of error
msec
Millisecond
NN
Neural Network
Normalized load resistance (Ro/Zo)
f ns
Normalized switching frequency (fs/fo)
Number of clusters
Co
Output filter capacitance ( F)
Vo
Output voltage (V)
Kc
Proportional gain
PID
Proportional plus Integral plus Derivative
PWM
Pulse Width Modulation
xliii
QRC
Quasi Resonant Converter
Vo,ref
Reference voltage (V)
Cr
vc r
Resonant capacitor voltage (V)
fo
Resonant frequency (kHz)
Lr
iL
Resonant inductor current (A)
RHP zero
Right Half Plane zero
ds
Signed distance
SFLC
Simple Fuzzy Logic Controller
SMC
Sliding Mode Control

Sliding surface
Vs
Supply voltage (V)
fs
Switching frequency (kHz)
Ts
SMPS
Switch Mode Power Supply

Time constant of RHP zero
Tuning parameter
nk
Turns ratio; k=1,2.
Ku
Ultimate gain
Pu
Ultimate period (sec)
UVLO
Under Voltage Leak Out
VCO
Voltage Controlled Oscillator
VMC
Voltage Mode Control
ZCS
Zero Current Switching
ZVS
Zero Voltage Switching
Z-N
Ziegler-Nichols

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vii

CONTROL OF DC-DC CONVERTER

SOFT SWITCHED CONVERTERS

1.4.1 Analog Resonant Controller

1.4.2 Fuzzy Logic Controller

1.4.3 Model Based Controllers using

OBJECTIVES OF THE THESIS

ORGANISATION OF THE THESIS

DESIGN OF LINEAR AND NONLINEAR

CONVERTER WITH RHP ZERO

ANALYSIS OF DC-DC BOOST

2.3.1 Dynamic Behavior of Boost

2.3.2 Design of Conventional PID

2.3.2.1 Ziegler-Nichols (Z-N)

2.3.2.3 Internal Model Control

2.3.2.4 Synthesis Method

2.3.3 Closed-loop Simulation Results

DESIGN OF CURRENT MODE

DERIVATION OF SLIDING MODE

DERIVATION OF FUZZY SLIDING

2.10.1 Driver Circuit

2.10.2 Overload Protection Circuit

2.10.3 Signal Conditioning Circuit

2.10.4 Pulse Generation

2.10.5 Voltage Control of Boost Converter

2.10.6 Voltage Control of Boost Converter

EFFICIENCY OF BOOST CONVERTER

ANALYSIS, DESIGN AND CONTROL OF

3.2.1 Linear Capacitor Charging Stage

(t0 t < t1)

3.2.3 Holding Stage (t2

3.2.4 Resonant Inductor Charging Stage

3.2.5 Linear Inductor Charging Stage

3.2.6 Constant Current Stage (t5 t<t6)

STEADY STATE CHARACTERISTICS

DESIGN PROCEDURE AND

3.4.1 Simulation Results

3.5.1 Analog Resonant Controller

3.5.1.1 Error Amplifier (E/A) and

3.5.1.2 One Shot Pulse Generator

3.5.1.3 Steering Logic and Output

3.5.1.4 Under Voltage Lockout

3.5.2 Implementation of Proto Type

3.5.2.1 Open-Loop Experimental

3.5.2.2 Closed-Loop Experimental

STEADY STATE CHARACTERISTICS

3.8.1 Control Characteristics

DESIGN PROCEDURE AND

3.9.1 Simulation Results

ANALYSIS OF PUSH-PULL ZVS-QRC

3.11.1 Linear Capacitor Charging

3.11.2 Resonant Inductor Discharging

3.11.3 Linear Inductor Charging Stage

DESIGN PROCEDURE OF PUSH-PULL

SIMPLE FUZZY LOGIC CONTROLLER

4.2.1 Linear Inductor Charging Stage

4.2.2 Resonant Capacitor Charging Stage

4.2.4 Resonant Inductor Discharging

4.2.5 Linear Capacitor Discharging Stage

STEADY STATE CHARACTERISTICS

DESIGN PROCEDURE AND

4.4.1 Design Example

4.4.2 Simulation Results of Buck-Boost

4.5.1 Design of PI Controller